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0011-v6.2-clk-qcom-ipq8074-populate-fw_name-for-all-parents.patch

0011-v6.2-clk-qcom-ipq8074-populate-fw_name-for-all-parents.patch 6.1 KB
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  1. From 78936d46470938caa9a7ea529deeb36777b4f98e Mon Sep 17 00:00:00 2001
    2. 

  2. From: Robert Marko <[email protected]>
    3. 

  3. Date: Wed, 16 Nov 2022 22:46:55 +0100
    4. 

  4. Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for all parents
    5. 

  5. 

  6. It appears that having only .name populated in parent_data for clocks
    7. 

  7. which are only globally searchable currently will not work as the clk core
    8. 

  8. won't copy that name if there is no .fw_name present as well.
    9. 

  9. 

  10. So, populate .fw_name for all parent clocks in parent_data.
    11. 

  11. 

  12. Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
    13. 

  13. 

  14. Co-developed-by: Christian Marangi <[email protected]>
    15. 

  15. Signed-off-by: Christian Marangi <[email protected]>
    16. 

  16. Signed-off-by: Robert Marko <[email protected]>
    17. 

  17. Signed-off-by: Bjorn Andersson <[email protected]>
    18. 

  18. Link: https://lore.kernel.org/r/[email protected]
    19. 

  19. ---
    20. 

  20.  drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++-----------------
    21. 

  21.  1 file changed, 26 insertions(+), 26 deletions(-)
    22. 

  22. 

  23. --- a/drivers/clk/qcom/gcc-ipq8074.c
    24. 

  24. +++ b/drivers/clk/qcom/gcc-ipq8074.c
    25. 

  25. @@ -674,7 +674,7 @@ static struct clk_rcg2 pcie0_aux_clk_src
    26. 

  26.  };
    27. 

  27.  
    28. 

  28.  static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
    29. 

  29. -	{ .name = "pcie20_phy0_pipe_clk" },
    30. 

  30. +	{ .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
    31. 

  31.  	{ .fw_name = "xo", .name = "xo" },
    32. 

  32.  };
    33. 

  33.  
    34. 

  34. @@ -727,7 +727,7 @@ static struct clk_rcg2 pcie1_aux_clk_src
    35. 

  35.  };
    36. 

  36.  
    37. 

  37.  static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
    38. 

  38. -	{ .name = "pcie20_phy1_pipe_clk" },
    39. 

  39. +	{ .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
    40. 

  40.  	{ .fw_name = "xo", .name = "xo" },
    41. 

  41.  };
    42. 

  42.  
    43. 

  43. @@ -1131,7 +1131,7 @@ static const struct freq_tbl ftbl_nss_no
    44. 

  44.  
    45. 

  45.  static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
    46. 

  46.  	{ .fw_name = "xo", .name = "xo" },
    47. 

  47. -	{ .name = "bias_pll_nss_noc_clk" },
    48. 

  48. +	{ .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
    49. 

  49.  	{ .hw = &gpll0.clkr.hw },
    50. 

  50.  	{ .hw = &gpll2.clkr.hw },
    51. 

  51.  };
    52. 

  52. @@ -1356,7 +1356,7 @@ static const struct freq_tbl ftbl_nss_pp
    53. 

  53.  
    54. 

  54.  static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
    55. 

  55.  	{ .fw_name = "xo", .name = "xo" },
    56. 

  56. -	{ .name = "bias_pll_cc_clk" },
    57. 

  57. +	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
    58. 

  58.  	{ .hw = &gpll0.clkr.hw },
    59. 

  59.  	{ .hw = &gpll4.clkr.hw },
    60. 

  60.  	{ .hw = &nss_crypto_pll.clkr.hw },
    61. 

  61. @@ -1407,10 +1407,10 @@ static const struct freq_tbl ftbl_nss_po
    62. 

  62.  
    63. 

  63.  static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
    64. 

  64.  	{ .fw_name = "xo", .name = "xo" },
    65. 

  65. -	{ .name = "uniphy0_gcc_rx_clk" },
    66. 

  66. -	{ .name = "uniphy0_gcc_tx_clk" },
    67. 

  67. +	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
    68. 

  68. +	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
    69. 

  69.  	{ .hw = &ubi32_pll.clkr.hw },
    70. 

  70. -	{ .name = "bias_pll_cc_clk" },
    71. 

  71. +	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
    72. 

  72.  };
    73. 

  73.  
    74. 

  74.  static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
    75. 

  75. @@ -1459,10 +1459,10 @@ static const struct freq_tbl ftbl_nss_po
    76. 

  76.  
    77. 

  77.  static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
    78. 

  78.  	{ .fw_name = "xo", .name = "xo" },
    79. 

  79. -	{ .name = "uniphy0_gcc_tx_clk" },
    80. 

  80. -	{ .name = "uniphy0_gcc_rx_clk" },
    81. 

  81. +	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
    82. 

  82. +	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
    83. 

  83.  	{ .hw = &ubi32_pll.clkr.hw },
    84. 

  84. -	{ .name = "bias_pll_cc_clk" },
    85. 

  85. +	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
    86. 

  86.  };
    87. 

  87.  
    88. 

  88.  static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
    89. 

  89. @@ -1690,12 +1690,12 @@ static const struct freq_tbl ftbl_nss_po
    90. 

  90.  
    91. 

  91.  static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
    92. 

  92.  	{ .fw_name = "xo", .name = "xo" },
    93. 

  93. -	{ .name = "uniphy0_gcc_rx_clk" },
    94. 

  94. -	{ .name = "uniphy0_gcc_tx_clk" },
    95. 

  95. -	{ .name = "uniphy1_gcc_rx_clk" },
    96. 

  96. -	{ .name = "uniphy1_gcc_tx_clk" },
    97. 

  97. +	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
    98. 

  98. +	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
    99. 

  99. +	{ .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
    100. 

  100. +	{ .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
    101. 

  101.  	{ .hw = &ubi32_pll.clkr.hw },
    102. 

  102. -	{ .name = "bias_pll_cc_clk" },
    103. 

  103. +	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
    104. 

  104.  };
    105. 

  105.  
    106. 

  106.  static const struct parent_map
    107. 

  107. @@ -1752,12 +1752,12 @@ static const struct freq_tbl ftbl_nss_po
    108. 

  108.  
    109. 

  109.  static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
    110. 

  110.  	{ .fw_name = "xo", .name = "xo" },
    111. 

  111. -	{ .name = "uniphy0_gcc_tx_clk" },
    112. 

  112. -	{ .name = "uniphy0_gcc_rx_clk" },
    113. 

  113. -	{ .name = "uniphy1_gcc_tx_clk" },
    114. 

  114. -	{ .name = "uniphy1_gcc_rx_clk" },
    115. 

  115. +	{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
    116. 

  116. +	{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
    117. 

  117. +	{ .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
    118. 

  118. +	{ .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
    119. 

  119.  	{ .hw = &ubi32_pll.clkr.hw },
    120. 

  120. -	{ .name = "bias_pll_cc_clk" },
    121. 

  121. +	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
    122. 

  122.  };
    123. 

  123.  
    124. 

  124.  static const struct parent_map
    125. 

  125. @@ -1814,10 +1814,10 @@ static const struct freq_tbl ftbl_nss_po
    126. 

  126.  
    127. 

  127.  static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
    128. 

  128.  	{ .fw_name = "xo", .name = "xo" },
    129. 

  129. -	{ .name = "uniphy2_gcc_rx_clk" },
    130. 

  130. -	{ .name = "uniphy2_gcc_tx_clk" },
    131. 

  131. +	{ .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
    132. 

  132. +	{ .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
    133. 

  133.  	{ .hw = &ubi32_pll.clkr.hw },
    134. 

  134. -	{ .name = "bias_pll_cc_clk" },
    135. 

  135. +	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
    136. 

  136.  };
    137. 

  137.  
    138. 

  138.  static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
    139. 

  139. @@ -1871,10 +1871,10 @@ static const struct freq_tbl ftbl_nss_po
    140. 

  140.  
    141. 

  141.  static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
    142. 

  142.  	{ .fw_name = "xo", .name = "xo" },
    143. 

  143. -	{ .name = "uniphy2_gcc_tx_clk" },
    144. 

  144. -	{ .name = "uniphy2_gcc_rx_clk" },
    145. 

  145. +	{ .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
    146. 

  146. +	{ .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
    147. 

  147.  	{ .hw = &ubi32_pll.clkr.hw },
    148. 

  148. -	{ .name = "bias_pll_cc_clk" },
    149. 

  149. +	{ .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
    150. 

  150.  };
    151. 

  151.  
    152. 

  152.  static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
    153.