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- From 9a0e95e34e9c0a713ddfd48c3a88a20d2bdfd514 Mon Sep 17 00:00:00 2001
- From: Gabor Juhos <[email protected]>
- Date: Fri, 11 Aug 2023 13:10:07 +0200
- Subject: [PATCH] net: phy: Introduce PSGMII PHY interface mode
- The PSGMII interface is similar to QSGMII. The main difference
- is that the PSGMII interface combines five SGMII lines into a
- single link while in QSGMII only four lines are combined.
- Similarly to the QSGMII, this interface mode might also needs
- special handling within the MAC driver.
- It is commonly used by Qualcomm with their QCA807x PHY series and
- modern WiSoC-s.
- Add definitions for the PHY layer to allow to express this type
- of connection between the MAC and PHY.
- Signed-off-by: Gabor Juhos <[email protected]>
- Signed-off-by: Robert Marko <[email protected]>
- Signed-off-by: David S. Miller <[email protected]>
- ---
- Documentation/networking/phy.rst | 4 ++++
- drivers/net/phy/phy-core.c | 2 ++
- drivers/net/phy/phylink.c | 3 +++
- include/linux/phy.h | 4 ++++
- 4 files changed, 13 insertions(+)
- --- a/Documentation/networking/phy.rst
- +++ b/Documentation/networking/phy.rst
- @@ -323,6 +323,10 @@ Some of the interface modes are describe
- contrast with the 1000BASE-X phy mode used for Clause 38 and 39 PMDs, this
- interface mode has different autonegotiation and only supports full duplex.
-
- +``PHY_INTERFACE_MODE_PSGMII``
- + This is the Penta SGMII mode, it is similar to QSGMII but it combines 5
- + SGMII lines into a single link compared to 4 on QSGMII.
- +
- Pause frames / flow control
- ===========================
-
- --- a/drivers/net/phy/phy-core.c
- +++ b/drivers/net/phy/phy-core.c
- @@ -140,6 +140,8 @@ int phy_interface_num_ports(phy_interfac
- case PHY_INTERFACE_MODE_QSGMII:
- case PHY_INTERFACE_MODE_QUSGMII:
- return 4;
- + case PHY_INTERFACE_MODE_PSGMII:
- + return 5;
- case PHY_INTERFACE_MODE_MAX:
- WARN_ONCE(1, "PHY_INTERFACE_MODE_MAX isn't a valid interface mode");
- return 0;
- --- a/drivers/net/phy/phylink.c
- +++ b/drivers/net/phy/phylink.c
- @@ -187,6 +187,7 @@ static int phylink_interface_max_speed(p
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII:
- + case PHY_INTERFACE_MODE_PSGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- case PHY_INTERFACE_MODE_QUSGMII:
- case PHY_INTERFACE_MODE_SGMII:
- @@ -448,6 +449,7 @@ unsigned long phylink_get_capabilities(p
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII:
- + case PHY_INTERFACE_MODE_PSGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- case PHY_INTERFACE_MODE_QUSGMII:
- case PHY_INTERFACE_MODE_SGMII:
- @@ -814,6 +816,7 @@ static int phylink_parse_mode(struct phy
-
- switch (pl->link_config.interface) {
- case PHY_INTERFACE_MODE_SGMII:
- + case PHY_INTERFACE_MODE_PSGMII:
- case PHY_INTERFACE_MODE_QSGMII:
- case PHY_INTERFACE_MODE_QUSGMII:
- case PHY_INTERFACE_MODE_RGMII:
- --- a/include/linux/phy.h
- +++ b/include/linux/phy.h
- @@ -103,6 +103,7 @@ extern const int phy_10gbit_features_arr
- * @PHY_INTERFACE_MODE_XGMII: 10 gigabit media-independent interface
- * @PHY_INTERFACE_MODE_XLGMII:40 gigabit media-independent interface
- * @PHY_INTERFACE_MODE_MOCA: Multimedia over Coax
- + * @PHY_INTERFACE_MODE_PSGMII: Penta SGMII
- * @PHY_INTERFACE_MODE_QSGMII: Quad SGMII
- * @PHY_INTERFACE_MODE_TRGMII: Turbo RGMII
- * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX
- @@ -140,6 +141,7 @@ typedef enum {
- PHY_INTERFACE_MODE_XGMII,
- PHY_INTERFACE_MODE_XLGMII,
- PHY_INTERFACE_MODE_MOCA,
- + PHY_INTERFACE_MODE_PSGMII,
- PHY_INTERFACE_MODE_QSGMII,
- PHY_INTERFACE_MODE_TRGMII,
- PHY_INTERFACE_MODE_100BASEX,
- @@ -247,6 +249,8 @@ static inline const char *phy_modes(phy_
- return "xlgmii";
- case PHY_INTERFACE_MODE_MOCA:
- return "moca";
- + case PHY_INTERFACE_MODE_PSGMII:
- + return "psgmii";
- case PHY_INTERFACE_MODE_QSGMII:
- return "qsgmii";
- case PHY_INTERFACE_MODE_TRGMII:
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