qcom-ipq4018-jalapeno.dtsi 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. // Copyright (c) 2018, Robert Marko <[email protected]>
  3. #include "qcom-ipq4019.dtsi"
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/soc/qcom,tcsr.h>
  7. / {
  8. soc {
  9. rng@22000 {
  10. status = "okay";
  11. };
  12. mdio@90000 {
  13. status = "okay";
  14. pinctrl-0 = <&mdio_pins>;
  15. pinctrl-names = "default";
  16. };
  17. ess-psgmii@98000 {
  18. status = "okay";
  19. };
  20. counter@4a1000 {
  21. compatible = "qcom,qca-gcnt";
  22. reg = <0x4a1000 0x4>;
  23. };
  24. tcsr@1949000 {
  25. compatible = "qcom,tcsr";
  26. reg = <0x1949000 0x100>;
  27. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  28. };
  29. tcsr@194b000 {
  30. status = "okay";
  31. compatible = "qcom,tcsr";
  32. reg = <0x194b000 0x100>;
  33. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  34. };
  35. ess_tcsr@1953000 {
  36. compatible = "qcom,tcsr";
  37. reg = <0x1953000 0x1000>;
  38. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  39. };
  40. tcsr@1957000 {
  41. compatible = "qcom,tcsr";
  42. reg = <0x1957000 0x100>;
  43. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  44. };
  45. usb2: usb2@60f8800 {
  46. status = "okay";
  47. };
  48. usb3: usb3@8af8800 {
  49. status = "okay";
  50. };
  51. crypto@8e3a000 {
  52. status = "okay";
  53. };
  54. watchdog@b017000 {
  55. status = "okay";
  56. };
  57. ess-switch@c000000 {
  58. status = "okay";
  59. switch_lan_bmp = <0x10>; /* lan port bitmap */
  60. };
  61. edma@c080000 {
  62. status = "okay";
  63. };
  64. };
  65. };
  66. &tlmm {
  67. mdio_pins: mdio_pinmux {
  68. pinmux_1 {
  69. pins = "gpio53";
  70. function = "mdio";
  71. };
  72. pinmux_2 {
  73. pins = "gpio52";
  74. function = "mdc";
  75. };
  76. pinconf {
  77. pins = "gpio52", "gpio53";
  78. bias-pull-up;
  79. };
  80. };
  81. serial_pins: serial_pinmux {
  82. mux {
  83. pins = "gpio60", "gpio61";
  84. function = "blsp_uart0";
  85. bias-disable;
  86. };
  87. };
  88. spi_0_pins: spi_0_pinmux {
  89. pin {
  90. function = "blsp_spi0";
  91. pins = "gpio55", "gpio56", "gpio57";
  92. drive-strength = <2>;
  93. bias-disable;
  94. };
  95. pin_cs {
  96. function = "gpio";
  97. pins = "gpio54", "gpio59";
  98. drive-strength = <2>;
  99. bias-disable;
  100. output-high;
  101. };
  102. };
  103. };
  104. &blsp_dma {
  105. status = "okay";
  106. };
  107. &blsp1_spi1 {
  108. status = "okay";
  109. pinctrl-0 = <&spi_0_pins>;
  110. pinctrl-names = "default";
  111. cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
  112. flash@0 {
  113. status = "okay";
  114. compatible = "jedec,spi-nor";
  115. reg = <0>;
  116. spi-max-frequency = <24000000>;
  117. partitions {
  118. compatible = "fixed-partitions";
  119. #address-cells = <1>;
  120. #size-cells = <1>;
  121. partition@0 {
  122. label = "SBL1";
  123. reg = <0x00000000 0x00040000>;
  124. read-only;
  125. };
  126. partition@40000 {
  127. label = "MIBIB";
  128. reg = <0x00040000 0x00020000>;
  129. read-only;
  130. };
  131. partition@60000 {
  132. label = "QSEE";
  133. reg = <0x00060000 0x00060000>;
  134. read-only;
  135. };
  136. partition@c0000 {
  137. label = "CDT";
  138. reg = <0x000c0000 0x00010000>;
  139. read-only;
  140. };
  141. partition@d0000 {
  142. label = "DDRPARAMS";
  143. reg = <0x000d0000 0x00010000>;
  144. read-only;
  145. };
  146. partition@e0000 {
  147. label = "APPSBLENV"; /* uboot env*/
  148. reg = <0x000e0000 0x00010000>;
  149. read-only;
  150. };
  151. partition@f0000 {
  152. label = "APPSBL"; /* uboot */
  153. reg = <0x000f0000 0x00080000>;
  154. read-only;
  155. };
  156. partition@170000 {
  157. label = "ART";
  158. reg = <0x00170000 0x00010000>;
  159. read-only;
  160. };
  161. };
  162. };
  163. spi-nand@1 {
  164. status = "okay";
  165. compatible = "spi-nand";
  166. reg = <1>;
  167. spi-max-frequency = <24000000>;
  168. partitions {
  169. compatible = "fixed-partitions";
  170. #address-cells = <1>;
  171. #size-cells = <1>;
  172. partition@0 {
  173. label = "ubi";
  174. reg = <0x00000000 0x08000000>;
  175. };
  176. };
  177. };
  178. };
  179. &blsp1_uart1 {
  180. status = "okay";
  181. pinctrl-0 = <&serial_pins>;
  182. pinctrl-names = "default";
  183. };
  184. &cryptobam {
  185. status = "okay";
  186. };
  187. &gmac0 {
  188. qcom,poll_required = <1>;
  189. qcom,poll_required_dynamic = <1>;
  190. qcom,phy_mdio_addr = <3>;
  191. vlan_tag = <1 0x10>;
  192. };
  193. &gmac1 {
  194. qcom,poll_required = <1>;
  195. qcom,poll_required_dynamic = <1>;
  196. qcom,phy_mdio_addr = <4>;
  197. vlan_tag = <2 0x20>;
  198. };
  199. &wifi0 {
  200. status = "okay";
  201. qcom,ath10k-calibration-variant = "8devices-Jalapeno";
  202. };
  203. &wifi1 {
  204. status = "okay";
  205. qcom,ath10k-calibration-variant = "8devices-Jalapeno";
  206. };
  207. &usb3_ss_phy {
  208. status = "okay";
  209. };
  210. &usb3_hs_phy {
  211. status = "okay";
  212. };
  213. &usb2_hs_phy {
  214. status = "okay";
  215. };