qcom-ipq8064-ap148.dts 4.3 KB

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  1. #include "qcom-ipq8064-v1.0.dtsi"
  2. / {
  3. model = "Qualcomm IPQ8064/AP148";
  4. compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
  5. memory@0 {
  6. reg = <0x42000000 0x1e000000>;
  7. device_type = "memory";
  8. };
  9. reserved-memory {
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. ranges;
  13. rsvd@41200000 {
  14. reg = <0x41200000 0x300000>;
  15. no-map;
  16. };
  17. };
  18. aliases {
  19. serial0 = &gsbi4_serial;
  20. mdio-gpio0 = &mdio0;
  21. };
  22. chosen {
  23. stdout-path = "serial0:115200n8";
  24. };
  25. soc {
  26. pinmux@800000 {
  27. i2c4_pins: i2c4_pinmux {
  28. pins = "gpio12", "gpio13";
  29. function = "gsbi4";
  30. bias-disable;
  31. };
  32. spi_pins: spi_pins {
  33. mux {
  34. pins = "gpio18", "gpio19", "gpio21";
  35. function = "gsbi5";
  36. drive-strength = <10>;
  37. bias-none;
  38. };
  39. };
  40. nand_pins: nand_pins {
  41. mux {
  42. pins = "gpio34", "gpio35", "gpio36",
  43. "gpio37", "gpio38", "gpio39",
  44. "gpio40", "gpio41", "gpio42",
  45. "gpio43", "gpio44", "gpio45",
  46. "gpio46", "gpio47";
  47. function = "nand";
  48. drive-strength = <10>;
  49. bias-disable;
  50. };
  51. pullups {
  52. pins = "gpio39";
  53. bias-pull-up;
  54. };
  55. hold {
  56. pins = "gpio40", "gpio41", "gpio42",
  57. "gpio43", "gpio44", "gpio45",
  58. "gpio46", "gpio47";
  59. bias-bus-hold;
  60. };
  61. };
  62. mdio0_pins: mdio0_pins {
  63. mux {
  64. pins = "gpio0", "gpio1";
  65. function = "gpio";
  66. drive-strength = <8>;
  67. bias-disable;
  68. };
  69. };
  70. rgmii2_pins: rgmii2_pins {
  71. mux {
  72. pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
  73. "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
  74. function = "rgmii2";
  75. drive-strength = <8>;
  76. bias-disable;
  77. };
  78. };
  79. };
  80. gsbi@16300000 {
  81. qcom,mode = <GSBI_PROT_I2C_UART>;
  82. status = "ok";
  83. serial@16340000 {
  84. status = "ok";
  85. };
  86. /*
  87. * The i2c device on gsbi4 should not be enabled.
  88. * On ipq806x designs gsbi4 i2c is meant for exclusive
  89. * RPM usage. Turning this on in kernel manifests as
  90. * i2c failure for the RPM.
  91. */
  92. };
  93. gsbi5: gsbi@1a200000 {
  94. qcom,mode = <GSBI_PROT_SPI>;
  95. status = "ok";
  96. spi4: spi@1a280000 {
  97. status = "ok";
  98. spi-max-frequency = <50000000>;
  99. pinctrl-0 = <&spi_pins>;
  100. pinctrl-names = "default";
  101. cs-gpios = <&qcom_pinmux 20 0>;
  102. flash: m25p80@0 {
  103. compatible = "s25fl256s1";
  104. #address-cells = <1>;
  105. #size-cells = <1>;
  106. spi-max-frequency = <50000000>;
  107. reg = <0>;
  108. partitions {
  109. compatible = "qcom,smem";
  110. };
  111. };
  112. };
  113. };
  114. sata-phy@1b400000 {
  115. status = "ok";
  116. };
  117. sata@29000000 {
  118. status = "ok";
  119. };
  120. phy@100f8800 { /* USB3 port 1 HS phy */
  121. status = "ok";
  122. };
  123. phy@100f8830 { /* USB3 port 1 SS phy */
  124. status = "ok";
  125. };
  126. phy@110f8800 { /* USB3 port 0 HS phy */
  127. status = "ok";
  128. };
  129. phy@110f8830 { /* USB3 port 0 SS phy */
  130. status = "ok";
  131. };
  132. usb30@0 {
  133. status = "ok";
  134. };
  135. usb30@1 {
  136. status = "ok";
  137. };
  138. pcie0: pci@1b500000 {
  139. status = "ok";
  140. };
  141. pcie1: pci@1b700000 {
  142. status = "ok";
  143. force_gen1 = <1>;
  144. };
  145. nand@1ac00000 {
  146. status = "ok";
  147. pinctrl-0 = <&nand_pins>;
  148. pinctrl-names = "default";
  149. cs0 {
  150. reg = <0>;
  151. compatible = "qcom,nandcs";
  152. nand-ecc-strength = <4>;
  153. nand-bus-width = <8>;
  154. nand-ecc-step-size = <512>;
  155. partitions {
  156. compatible = "qcom,smem";
  157. };
  158. };
  159. };
  160. mdio0: mdio {
  161. compatible = "virtual,mdio-gpio";
  162. #address-cells = <1>;
  163. #size-cells = <0>;
  164. gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>;
  165. pinctrl-0 = <&mdio0_pins>;
  166. pinctrl-names = "default";
  167. phy0: ethernet-phy@0 {
  168. reg = <0>;
  169. qca,ar8327-initvals = <
  170. 0x00004 0x7600000 /* PAD0_MODE */
  171. 0x00008 0x1000000 /* PAD5_MODE */
  172. 0x0000c 0x80 /* PAD6_MODE */
  173. 0x000e4 0x6a545 /* MAC_POWER_SEL */
  174. 0x000e0 0xc74164de /* SGMII_CTRL */
  175. 0x0007c 0x4e /* PORT0_STATUS */
  176. 0x00094 0x4e /* PORT6_STATUS */
  177. >;
  178. };
  179. phy4: ethernet-phy@4 {
  180. reg = <4>;
  181. };
  182. };
  183. gmac1: ethernet@37200000 {
  184. status = "ok";
  185. phy-mode = "rgmii";
  186. qcom,id = <1>;
  187. pinctrl-0 = <&rgmii2_pins>;
  188. pinctrl-names = "default";
  189. fixed-link {
  190. speed = <1000>;
  191. full-duplex;
  192. };
  193. };
  194. gmac2: ethernet@37400000 {
  195. status = "ok";
  196. phy-mode = "sgmii";
  197. qcom,id = <2>;
  198. fixed-link {
  199. speed = <1000>;
  200. full-duplex;
  201. };
  202. };
  203. };
  204. };
  205. &adm_dma {
  206. status = "ok";
  207. };