qcom-ipq8064-ap161.dts 3.0 KB

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  1. #include "qcom-ipq8064-v1.0.dtsi"
  2. / {
  3. model = "Qualcomm IPQ8064/AP161";
  4. compatible = "qcom,ipq8064-ap161", "qcom,ipq8064";
  5. memory@0 {
  6. reg = <0x42000000 0x1e000000>;
  7. device_type = "memory";
  8. };
  9. reserved-memory {
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. ranges;
  13. rsvd@41200000 {
  14. reg = <0x41200000 0x300000>;
  15. no-map;
  16. };
  17. };
  18. aliases {
  19. mdio-gpio0 = &mdio0;
  20. };
  21. };
  22. &qcom_pinmux {
  23. rgmii2_pins: rgmii2_pins {
  24. mux {
  25. pins = "gpio27", "gpio28", "gpio29",
  26. "gpio30", "gpio31", "gpio32",
  27. "gpio51", "gpio52", "gpio59",
  28. "gpio60", "gpio61", "gpio62",
  29. "gpio2", "gpio66";
  30. };
  31. };
  32. };
  33. &gsbi4 {
  34. qcom,mode = <GSBI_PROT_I2C_UART>;
  35. status = "okay";
  36. serial@16340000 {
  37. status = "okay";
  38. };
  39. /*
  40. * The i2c device on gsbi4 should not be enabled.
  41. * On ipq806x designs gsbi4 i2c is meant for exclusive
  42. * RPM usage. Turning this on in kernel manifests as
  43. * i2c failure for the RPM.
  44. */
  45. };
  46. &gsbi5 {
  47. qcom,mode = <GSBI_PROT_SPI>;
  48. status = "okay";
  49. spi4: spi@1a280000 {
  50. status = "okay";
  51. spi-max-frequency = <50000000>;
  52. pinctrl-0 = <&spi_pins>;
  53. pinctrl-names = "default";
  54. cs-gpios = <&qcom_pinmux 20 0>;
  55. m25p80@0 {
  56. compatible = "s25fl256s1";
  57. #address-cells = <1>;
  58. #size-cells = <1>;
  59. spi-max-frequency = <50000000>;
  60. reg = <0>;
  61. partitions {
  62. compatible = "qcom,smem";
  63. };
  64. };
  65. };
  66. };
  67. &sata_phy {
  68. status = "okay";
  69. };
  70. &sata {
  71. status = "okay";
  72. };
  73. &usb3_0 {
  74. status = "okay";
  75. };
  76. &usb3_1 {
  77. status = "okay";
  78. };
  79. &pcie0 {
  80. status = "okay";
  81. };
  82. &pcie1 {
  83. status = "okay";
  84. force_gen1 = <1>;
  85. };
  86. &pcie2 {
  87. status = "okay";
  88. };
  89. &nand_controller {
  90. status = "okay";
  91. pinctrl-0 = <&nand_pins>;
  92. pinctrl-names = "default";
  93. nand@0 {
  94. reg = <0>;
  95. compatible = "qcom,nandcs";
  96. nand-ecc-strength = <4>;
  97. nand-bus-width = <8>;
  98. nand-ecc-step-size = <512>;
  99. partitions {
  100. compatible = "qcom,smem";
  101. };
  102. };
  103. };
  104. &mdio0 {
  105. status = "okay";
  106. pinctrl-0 = <&mdio0_pins>;
  107. pinctrl-names = "default";
  108. phy0: ethernet-phy@0 {
  109. reg = <0>;
  110. qca,ar8327-initvals = <
  111. 0x00004 0x7600000 /* PAD0_MODE */
  112. 0x00008 0x1000000 /* PAD5_MODE */
  113. 0x0000c 0x20080 /* PAD6_MODE */
  114. 0x000e4 0x6a545 /* MAC_POWER_SEL */
  115. 0x000e0 0xc74164de /* SGMII_CTRL */
  116. 0x0007c 0x4e /* PORT0_STATUS */
  117. 0x00094 0x4e /* PORT6_STATUS */
  118. >;
  119. };
  120. phy4: ethernet-phy@4 {
  121. reg = <4>;
  122. qca,phy-rgmii-en;
  123. qca,txclk-delay-en;
  124. qca,rxclk-delay-en;
  125. };
  126. phy3: ethernet-phy@3 {
  127. device_type = "ethernet-phy";
  128. reg = <3>;
  129. };
  130. };
  131. &gmac0 {
  132. status = "okay";
  133. phy-mode = "rgmii";
  134. qcom,id = <0>;
  135. pinctrl-0 = <&rgmii2_pins>;
  136. pinctrl-names = "default";
  137. mdiobus = <&mdio0>;
  138. fixed-link {
  139. speed = <1000>;
  140. full-duplex;
  141. };
  142. };
  143. &gmac1 {
  144. status = "okay";
  145. phy-mode = "rgmii";
  146. qcom,id = <1>;
  147. mdiobus = <&mdio0>;
  148. fixed-link {
  149. speed = <1000>;
  150. full-duplex;
  151. };
  152. };
  153. &gmac2 {
  154. status = "okay";
  155. phy-mode = "sgmii";
  156. qcom,id = <2>;
  157. mdiobus = <&mdio0>;
  158. fixed-link {
  159. speed = <1000>;
  160. full-duplex;
  161. };
  162. };
  163. &adm_dma {
  164. status = "okay";
  165. };