qcom-ipq8064-db149.dts 2.5 KB

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  1. #include "qcom-ipq8064-v1.0.dtsi"
  2. / {
  3. model = "Qualcomm IPQ8064/DB149";
  4. compatible = "qcom,ipq8064-db149", "qcom,ipq8064";
  5. reserved-memory {
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. ranges;
  9. rsvd@41200000 {
  10. reg = <0x41200000 0x300000>;
  11. no-map;
  12. };
  13. };
  14. };
  15. &qcom_pinmux {
  16. rgmii0_pins: rgmii0_pins {
  17. mux {
  18. pins = "gpio2", "gpio66";
  19. drive-strength = <8>;
  20. bias-disable;
  21. };
  22. };
  23. };
  24. &gsbi2 {
  25. qcom,mode = <GSBI_PROT_I2C_UART>;
  26. status = "okay";
  27. uart2: serial@12490000 {
  28. status = "okay";
  29. };
  30. };
  31. &gsbi5 {
  32. qcom,mode = <GSBI_PROT_SPI>;
  33. status = "okay";
  34. spi4: spi@1a280000 {
  35. status = "okay";
  36. spi-max-frequency = <50000000>;
  37. pinctrl-0 = <&spi_pins>;
  38. pinctrl-names = "default";
  39. cs-gpios = <&qcom_pinmux 20 0>;
  40. m25p80@0 {
  41. compatible = "s25fl256s1";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. spi-max-frequency = <50000000>;
  45. reg = <0>;
  46. m25p,fast-read;
  47. partition@0 {
  48. label = "lowlevel_init";
  49. reg = <0x0 0x1b0000>;
  50. };
  51. partition@1 {
  52. label = "u-boot";
  53. reg = <0x1b0000 0x80000>;
  54. };
  55. partition@2 {
  56. label = "u-boot-env";
  57. reg = <0x230000 0x40000>;
  58. };
  59. partition@3 {
  60. label = "caldata";
  61. reg = <0x270000 0x40000>;
  62. };
  63. partition@4 {
  64. label = "firmware";
  65. reg = <0x2b0000 0x1d50000>;
  66. };
  67. };
  68. };
  69. };
  70. &sata_phy {
  71. status = "okay";
  72. };
  73. &sata {
  74. status = "okay";
  75. };
  76. &usb3_0 {
  77. status = "okay";
  78. };
  79. &usb3_1 {
  80. status = "okay";
  81. };
  82. &pcie0 {
  83. status = "okay";
  84. };
  85. &pcie1 {
  86. status = "okay";
  87. };
  88. &pcie2 {
  89. status = "okay";
  90. };
  91. &mdio0 {
  92. status = "okay";
  93. pinctrl-0 = <&mdio0_pins>;
  94. pinctrl-names = "default";
  95. phy0: ethernet-phy@0 {
  96. reg = <0>;
  97. qca,ar8327-initvals = <
  98. 0x00004 0x7600000 /* PAD0_MODE */
  99. 0x00008 0x1000000 /* PAD5_MODE */
  100. 0x0000c 0x80 /* PAD6_MODE */
  101. 0x000e4 0x6a545 /* MAC_POWER_SEL */
  102. 0x000e0 0xc74164de /* SGMII_CTRL */
  103. 0x0007c 0x4e /* PORT0_STATUS */
  104. 0x00094 0x4e /* PORT6_STATUS */
  105. >;
  106. };
  107. phy4: ethernet-phy@4 {
  108. reg = <4>;
  109. };
  110. phy6: ethernet-phy@6 {
  111. reg = <6>;
  112. };
  113. phy7: ethernet-phy@7 {
  114. reg = <7>;
  115. };
  116. };
  117. &gmac0 {
  118. status = "okay";
  119. phy-mode = "rgmii";
  120. qcom,id = <0>;
  121. phy-handle = <&phy4>;
  122. pinctrl-0 = <&rgmii0_pins>;
  123. pinctrl-names = "default";
  124. };
  125. &gmac1 {
  126. status = "okay";
  127. phy-mode = "sgmii";
  128. qcom,id = <1>;
  129. fixed-link {
  130. speed = <1000>;
  131. full-duplex;
  132. };
  133. };
  134. &gmac2 {
  135. status = "okay";
  136. phy-mode = "sgmii";
  137. qcom,id = <2>;
  138. phy-handle = <&phy6>;
  139. };
  140. &gmac3 {
  141. status = "okay";
  142. phy-mode = "sgmii";
  143. qcom,id = <3>;
  144. phy-handle = <&phy7>;
  145. };