mt7620a_head-weblink_hdrm200.dts 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "mt7620a.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. / {
  6. compatible = "head-weblink,hdrm200", "ralink,mt7620a-soc";
  7. model = "Head Weblink HDRM200";
  8. aliases {
  9. led-boot = &led_system;
  10. led-failsafe = &led_system;
  11. led-running = &led_system;
  12. led-upgrade = &led_system;
  13. };
  14. chosen {
  15. bootargs = "console=ttyS1,57600";
  16. };
  17. leds {
  18. compatible = "gpio-leds";
  19. rssi {
  20. label = "red:rssi";
  21. gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
  22. };
  23. led_system: system {
  24. label = "green:system";
  25. gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
  26. };
  27. air {
  28. label = "green:wifi";
  29. gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
  30. };
  31. };
  32. keys {
  33. compatible = "gpio-keys";
  34. wps {
  35. label = "wps";
  36. gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
  37. linux,code = <KEY_WPS_BUTTON>;
  38. };
  39. reset {
  40. label = "reset";
  41. gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
  42. linux,code = <KEY_RESTART>;
  43. };
  44. };
  45. };
  46. &spi0 {
  47. status = "okay";
  48. flash@0 {
  49. compatible = "jedec,spi-nor";
  50. reg = <0>;
  51. spi-max-frequency = <10000000>;
  52. partitions {
  53. compatible = "fixed-partitions";
  54. #address-cells = <1>;
  55. #size-cells = <1>;
  56. partition@0 {
  57. label = "u-boot";
  58. reg = <0x0 0x30000>;
  59. read-only;
  60. };
  61. partition@30000 {
  62. label = "u-boot-env";
  63. reg = <0x30000 0x10000>;
  64. read-only;
  65. };
  66. factory: partition@40000 {
  67. label = "factory";
  68. reg = <0x40000 0x10000>;
  69. read-only;
  70. };
  71. firmware: partition@50000 {
  72. compatible = "denx,uimage";
  73. label = "firmware";
  74. reg = <0x50000 0xfb0000>;
  75. };
  76. };
  77. };
  78. };
  79. &gpio0 {
  80. status = "okay";
  81. };
  82. &gpio1 {
  83. status = "okay";
  84. };
  85. &gpio3 {
  86. status = "okay";
  87. };
  88. &sdhci {
  89. status = "okay";
  90. };
  91. &ehci {
  92. status = "okay";
  93. };
  94. &ohci {
  95. status = "okay";
  96. };
  97. &ethernet {
  98. pinctrl-names = "default";
  99. pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
  100. mtd-mac-address = <&factory 0x4>;
  101. port@4 {
  102. status = "okay";
  103. phy-handle = <&phy4>;
  104. phy-mode = "rgmii";
  105. };
  106. port@5 {
  107. status = "okay";
  108. phy-handle = <&phy5>;
  109. phy-mode = "rgmii";
  110. };
  111. mdio-bus {
  112. status = "okay";
  113. phy4: ethernet-phy@4 {
  114. reg = <4>;
  115. phy-mode = "rgmii";
  116. };
  117. phy5: ethernet-phy@5 {
  118. reg = <5>;
  119. phy-mode = "rgmii";
  120. };
  121. };
  122. };
  123. &wmac {
  124. ralink,mtd-eeprom = <&factory 0x0>;
  125. };
  126. &state_default {
  127. default {
  128. groups = "i2c", "uartf", "pa", "spi refclk",
  129. "wled";
  130. function = "gpio";
  131. };
  132. };
  133. &pcie {
  134. status = "okay";
  135. };
  136. &pcie0 {
  137. wifi@0,0 {
  138. compatible = "mediatek,mt76";
  139. reg = <0x0000 0 0 0 0>;
  140. mediatek,mtd-eeprom = <&factory 0x8000>;
  141. ieee80211-freq-limit = <5000000 6000000>;
  142. };
  143. };
  144. &uart {
  145. status = "okay";
  146. };