mt7620a_lb-link_bl-w1200.dts 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. #include "mt7620a.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. / {
  6. compatible = "lb-link,bl-w1200", "ralink,mt7620a-soc";
  7. model = "LB-Link BL-W1200";
  8. aliases {
  9. led-boot = &led_wps;
  10. led-failsafe = &led_wps;
  11. led-upgrade = &led_wps;
  12. };
  13. keys {
  14. compatible = "gpio-keys";
  15. reset_wps {
  16. label = "reset_wps";
  17. gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
  18. linux,code = <KEY_RESTART>;
  19. };
  20. };
  21. leds {
  22. compatible = "gpio-leds";
  23. led_wps: wps {
  24. label = "green:wps";
  25. gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  26. };
  27. };
  28. };
  29. &gpio1 {
  30. status = "okay";
  31. };
  32. &spi0 {
  33. status = "okay";
  34. flash@0 {
  35. compatible = "jedec,spi-nor";
  36. reg = <0>;
  37. spi-max-frequency = <50000000>;
  38. partitions {
  39. compatible = "fixed-partitions";
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. partition@0 {
  43. label = "u-boot";
  44. reg = <0x0 0x30000>;
  45. read-only;
  46. };
  47. partition@30000 {
  48. label = "config";
  49. reg = <0x30000 0x10000>;
  50. read-only;
  51. };
  52. factory: partition@40000 {
  53. label = "factory";
  54. reg = <0x40000 0x10000>;
  55. read-only;
  56. };
  57. partition@50000 {
  58. compatible = "denx,uimage";
  59. label = "firmware";
  60. reg = <0x50000 0x7b0000>;
  61. };
  62. };
  63. };
  64. };
  65. &state_default {
  66. gpio {
  67. groups = "uartf", "spi refclk";
  68. function = "gpio";
  69. };
  70. };
  71. &ethernet {
  72. pinctrl-names = "default";
  73. pinctrl-0 = <&rgmii2_pins &mdio_pins>;
  74. mtd-mac-address = <&factory 0x28>;
  75. mediatek,portmap = "wllll";
  76. port@5 {
  77. status = "okay";
  78. mediatek,fixed-link = <1000 1 1 1>;
  79. phy-mode = "rgmii";
  80. };
  81. mdio-bus {
  82. status = "okay";
  83. ethernet-phy@0 {
  84. reg = <0>;
  85. phy-mode = "rgmii";
  86. };
  87. ethernet-phy@1 {
  88. reg = <1>;
  89. phy-mode = "rgmii";
  90. };
  91. ethernet-phy@2 {
  92. reg = <2>;
  93. phy-mode = "rgmii";
  94. };
  95. ethernet-phy@3 {
  96. reg = <3>;
  97. phy-mode = "rgmii";
  98. };
  99. ethernet-phy@4 {
  100. reg = <4>;
  101. phy-mode = "rgmii";
  102. };
  103. ethernet-phy@1f {
  104. reg = <0x1f>;
  105. phy-mode = "rgmii";
  106. };
  107. };
  108. };
  109. &wmac {
  110. ralink,mtd-eeprom = <&factory 0x0>;
  111. };
  112. &pcie {
  113. status = "okay";
  114. };
  115. &pcie0 {
  116. wifi@0,0 {
  117. compatible = "mediatek,mt76";
  118. reg = <0x0000 0 0 0 0>;
  119. ieee80211-freq-limit = <5000000 6000000>;
  120. mediatek,mtd-eeprom = <&factory 0x8000>;
  121. led {
  122. led-sources = <2>;
  123. led-active-low;
  124. };
  125. };
  126. };
  127. &ehci {
  128. status = "okay";
  129. };
  130. &ohci {
  131. status = "okay";
  132. };