mt7620a_planex_db-wrt01.dts 1.5 KB

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  1. #include "mt7620a.dtsi"
  2. #include <dt-bindings/gpio/gpio.h>
  3. #include <dt-bindings/input/input.h>
  4. / {
  5. compatible = "planex,db-wrt01", "ralink,mt7620a-soc";
  6. model = "Planex DB-WRT01";
  7. aliases {
  8. led-boot = &led_power;
  9. led-failsafe = &led_power;
  10. led-running = &led_power;
  11. led-upgrade = &led_power;
  12. };
  13. leds {
  14. compatible = "gpio-leds";
  15. led_power: power {
  16. label = "orange:power";
  17. gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
  18. };
  19. };
  20. keys {
  21. compatible = "gpio-keys";
  22. s1 {
  23. label = "wps";
  24. gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
  25. linux,code = <KEY_WPS_BUTTON>;
  26. };
  27. };
  28. };
  29. &gpio1 {
  30. status = "okay";
  31. };
  32. &spi0 {
  33. status = "okay";
  34. flash@0 {
  35. compatible = "jedec,spi-nor";
  36. reg = <0>;
  37. spi-max-frequency = <10000000>;
  38. partitions {
  39. compatible = "fixed-partitions";
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. partition@0 {
  43. label = "u-boot";
  44. reg = <0x0 0x30000>;
  45. read-only;
  46. };
  47. partition@30000 {
  48. label = "u-boot-env";
  49. reg = <0x30000 0x10000>;
  50. read-only;
  51. };
  52. factory: partition@40000 {
  53. label = "factory";
  54. reg = <0x40000 0x10000>;
  55. read-only;
  56. };
  57. partition@50000 {
  58. compatible = "denx,uimage";
  59. label = "firmware";
  60. reg = <0x50000 0x7b0000>;
  61. };
  62. };
  63. };
  64. };
  65. &state_default {
  66. gpio {
  67. groups = "i2c", "spi refclk", "rgmii1";
  68. function = "gpio";
  69. };
  70. };
  71. &ethernet {
  72. pinctrl-names = "default";
  73. pinctrl-0 = <&ephy_pins>;
  74. mtd-mac-address = <&factory 0x4>;
  75. mediatek,portmap = "llllw";
  76. };
  77. &gsw {
  78. mediatek,port4 = "ephy";
  79. };
  80. &wmac {
  81. ralink,mtd-eeprom = <&factory 0x0>;
  82. };