mt7620a_planex_mzk-750dhp.dts 2.0 KB

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  1. #include "mt7620a.dtsi"
  2. #include <dt-bindings/gpio/gpio.h>
  3. #include <dt-bindings/input/input.h>
  4. / {
  5. compatible = "planex,mzk-750dhp", "ralink,mt7620a-soc";
  6. model = "Planex MZK-750DHP";
  7. aliases {
  8. led-boot = &led_power;
  9. led-failsafe = &led_power;
  10. led-running = &led_power;
  11. led-upgrade = &led_power;
  12. };
  13. leds {
  14. compatible = "gpio-leds";
  15. wps {
  16. label = "green:wps";
  17. gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
  18. };
  19. led_power: power {
  20. label = "green:power";
  21. gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  22. };
  23. wlan5g {
  24. label = "green:wlan5g";
  25. gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
  26. };
  27. };
  28. keys {
  29. compatible = "gpio-keys";
  30. s1 {
  31. label = "reset";
  32. gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
  33. linux,code = <KEY_RESTART>;
  34. };
  35. s2 {
  36. label = "wps";
  37. gpios = <&gpio2 19 GPIO_ACTIVE_LOW>;
  38. linux,code = <KEY_WPS_BUTTON>;
  39. };
  40. };
  41. };
  42. &gpio1 {
  43. status = "okay";
  44. };
  45. &gpio2 {
  46. status = "okay";
  47. };
  48. &spi0 {
  49. status = "okay";
  50. flash@0 {
  51. compatible = "jedec,spi-nor";
  52. reg = <0>;
  53. spi-max-frequency = <10000000>;
  54. partitions {
  55. compatible = "fixed-partitions";
  56. #address-cells = <1>;
  57. #size-cells = <1>;
  58. partition@0 {
  59. label = "u-boot";
  60. reg = <0x0 0x30000>;
  61. read-only;
  62. };
  63. partition@30000 {
  64. label = "u-boot-env";
  65. reg = <0x30000 0x10000>;
  66. read-only;
  67. };
  68. factory: partition@40000 {
  69. label = "factory";
  70. reg = <0x40000 0x10000>;
  71. read-only;
  72. };
  73. partition@50000 {
  74. compatible = "denx,uimage";
  75. label = "firmware";
  76. reg = <0x50000 0x7b0000>;
  77. };
  78. };
  79. };
  80. };
  81. &state_default {
  82. gpio {
  83. groups = "i2c", "spi refclk", "rgmii1", "nd_sd";
  84. function = "gpio";
  85. };
  86. };
  87. &ethernet {
  88. pinctrl-names = "default";
  89. pinctrl-0 = <&ephy_pins>;
  90. mtd-mac-address = <&factory 0x4>;
  91. mediatek,portmap = "llllw";
  92. };
  93. &gsw {
  94. mediatek,port4 = "ephy";
  95. };
  96. &wmac {
  97. ralink,mtd-eeprom = <&factory 0x0>;
  98. };
  99. &pcie {
  100. status = "okay";
  101. };
  102. &pcie0 {
  103. mt76@0,0 {
  104. reg = <0x0000 0 0 0 0>;
  105. mediatek,mtd-eeprom = <&factory 0x8000>;
  106. };
  107. };