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- From 908a87b47af8303c9aa8fb6aa183ca9f8b544d78 Mon Sep 17 00:00:00 2001
- From: YH Huang <[email protected]>
- Date: Mon, 11 May 2015 17:26:21 +0800
- Subject: [PATCH 27/76] dt-bindings: pwm: add Mediatek display PWM bindings
- Document the device-tree binding of Mediatek display PWM.
- Signed-off-by: YH Huang <[email protected]>
- ---
- .../devicetree/bindings/pwm/pwm-disp-mediatek.txt | 25 ++++++++++++++++++++
- 1 file changed, 25 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pwm/pwm-disp-mediatek.txt
- --- /dev/null
- +++ b/Documentation/devicetree/bindings/pwm/pwm-disp-mediatek.txt
- @@ -0,0 +1,25 @@
- +Mediatek display PWM controller
- +
- +Required properties:
- + - compatible: should be "mediatek,<name>-disp-pwm"
- + - "mediatek,mt8173-disp-pwm": found on mt8173 SoC
- + - "mediatek,mt6595-disp-pwm": found on mt6595 SoC
- + - reg: physical base address and length of the controller's registers
- + - #pwm-cells: must be 2. See pwm.txt in this directory
- + for a description of the cell format
- + - clocks: phandle and clock specifier of the PWM reference clock
- + - clock-names: must contain the following
- + - "main": clock used to generate PWM signals
- + - "mm": sync signals from the modules of mmsys
- +
- +Example:
- + pwm0: pwm@1401e000 {
- + compatible = "mediatek,mt8173-disp-pwm",
- + "mediatek,mt6595-disp-pwm";
- + reg = <0 0x1401e000 0 0x1000>;
- + #pwm-cells = <2>;
- + clocks = <&mmsys MM_DISP_PWM026M>,
- + <&mmsys MM_DISP_PWM0MM>;
- + clock-names = "main",
- + "mm";
- + };
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