781-net-ethernet-mtk_eth_soc-move-gdma_to_ppe-and-ppe_ba.patch 4.2 KB

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  1. From patchwork Thu Sep 8 19:33:38 2022
  2. Content-Type: text/plain; charset="utf-8"
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  5. X-Patchwork-Submitter: Lorenzo Bianconi <[email protected]>
  6. X-Patchwork-Id: 12970556
  7. X-Patchwork-Delegate: [email protected]
  8. From: Lorenzo Bianconi <[email protected]>
  9. To: [email protected]
  10. Cc: [email protected], [email protected], [email protected],
  11. [email protected], [email protected], [email protected],
  12. [email protected], [email protected], [email protected],
  13. [email protected], [email protected],
  14. [email protected], [email protected],
  15. [email protected], [email protected],
  16. [email protected], [email protected]
  17. Subject: [PATCH net-next 03/12] net: ethernet: mtk_eth_soc: move gdma_to_ppe
  18. and ppe_base definitions in mtk register map
  19. Date: Thu, 8 Sep 2022 21:33:37 +0200
  20. Message-Id:
  21. <95938fc9cbe0223714be2658a49ca58e9baace00.1662661555.git.lorenzo@kernel.org>
  22. X-Mailer: git-send-email 2.37.3
  23. In-Reply-To: <[email protected]>
  24. References: <[email protected]>
  25. MIME-Version: 1.0
  26. Precedence: bulk
  27. List-ID: <netdev.vger.kernel.org>
  28. X-Mailing-List: [email protected]
  29. X-Patchwork-Delegate: [email protected]
  30. This is a preliminary patch to introduce mt7986 hw packet engine.
  31. Signed-off-by: Lorenzo Bianconi <[email protected]>
  32. ---
  33. drivers/net/ethernet/mediatek/mtk_eth_soc.c | 15 +++++++++++----
  34. drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 ++-
  35. drivers/net/ethernet/mediatek/mtk_ppe.h | 2 --
  36. 3 files changed, 13 insertions(+), 7 deletions(-)
  37. --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  38. +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  39. @@ -73,6 +73,8 @@ static const struct mtk_reg_map mtk_reg_
  40. .fq_blen = 0x1b2c,
  41. },
  42. .gdm1_cnt = 0x2400,
  43. + .gdma_to_ppe0 = 0x4444,
  44. + .ppe_base = 0x0c00,
  45. };
  46. static const struct mtk_reg_map mt7628_reg_map = {
  47. @@ -126,6 +128,8 @@ static const struct mtk_reg_map mt7986_r
  48. .fq_blen = 0x472c,
  49. },
  50. .gdm1_cnt = 0x1c00,
  51. + .gdma_to_ppe0 = 0x3333,
  52. + .ppe_base = 0x2000,
  53. };
  54. /* strings used by ethtool */
  55. @@ -2924,6 +2928,7 @@ static int mtk_open(struct net_device *d
  56. /* we run 2 netdevs on the same dma ring so we only bring it up once */
  57. if (!refcount_read(&eth->dma_refcnt)) {
  58. + const struct mtk_soc_data *soc = eth->soc;
  59. u32 gdm_config = MTK_GDMA_TO_PDMA;
  60. int err;
  61. @@ -2931,15 +2936,15 @@ static int mtk_open(struct net_device *d
  62. if (err)
  63. return err;
  64. - if (eth->soc->offload_version && mtk_ppe_start(eth->ppe) == 0)
  65. - gdm_config = MTK_GDMA_TO_PPE;
  66. + if (soc->offload_version && mtk_ppe_start(eth->ppe) == 0)
  67. + gdm_config = soc->reg_map->gdma_to_ppe0;
  68. mtk_gdm_config(eth, gdm_config);
  69. napi_enable(&eth->tx_napi);
  70. napi_enable(&eth->rx_napi);
  71. mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
  72. - mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
  73. + mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask);
  74. refcount_set(&eth->dma_refcnt, 1);
  75. }
  76. else
  77. @@ -4045,7 +4050,9 @@ static int mtk_probe(struct platform_dev
  78. }
  79. if (eth->soc->offload_version) {
  80. - eth->ppe = mtk_ppe_init(eth, eth->base + MTK_ETH_PPE_BASE, 2);
  81. + u32 ppe_addr = eth->soc->reg_map->ppe_base;
  82. +
  83. + eth->ppe = mtk_ppe_init(eth, eth->base + ppe_addr, 2);
  84. if (!eth->ppe) {
  85. err = -ENOMEM;
  86. goto err_free_dev;
  87. --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  88. +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  89. @@ -105,7 +105,6 @@
  90. #define MTK_GDMA_TCS_EN BIT(21)
  91. #define MTK_GDMA_UCS_EN BIT(20)
  92. #define MTK_GDMA_TO_PDMA 0x0
  93. -#define MTK_GDMA_TO_PPE 0x4444
  94. #define MTK_GDMA_DROP_ALL 0x7777
  95. /* Unicast Filter MAC Address Register - Low */
  96. @@ -952,6 +951,8 @@ struct mtk_reg_map {
  97. u32 fq_blen; /* fq free page buffer length */
  98. } qdma;
  99. u32 gdm1_cnt;
  100. + u32 gdma_to_ppe0;
  101. + u32 ppe_base;
  102. };
  103. /* struct mtk_eth_data - This is the structure holding all differences
  104. --- a/drivers/net/ethernet/mediatek/mtk_ppe.h
  105. +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
  106. @@ -8,8 +8,6 @@
  107. #include <linux/bitfield.h>
  108. #include <linux/rhashtable.h>
  109. -#define MTK_ETH_PPE_BASE 0xc00
  110. -
  111. #define MTK_PPE_ENTRIES_SHIFT 3
  112. #define MTK_PPE_ENTRIES (1024 << MTK_PPE_ENTRIES_SHIFT)
  113. #define MTK_PPE_HASH_MASK (MTK_PPE_ENTRIES - 1)