ipq8072-haze.dts 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /dts-v1/;
  3. #include "ipq8074.dtsi"
  4. #include "ipq8074-hk-cpu.dtsi"
  5. #include "ipq8074-ess.dtsi"
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/input/input.h>
  8. #include <dt-bindings/leds/common.h>
  9. / {
  10. model = "prpl Foundation Haze";
  11. compatible = "prpl,haze", "qcom,ipq8074";
  12. aliases {
  13. serial0 = &blsp1_uart5;
  14. /* Aliases are required by U-Boot to patch MAC addresses */
  15. ethernet0 = &dp6_syn;
  16. ethernet1 = &dp4;
  17. ethernet2 = &dp3;
  18. ethernet3 = &dp2;
  19. label-mac-device = &dp6_syn;
  20. };
  21. chosen {
  22. stdout-path = "serial0:115200n8";
  23. };
  24. keys {
  25. compatible = "gpio-keys";
  26. pinctrl-0 = <&button_pins>;
  27. pinctrl-names = "default";
  28. wps-button {
  29. label = "wps";
  30. gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
  31. linux,code = <KEY_WPS_BUTTON>;
  32. };
  33. reset-button {
  34. label = "reset";
  35. gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
  36. linux,code = <KEY_RESTART>;
  37. };
  38. };
  39. };
  40. &tlmm {
  41. mdio_pins: mdio-state {
  42. mdc-pins {
  43. pins = "gpio68";
  44. function = "mdc";
  45. drive-strength = <8>;
  46. bias-pull-up;
  47. };
  48. mdio-pins {
  49. pins = "gpio69";
  50. function = "mdio";
  51. drive-strength = <8>;
  52. bias-pull-up;
  53. };
  54. };
  55. button_pins: button-state {
  56. wps-pins {
  57. pins = "gpio42";
  58. function = "gpio";
  59. drive-strength = <8>;
  60. bias-pull-up;
  61. };
  62. rst-pins {
  63. pins = "gpio44";
  64. function = "gpio";
  65. drive-strength = <8>;
  66. bias-pull-up;
  67. };
  68. };
  69. };
  70. &blsp1_uart5 {
  71. status = "okay";
  72. };
  73. &prng {
  74. status = "okay";
  75. };
  76. &ssphy_0 {
  77. status = "okay";
  78. };
  79. &qusb_phy_0 {
  80. status = "okay";
  81. };
  82. &ssphy_1 {
  83. status = "okay";
  84. };
  85. &qusb_phy_1 {
  86. status = "okay";
  87. };
  88. &usb_0 {
  89. status = "okay";
  90. };
  91. &usb_1 {
  92. status = "okay";
  93. };
  94. &cryptobam {
  95. status = "okay";
  96. };
  97. &crypto {
  98. status = "okay";
  99. };
  100. &qpic_bam {
  101. status = "okay";
  102. };
  103. &blsp1_spi1 { /* BLSP1 QUP1 */
  104. pinctrl-0 = <&spi_0_pins>;
  105. pinctrl-names = "default";
  106. cs-gpios = <0>;
  107. status = "okay";
  108. flash@0 {
  109. #address-cells = <1>;
  110. #size-cells = <1>;
  111. reg = <0>;
  112. compatible = "jedec,spi-nor";
  113. spi-max-frequency = <50000000>;
  114. partitions {
  115. compatible = "qcom,smem-part";
  116. };
  117. };
  118. };
  119. &mdio {
  120. status = "okay";
  121. pinctrl-0 = <&mdio_pins>;
  122. pinctrl-names = "default";
  123. reset-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
  124. qca8075_1: ethernet-phy@0 {
  125. compatible = "ethernet-phy-ieee802.3-c22";
  126. reg = <0>;
  127. };
  128. qca8075_2: ethernet-phy@1 {
  129. compatible = "ethernet-phy-ieee802.3-c22";
  130. reg = <1>;
  131. };
  132. qca8075_3: ethernet-phy@2 {
  133. compatible = "ethernet-phy-ieee802.3-c22";
  134. reg = <2>;
  135. };
  136. qca8075_4: ethernet-phy@3 {
  137. compatible = "ethernet-phy-ieee802.3-c22";
  138. reg = <3>;
  139. };
  140. aqr113c: ethernet-phy@5 {
  141. compatible ="ethernet-phy-ieee802.3-c45";
  142. reg = <8>;
  143. reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
  144. };
  145. };
  146. &sdhc_1 {
  147. status = "okay";
  148. vqmmc-supply = <&l11>;
  149. };
  150. &switch {
  151. status = "okay";
  152. switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
  153. switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
  154. switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
  155. switch_mac_mode1 = <MAC_MODE_10GBASE_R>; /* mac mode for uniphy instance1*/
  156. switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/
  157. bm_tick_mode = <0>; /* bm tick mode */
  158. tm_tick_mode = <0>; /* tm tick mode */
  159. qcom,port_phyinfo {
  160. port@0 {
  161. port_id = <1>;
  162. phy_address = <0>;
  163. };
  164. port@1 {
  165. port_id = <2>;
  166. phy_address = <1>;
  167. };
  168. port@2 {
  169. port_id = <3>;
  170. phy_address = <2>;
  171. };
  172. port@3 {
  173. port_id = <4>;
  174. phy_address = <3>;
  175. };
  176. port@4 {
  177. port_id = <6>;
  178. phy_address = <8>;
  179. compatible = "ethernet-phy-ieee802.3-c45";
  180. ethernet-phy-ieee802.3-c45;
  181. };
  182. };
  183. };
  184. &edma {
  185. status = "okay";
  186. };
  187. /* Dummy LAN port */
  188. &dp1 {
  189. status = "disabled";
  190. phy-handle = <&qca8075_1>;
  191. label = "lan4";
  192. };
  193. &dp2 {
  194. status = "okay";
  195. phy-handle = <&qca8075_2>;
  196. label = "lan3";
  197. };
  198. &dp3 {
  199. status = "okay";
  200. phy-handle = <&qca8075_3>;
  201. label = "lan2";
  202. };
  203. &dp4 {
  204. status = "okay";
  205. phy-handle = <&qca8075_4>;
  206. label = "lan1";
  207. };
  208. &dp6_syn {
  209. status = "okay";
  210. qcom,mactype = <1>;
  211. phy-handle = <&aqr113c>;
  212. label = "wan";
  213. };
  214. &pcie_qmp0 {
  215. status = "okay";
  216. };
  217. &pcie0 {
  218. status = "okay";
  219. perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
  220. bridge@0,0 {
  221. reg = <0x00020000 0 0 0 0>;
  222. #address-cells = <3>;
  223. #size-cells = <2>;
  224. ranges;
  225. };
  226. };
  227. &pcie_qmp1 {
  228. status = "okay";
  229. };
  230. &pcie1 {
  231. status = "okay";
  232. perst-gpio = <&tlmm 61 GPIO_ACTIVE_LOW>;
  233. bridge@1,0 {
  234. reg = <0x00010000 0 0 0 0>;
  235. #address-cells = <3>;
  236. #size-cells = <2>;
  237. ranges;
  238. wifi@1,0 {
  239. status = "okay";
  240. /* ath11k has no DT compatible for PCI cards */
  241. compatible = "pci17cb,1104";
  242. reg = <0x00010000 0 0 0 0>;
  243. qcom,ath11k-calibration-variant = "prpl-Haze";
  244. };
  245. };
  246. };
  247. &wifi {
  248. status = "okay";
  249. qcom,ath11k-calibration-variant = "prpl-Haze";
  250. };