0010-arch-mips-ralink-add-spi1-clocks.patch 1.7 KB

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  1. From 39ce22c870f4503bed5e451acfcab21eba3b6239 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <[email protected]>
  3. Date: Sun, 27 Jul 2014 09:49:07 +0100
  4. Subject: [PATCH 10/53] arch: mips: ralink: add spi1 clocks
  5. based on f3bc64d6d1f21c1b92d75f233a37b75d77af6963
  6. Signed-off-by: John Crispin <[email protected]>
  7. ---
  8. arch/mips/ralink/mt7620.c | 1 +
  9. arch/mips/ralink/rt305x.c | 1 +
  10. arch/mips/ralink/rt3883.c | 1 +
  11. 3 files changed, 3 insertions(+)
  12. --- a/arch/mips/ralink/mt7620.c
  13. +++ b/arch/mips/ralink/mt7620.c
  14. @@ -436,6 +436,7 @@ void __init ralink_clk_init(void)
  15. ralink_clk_add("10000100.timer", periph_rate);
  16. ralink_clk_add("10000120.watchdog", periph_rate);
  17. ralink_clk_add("10000b00.spi", sys_rate);
  18. + ralink_clk_add("10000b40.spi", sys_rate);
  19. ralink_clk_add("10000c00.uartlite", periph_rate);
  20. ralink_clk_add("10180000.wmac", xtal_rate);
  21. --- a/arch/mips/ralink/rt305x.c
  22. +++ b/arch/mips/ralink/rt305x.c
  23. @@ -201,6 +201,7 @@ void __init ralink_clk_init(void)
  24. ralink_clk_add("cpu", cpu_rate);
  25. ralink_clk_add("sys", sys_rate);
  26. ralink_clk_add("10000b00.spi", sys_rate);
  27. + ralink_clk_add("10000b40.spi", sys_rate);
  28. ralink_clk_add("10000100.timer", wdt_rate);
  29. ralink_clk_add("10000120.watchdog", wdt_rate);
  30. ralink_clk_add("10000500.uart", uart_rate);
  31. --- a/arch/mips/ralink/rt3883.c
  32. +++ b/arch/mips/ralink/rt3883.c
  33. @@ -109,6 +109,7 @@ void __init ralink_clk_init(void)
  34. ralink_clk_add("10000120.watchdog", sys_rate);
  35. ralink_clk_add("10000500.uart", 40000000);
  36. ralink_clk_add("10000b00.spi", sys_rate);
  37. + ralink_clk_add("10000b40.spi", sys_rate);
  38. ralink_clk_add("10000c00.uartlite", 40000000);
  39. ralink_clk_add("10100000.ethernet", sys_rate);
  40. ralink_clk_add("10180000.wmac", 40000000);