0048-asoc-add-mt7620-support.patch 20 KB

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  1. From 7f29222b1731e8182ba94a331531dec18865a1e4 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <[email protected]>
  3. Date: Sun, 27 Jul 2014 09:31:47 +0100
  4. Subject: [PATCH 48/53] asoc: add mt7620 support
  5. Signed-off-by: John Crispin <[email protected]>
  6. ---
  7. arch/mips/ralink/of.c | 2 +
  8. sound/soc/Kconfig | 1 +
  9. sound/soc/Makefile | 1 +
  10. sound/soc/ralink/Kconfig | 15 ++
  11. sound/soc/ralink/Makefile | 11 +
  12. sound/soc/ralink/mt7620-i2s.c | 436 ++++++++++++++++++++++++++++++++++++++
  13. sound/soc/ralink/mt7620-wm8960.c | 233 ++++++++++++++++++++
  14. 7 files changed, 699 insertions(+)
  15. create mode 100644 sound/soc/ralink/Kconfig
  16. create mode 100644 sound/soc/ralink/Makefile
  17. create mode 100644 sound/soc/ralink/mt7620-i2s.c
  18. create mode 100644 sound/soc/ralink/mt7620-wm8960.c
  19. --- a/arch/mips/ralink/of.c
  20. +++ b/arch/mips/ralink/of.c
  21. @@ -15,6 +15,7 @@
  22. #include <linux/of_fdt.h>
  23. #include <linux/kernel.h>
  24. #include <linux/bootmem.h>
  25. +#include <linux/module.h>
  26. #include <linux/of_platform.h>
  27. #include <linux/of_address.h>
  28. @@ -26,6 +27,7 @@
  29. #include "common.h"
  30. __iomem void *rt_sysc_membase;
  31. +EXPORT_SYMBOL(rt_sysc_membase);
  32. __iomem void *rt_memc_membase;
  33. __iomem void *plat_of_remap_node(const char *node)
  34. --- a/sound/soc/Kconfig
  35. +++ b/sound/soc/Kconfig
  36. @@ -56,6 +56,7 @@ source "sound/soc/mxs/Kconfig"
  37. source "sound/soc/pxa/Kconfig"
  38. source "sound/soc/qcom/Kconfig"
  39. source "sound/soc/rockchip/Kconfig"
  40. +source "sound/soc/ralink/Kconfig"
  41. source "sound/soc/samsung/Kconfig"
  42. source "sound/soc/sh/Kconfig"
  43. source "sound/soc/sirf/Kconfig"
  44. --- a/sound/soc/Makefile
  45. +++ b/sound/soc/Makefile
  46. @@ -36,6 +36,7 @@ obj-$(CONFIG_SND_SOC) += kirkwood/
  47. obj-$(CONFIG_SND_SOC) += pxa/
  48. obj-$(CONFIG_SND_SOC) += qcom/
  49. obj-$(CONFIG_SND_SOC) += rockchip/
  50. +obj-$(CONFIG_SND_SOC) += ralink/
  51. obj-$(CONFIG_SND_SOC) += samsung/
  52. obj-$(CONFIG_SND_SOC) += sh/
  53. obj-$(CONFIG_SND_SOC) += sirf/
  54. --- /dev/null
  55. +++ b/sound/soc/ralink/Kconfig
  56. @@ -0,0 +1,15 @@
  57. +config SND_MT7620_SOC_I2S
  58. + depends on SOC_MT7620 && SND_SOC
  59. + select SND_SOC_GENERIC_DMAENGINE_PCM
  60. + tristate "SoC Audio (I2S protocol) for Ralink MT7620 SoC"
  61. + help
  62. + Say Y if you want to use I2S protocol and I2S codec on Ingenic MT7620
  63. + based boards.
  64. +
  65. +config SND_MT7620_SOC_WM8960
  66. + tristate "SoC Audio support for Ralink WM8960"
  67. + select SND_MT7620_SOC_I2S
  68. + select SND_SOC_WM8960
  69. + help
  70. + Say Y if you want to add support for ASoC audio on the Qi LB60 board
  71. + a.k.a Qi Ben NanoNote.
  72. --- /dev/null
  73. +++ b/sound/soc/ralink/Makefile
  74. @@ -0,0 +1,11 @@
  75. +#
  76. +# Jz4740 Platform Support
  77. +#
  78. +snd-soc-mt7620-i2s-objs := mt7620-i2s.o
  79. +
  80. +obj-$(CONFIG_SND_MT7620_SOC_I2S) += snd-soc-mt7620-i2s.o
  81. +
  82. +# Jz4740 Machine Support
  83. +snd-soc-mt7620-wm8960-objs := mt7620-wm8960.o
  84. +
  85. +obj-$(CONFIG_SND_MT7620_SOC_WM8960) += snd-soc-mt7620-wm8960.o
  86. --- /dev/null
  87. +++ b/sound/soc/ralink/mt7620-i2s.c
  88. @@ -0,0 +1,436 @@
  89. +/*
  90. + * Copyright (C) 2010, Lars-Peter Clausen <[email protected]>
  91. + *
  92. + * This program is free software; you can redistribute it and/or modify it
  93. + * under the terms of the GNU General Public License as published by the
  94. + * Free Software Foundation; either version 2 of the License, or (at your
  95. + * option) any later version.
  96. + *
  97. + * You should have received a copy of the GNU General Public License along
  98. + * with this program; if not, write to the Free Software Foundation, Inc.,
  99. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  100. + *
  101. + */
  102. +
  103. +#include <linux/init.h>
  104. +#include <linux/io.h>
  105. +#include <linux/kernel.h>
  106. +#include <linux/module.h>
  107. +#include <linux/platform_device.h>
  108. +#include <linux/slab.h>
  109. +
  110. +#include <linux/delay.h>
  111. +
  112. +#include <linux/dma-mapping.h>
  113. +
  114. +#include <sound/core.h>
  115. +#include <sound/pcm.h>
  116. +#include <sound/pcm_params.h>
  117. +#include <sound/soc.h>
  118. +#include <sound/initval.h>
  119. +#include <sound/dmaengine_pcm.h>
  120. +
  121. +#include <ralink_regs.h>
  122. +
  123. +#define I2S_REG_CFG0 0x00
  124. +#define I2S_REG_CFG0_EN BIT(31)
  125. +#define I2S_REG_CFG0_DMA_EN BIT(30)
  126. +#define I2S_REG_CFG0_BYTE_SWAP BIT(28)
  127. +#define I2S_REG_CFG0_TX_EN BIT(24)
  128. +#define I2S_REG_CFG0_RX_EN BIT(20)
  129. +#define I2S_REG_CFG0_SLAVE BIT(16)
  130. +#define I2S_REG_CFG0_RX_THRES 12
  131. +#define I2S_REG_CFG0_TX_THRES 4
  132. +#define I2S_REG_CFG0_DFT_THRES (4 << I2S_REG_CFG0_RX_THRES) | \
  133. + (4 << I2S_REG_CFG0_TX_THRES)
  134. +
  135. +#define I2S_REG_INT_STATUS 0x04
  136. +#define I2S_REG_INT_EN 0x08
  137. +#define I2S_REG_FF_STATUS 0x0c
  138. +#define I2S_REG_WREG 0x10
  139. +#define I2S_REG_RREG 0x14
  140. +#define I2S_REG_CFG1 0x18
  141. +
  142. +#define I2S_REG_DIVCMP 0x20
  143. +#define I2S_REG_DIVINT 0x24
  144. +#define I2S_REG_CLK_EN BIT(31)
  145. +
  146. +struct mt7620_i2s {
  147. + struct resource *mem;
  148. + void __iomem *base;
  149. + dma_addr_t phys_base;
  150. +
  151. + struct snd_dmaengine_dai_dma_data playback_dma_data;
  152. + struct snd_dmaengine_dai_dma_data capture_dma_data;
  153. +};
  154. +
  155. +static inline uint32_t mt7620_i2s_read(const struct mt7620_i2s *i2s,
  156. + unsigned int reg)
  157. +{
  158. + return readl(i2s->base + reg);
  159. +}
  160. +
  161. +static inline void mt7620_i2s_write(const struct mt7620_i2s *i2s,
  162. + unsigned int reg, uint32_t value)
  163. +{
  164. + //printk("i2s --> %p = 0x%08X\n", i2s->base + reg, value);
  165. + writel(value, i2s->base + reg);
  166. +}
  167. +
  168. +static int mt7620_i2s_startup(struct snd_pcm_substream *substream,
  169. + struct snd_soc_dai *dai)
  170. +{
  171. + struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  172. + uint32_t cfg;
  173. +
  174. + if (dai->active)
  175. + return 0;
  176. +
  177. + cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
  178. + cfg |= I2S_REG_CFG0_EN;
  179. + mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
  180. +
  181. + return 0;
  182. +}
  183. +
  184. +static void mt7620_i2s_shutdown(struct snd_pcm_substream *substream,
  185. + struct snd_soc_dai *dai)
  186. +{
  187. + struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  188. + uint32_t cfg;
  189. +
  190. + if (dai->active)
  191. + return;
  192. +
  193. + cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
  194. + cfg &= ~I2S_REG_CFG0_EN;
  195. + mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
  196. +}
  197. +
  198. +static int mt7620_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
  199. + struct snd_soc_dai *dai)
  200. +{
  201. + struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  202. +
  203. + uint32_t cfg;
  204. + uint32_t mask;
  205. +
  206. + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  207. + mask = I2S_REG_CFG0_TX_EN;
  208. + else
  209. + mask = I2S_REG_CFG0_RX_EN;
  210. +
  211. + cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
  212. +
  213. + switch (cmd) {
  214. + case SNDRV_PCM_TRIGGER_START:
  215. + case SNDRV_PCM_TRIGGER_RESUME:
  216. + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  217. + cfg |= mask;
  218. + break;
  219. + case SNDRV_PCM_TRIGGER_STOP:
  220. + case SNDRV_PCM_TRIGGER_SUSPEND:
  221. + case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  222. + cfg &= ~mask;
  223. + break;
  224. + default:
  225. + return -EINVAL;
  226. + }
  227. +
  228. + if (cfg & (I2S_REG_CFG0_TX_EN | I2S_REG_CFG0_RX_EN))
  229. + cfg |= I2S_REG_CFG0_DMA_EN;
  230. + else
  231. + cfg &= ~I2S_REG_CFG0_DMA_EN;
  232. +
  233. + mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
  234. +
  235. + return 0;
  236. +}
  237. +
  238. +static int mt7620_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  239. +{
  240. + struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  241. + uint32_t cfg;
  242. +
  243. + cfg = mt7620_i2s_read(i2s, I2S_REG_CFG0);
  244. +
  245. + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  246. + case SND_SOC_DAIFMT_CBS_CFS:
  247. + cfg |= I2S_REG_CFG0_SLAVE;
  248. + break;
  249. + case SND_SOC_DAIFMT_CBM_CFM:
  250. + cfg &= ~I2S_REG_CFG0_SLAVE;
  251. + break;
  252. + case SND_SOC_DAIFMT_CBM_CFS:
  253. + default:
  254. + return -EINVAL;
  255. + }
  256. +
  257. + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  258. + case SND_SOC_DAIFMT_I2S:
  259. + case SND_SOC_DAIFMT_MSB:
  260. + cfg &= ~I2S_REG_CFG0_BYTE_SWAP;
  261. + break;
  262. + case SND_SOC_DAIFMT_LSB:
  263. + cfg |= I2S_REG_CFG0_BYTE_SWAP;
  264. + break;
  265. + default:
  266. + return -EINVAL;
  267. + }
  268. +
  269. + switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  270. + case SND_SOC_DAIFMT_NB_NF:
  271. + break;
  272. + default:
  273. + return -EINVAL;
  274. + }
  275. +
  276. + mt7620_i2s_write(i2s, I2S_REG_CFG0, cfg);
  277. +
  278. + return 0;
  279. +}
  280. +
  281. +static int mt7620_i2s_hw_params(struct snd_pcm_substream *substream,
  282. + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  283. +{
  284. +
  285. + return 0;
  286. +}
  287. +
  288. +unsigned long i2sMaster_inclk_int[11] = {
  289. + 78, 56, 52, 39, 28, 26, 19, 14, 13, 9, 6};
  290. +unsigned long i2sMaster_inclk_comp[11] = {
  291. + 64, 352, 42, 32, 176, 21, 272, 88, 10, 455, 261};
  292. +
  293. +
  294. +static int mt7620_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  295. + unsigned int freq, int dir)
  296. +{
  297. + struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  298. +
  299. + printk("Internal REFCLK with fractional division\n");
  300. +
  301. + mt7620_i2s_write(i2s, I2S_REG_DIVINT, i2sMaster_inclk_int[7]);
  302. + mt7620_i2s_write(i2s, I2S_REG_DIVCMP,
  303. + i2sMaster_inclk_comp[7] | I2S_REG_CLK_EN);
  304. +
  305. +/* struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  306. + struct clk *parent;
  307. + int ret = 0;
  308. +
  309. + switch (clk_id) {
  310. + case JZ4740_I2S_CLKSRC_EXT:
  311. + parent = clk_get(NULL, "ext");
  312. + clk_set_parent(i2s->clk_i2s, parent);
  313. + break;
  314. + case JZ4740_I2S_CLKSRC_PLL:
  315. + parent = clk_get(NULL, "pll half");
  316. + clk_set_parent(i2s->clk_i2s, parent);
  317. + ret = clk_set_rate(i2s->clk_i2s, freq);
  318. + break;
  319. + default:
  320. + return -EINVAL;
  321. + }
  322. + clk_put(parent);
  323. +
  324. + return ret;*/
  325. + return 0;
  326. +}
  327. +
  328. +static void mt7620_i2c_init_pcm_config(struct mt7620_i2s *i2s)
  329. +{
  330. + struct snd_dmaengine_dai_dma_data *dma_data;
  331. +
  332. + /* Playback */
  333. + dma_data = &i2s->playback_dma_data;
  334. + dma_data->maxburst = 16;
  335. + dma_data->slave_id = 2; //JZ4740_DMA_TYPE_AIC_TRANSMIT;
  336. + dma_data->addr = i2s->phys_base + I2S_REG_WREG;
  337. +
  338. + /* Capture */
  339. + dma_data = &i2s->capture_dma_data;
  340. + dma_data->maxburst = 16;
  341. + dma_data->slave_id = 3; //JZ4740_DMA_TYPE_AIC_RECEIVE;
  342. + dma_data->addr = i2s->phys_base + I2S_REG_RREG;
  343. +}
  344. +
  345. +static int mt7620_i2s_dai_probe(struct snd_soc_dai *dai)
  346. +{
  347. + struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  348. + uint32_t data;
  349. +
  350. + mt7620_i2c_init_pcm_config(i2s);
  351. + dai->playback_dma_data = &i2s->playback_dma_data;
  352. + dai->capture_dma_data = &i2s->capture_dma_data;
  353. +
  354. + /* set share pins to i2s/gpio mode and i2c mode */
  355. + data = rt_sysc_r32(0x60);
  356. + data &= 0xFFFFFFE2;
  357. + data |= 0x00000018;
  358. + rt_sysc_w32(data, 0x60);
  359. +
  360. + printk("Internal REFCLK with fractional division\n");
  361. +
  362. + mt7620_i2s_write(i2s, I2S_REG_CFG0, I2S_REG_CFG0_DFT_THRES);
  363. + mt7620_i2s_write(i2s, I2S_REG_CFG1, 0);
  364. + mt7620_i2s_write(i2s, I2S_REG_INT_EN, 0);
  365. +
  366. + mt7620_i2s_write(i2s, I2S_REG_DIVINT, i2sMaster_inclk_int[7]);
  367. + mt7620_i2s_write(i2s, I2S_REG_DIVCMP,
  368. + i2sMaster_inclk_comp[7] | I2S_REG_CLK_EN);
  369. +
  370. + return 0;
  371. +}
  372. +
  373. +static int mt7620_i2s_dai_remove(struct snd_soc_dai *dai)
  374. +{
  375. + return 0;
  376. +}
  377. +
  378. +static const struct snd_soc_dai_ops mt7620_i2s_dai_ops = {
  379. + .startup = mt7620_i2s_startup,
  380. + .shutdown = mt7620_i2s_shutdown,
  381. + .trigger = mt7620_i2s_trigger,
  382. + .hw_params = mt7620_i2s_hw_params,
  383. + .set_fmt = mt7620_i2s_set_fmt,
  384. + .set_sysclk = mt7620_i2s_set_sysclk,
  385. +};
  386. +
  387. +#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  388. + SNDRV_PCM_FMTBIT_S24_LE)
  389. +
  390. +static struct snd_soc_dai_driver mt7620_i2s_dai = {
  391. + .probe = mt7620_i2s_dai_probe,
  392. + .remove = mt7620_i2s_dai_remove,
  393. + .playback = {
  394. + .channels_min = 1,
  395. + .channels_max = 2,
  396. + .rates = SNDRV_PCM_RATE_8000_48000,
  397. + .formats = JZ4740_I2S_FMTS,
  398. + },
  399. + .capture = {
  400. + .channels_min = 2,
  401. + .channels_max = 2,
  402. + .rates = SNDRV_PCM_RATE_8000_48000,
  403. + .formats = JZ4740_I2S_FMTS,
  404. + },
  405. + .symmetric_rates = 1,
  406. + .ops = &mt7620_i2s_dai_ops,
  407. +};
  408. +
  409. +static const struct snd_pcm_hardware mt7620_pcm_hardware = {
  410. + .info = SNDRV_PCM_INFO_MMAP |
  411. + SNDRV_PCM_INFO_MMAP_VALID |
  412. + SNDRV_PCM_INFO_INTERLEAVED |
  413. + SNDRV_PCM_INFO_BLOCK_TRANSFER,
  414. + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
  415. + .period_bytes_min = PAGE_SIZE,
  416. + .period_bytes_max = 64 * 1024,
  417. + .periods_min = 2,
  418. + .periods_max = 128,
  419. + .buffer_bytes_max = 128 * 1024,
  420. + .fifo_size = 32,
  421. +};
  422. +
  423. +static const struct snd_dmaengine_pcm_config mt7620_dmaengine_pcm_config = {
  424. + .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
  425. + .pcm_hardware = &mt7620_pcm_hardware,
  426. + .prealloc_buffer_size = 256 * PAGE_SIZE,
  427. +};
  428. +
  429. +static const struct snd_soc_component_driver mt7620_i2s_component = {
  430. + .name = "mt7620-i2s",
  431. +};
  432. +
  433. +static int mt7620_i2s_dev_probe(struct platform_device *pdev)
  434. +{
  435. + struct mt7620_i2s *i2s;
  436. + int ret;
  437. +
  438. + snd_dmaengine_pcm_register(&pdev->dev,
  439. + &mt7620_dmaengine_pcm_config,
  440. + SND_DMAENGINE_PCM_FLAG_COMPAT);
  441. +
  442. + i2s = kzalloc(sizeof(*i2s), GFP_KERNEL);
  443. + if (!i2s)
  444. + return -ENOMEM;
  445. +
  446. + i2s->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  447. + if (!i2s->mem) {
  448. + ret = -ENOENT;
  449. + goto err_free;
  450. + }
  451. +
  452. + i2s->mem = request_mem_region(i2s->mem->start, resource_size(i2s->mem),
  453. + pdev->name);
  454. + if (!i2s->mem) {
  455. + ret = -EBUSY;
  456. + goto err_free;
  457. + }
  458. +
  459. + i2s->base = ioremap_nocache(i2s->mem->start, resource_size(i2s->mem));
  460. + if (!i2s->base) {
  461. + ret = -EBUSY;
  462. + goto err_release_mem_region;
  463. + }
  464. +
  465. + i2s->phys_base = i2s->mem->start;
  466. +
  467. + platform_set_drvdata(pdev, i2s);
  468. + ret = snd_soc_register_component(&pdev->dev, &mt7620_i2s_component,
  469. + &mt7620_i2s_dai, 1);
  470. +
  471. + if (!ret) {
  472. + dev_err(&pdev->dev, "loaded\n");
  473. + return ret;
  474. + }
  475. +
  476. + dev_err(&pdev->dev, "Failed to register DAI\n");
  477. + iounmap(i2s->base);
  478. +
  479. +err_release_mem_region:
  480. + release_mem_region(i2s->mem->start, resource_size(i2s->mem));
  481. +err_free:
  482. + kfree(i2s);
  483. +
  484. + return ret;
  485. +}
  486. +
  487. +static int mt7620_i2s_dev_remove(struct platform_device *pdev)
  488. +{
  489. + struct mt7620_i2s *i2s = platform_get_drvdata(pdev);
  490. +
  491. + snd_soc_unregister_component(&pdev->dev);
  492. +
  493. + iounmap(i2s->base);
  494. + release_mem_region(i2s->mem->start, resource_size(i2s->mem));
  495. +
  496. + kfree(i2s);
  497. +
  498. + snd_dmaengine_pcm_unregister(&pdev->dev);
  499. +
  500. + return 0;
  501. +}
  502. +
  503. +static const struct of_device_id mt7620_i2s_match[] = {
  504. + { .compatible = "ralink,mt7620a-i2s" },
  505. + {},
  506. +};
  507. +MODULE_DEVICE_TABLE(of, mt7620_i2s_match);
  508. +
  509. +static struct platform_driver mt7620_i2s_driver = {
  510. + .probe = mt7620_i2s_dev_probe,
  511. + .remove = mt7620_i2s_dev_remove,
  512. + .driver = {
  513. + .name = "mt7620-i2s",
  514. + .owner = THIS_MODULE,
  515. + .of_match_table = mt7620_i2s_match,
  516. + },
  517. +};
  518. +
  519. +module_platform_driver(mt7620_i2s_driver);
  520. +
  521. +MODULE_AUTHOR("Lars-Peter Clausen, <[email protected]>");
  522. +MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
  523. +MODULE_LICENSE("GPL");
  524. +MODULE_ALIAS("platform:mt7620-i2s");
  525. --- /dev/null
  526. +++ b/sound/soc/ralink/mt7620-wm8960.c
  527. @@ -0,0 +1,233 @@
  528. +/*
  529. + * Copyright 2013 Freescale Semiconductor, Inc.
  530. + *
  531. + * Based on mt7620-sgtl5000.c
  532. + * Copyright 2012 Freescale Semiconductor, Inc.
  533. + * Copyright 2012 Linaro Ltd.
  534. + *
  535. + * The code contained herein is licensed under the GNU General Public
  536. + * License. You may obtain a copy of the GNU General Public License
  537. + * Version 2 or later at the following locations:
  538. + *
  539. + * http://www.opensource.org/licenses/gpl-license.html
  540. + * http://www.gnu.org/copyleft/gpl.html
  541. + */
  542. +
  543. +#include <linux/module.h>
  544. +#include <linux/of_platform.h>
  545. +#include <linux/i2c.h>
  546. +#include <linux/slab.h>
  547. +#include <sound/soc.h>
  548. +#include <sound/pcm_params.h>
  549. +#include <sound/soc-dapm.h>
  550. +#include <linux/pinctrl/consumer.h>
  551. +
  552. +#include "../codecs/wm8960.h"
  553. +
  554. +#define DAI_NAME_SIZE 32
  555. +
  556. +struct mt7620_wm8960_data {
  557. + struct snd_soc_dai_link dai;
  558. + struct snd_soc_card card;
  559. + char codec_dai_name[DAI_NAME_SIZE];
  560. + char platform_name[DAI_NAME_SIZE];
  561. + unsigned int clk_frequency;
  562. +};
  563. +
  564. +struct mt7620_priv {
  565. + struct platform_device *pdev;
  566. +};
  567. +static struct mt7620_priv card_priv;
  568. +
  569. +static const struct snd_soc_dapm_widget mt7620_wm8960_dapm_widgets[] = {
  570. + SND_SOC_DAPM_HP("Headphone Jack", NULL),
  571. + SND_SOC_DAPM_SPK("Ext Spk", NULL),
  572. + SND_SOC_DAPM_MIC("AMIC", NULL),
  573. + SND_SOC_DAPM_MIC("DMIC", NULL),
  574. +};
  575. +
  576. +static int sample_rate = 44100;
  577. +static snd_pcm_format_t sample_format = SNDRV_PCM_FORMAT_S16_LE;
  578. +
  579. +static int mt7620_hifi_hw_params(struct snd_pcm_substream *substream,
  580. + struct snd_pcm_hw_params *params)
  581. +{
  582. + sample_rate = params_rate(params);
  583. + sample_format = params_format(params);
  584. +
  585. + return 0;
  586. +}
  587. +
  588. +static struct snd_soc_ops mt7620_hifi_ops = {
  589. + .hw_params = mt7620_hifi_hw_params,
  590. +};
  591. +
  592. +static int mt7620_wm8960_set_bias_level(struct snd_soc_card *card,
  593. + struct snd_soc_dapm_context *dapm,
  594. + enum snd_soc_bias_level level)
  595. +{
  596. + struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
  597. + struct mt7620_priv *priv = &card_priv;
  598. + struct mt7620_wm8960_data *data = snd_soc_card_get_drvdata(card);
  599. + struct device *dev = &priv->pdev->dev;
  600. + int ret;
  601. +
  602. + if (dapm->dev != codec_dai->dev)
  603. + return 0;
  604. +
  605. + switch (level) {
  606. + case SND_SOC_BIAS_PREPARE:
  607. + if (dapm->bias_level == SND_SOC_BIAS_STANDBY) {
  608. + }
  609. + break;
  610. +
  611. + case SND_SOC_BIAS_STANDBY:
  612. + if (dapm->bias_level == SND_SOC_BIAS_PREPARE) {
  613. + ret = snd_soc_dai_set_sysclk(codec_dai,
  614. + WM8960_SYSCLK_MCLK, data->clk_frequency,
  615. + SND_SOC_CLOCK_IN);
  616. + if (ret < 0) {
  617. + dev_err(dev,
  618. + "failed to switch away from FLL: %d\n",
  619. + ret);
  620. + return ret;
  621. + }
  622. + }
  623. + break;
  624. +
  625. + default:
  626. + break;
  627. + }
  628. +
  629. + return 0;
  630. +}
  631. +
  632. +static int mt7620_wm8960_late_probe(struct snd_soc_card *card)
  633. +{
  634. + struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
  635. + struct mt7620_priv *priv = &card_priv;
  636. + struct mt7620_wm8960_data *data = snd_soc_card_get_drvdata(card);
  637. + struct device *dev = &priv->pdev->dev;
  638. + int ret;
  639. +
  640. + ret = snd_soc_dai_set_sysclk(codec_dai, WM8960_SYSCLK_MCLK,
  641. + data->clk_frequency, SND_SOC_CLOCK_IN);
  642. + if (ret < 0)
  643. + dev_err(dev, "failed to set sysclk in %s\n", __func__);
  644. +
  645. + return ret;
  646. +}
  647. +
  648. +static int mt7620_wm8960_probe(struct platform_device *pdev)
  649. +{
  650. + struct device_node *i2s_np, *codec_np;
  651. + struct platform_device *i2s_pdev;
  652. + struct mt7620_priv *priv = &card_priv;
  653. + struct i2c_client *codec_dev;
  654. + struct mt7620_wm8960_data *data;
  655. + int ret;
  656. +
  657. + priv->pdev = pdev;
  658. +
  659. + i2s_np = of_parse_phandle(pdev->dev.of_node, "i2s-controller", 0);
  660. + codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
  661. + if (!i2s_np || !codec_np) {
  662. + dev_err(&pdev->dev, "phandle missing or invalid\n");
  663. + ret = -EINVAL;
  664. + goto fail;
  665. + }
  666. +
  667. + i2s_pdev = of_find_device_by_node(i2s_np);
  668. + if (!i2s_pdev) {
  669. + dev_err(&pdev->dev, "failed to find SSI platform device\n");
  670. + ret = -EINVAL;
  671. + goto fail;
  672. + }
  673. + codec_dev = of_find_i2c_device_by_node(codec_np);
  674. + if (!codec_dev || !codec_dev->dev.driver) {
  675. + dev_err(&pdev->dev, "failed to find codec platform device\n");
  676. + ret = -EINVAL;
  677. + goto fail;
  678. + }
  679. +
  680. + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
  681. + if (!data) {
  682. + ret = -ENOMEM;
  683. + goto fail;
  684. + }
  685. +
  686. + data->clk_frequency = 12000000;
  687. + data->dai.name = "HiFi";
  688. + data->dai.stream_name = "HiFi";
  689. + data->dai.codec_dai_name = "wm8960-hifi";
  690. + data->dai.codec_of_node = codec_np;
  691. + data->dai.cpu_dai_name = dev_name(&i2s_pdev->dev);
  692. + data->dai.platform_of_node = i2s_np;
  693. + data->dai.ops = &mt7620_hifi_ops;
  694. + data->dai.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
  695. + SND_SOC_DAIFMT_CBM_CFM;
  696. +
  697. + data->card.dev = &pdev->dev;
  698. + ret = snd_soc_of_parse_card_name(&data->card, "model");
  699. + if (ret)
  700. + goto fail;
  701. + ret = snd_soc_of_parse_audio_routing(&data->card, "audio-routing");
  702. + if (ret)
  703. + goto fail;
  704. + data->card.num_links = 1;
  705. + data->card.dai_link = &data->dai;
  706. + data->card.dapm_widgets = mt7620_wm8960_dapm_widgets;
  707. + data->card.num_dapm_widgets = ARRAY_SIZE(mt7620_wm8960_dapm_widgets);
  708. +
  709. + data->card.late_probe = mt7620_wm8960_late_probe;
  710. + data->card.set_bias_level = mt7620_wm8960_set_bias_level;
  711. +
  712. + platform_set_drvdata(pdev, &data->card);
  713. + snd_soc_card_set_drvdata(&data->card, data);
  714. +
  715. + ret = devm_snd_soc_register_card(&pdev->dev, &data->card);
  716. + if (ret) {
  717. + dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
  718. + goto fail;
  719. + }
  720. +
  721. + of_node_put(i2s_np);
  722. + of_node_put(codec_np);
  723. +
  724. + return 0;
  725. +fail:
  726. + if (i2s_np)
  727. + of_node_put(i2s_np);
  728. + if (codec_np)
  729. + of_node_put(codec_np);
  730. +
  731. + return ret;
  732. +}
  733. +
  734. +static int mt7620_wm8960_remove(struct platform_device *pdev)
  735. +{
  736. + return 0;
  737. +}
  738. +
  739. +static const struct of_device_id mt7620_wm8960_dt_ids[] = {
  740. + { .compatible = "mediatek,mt7620-audio-wm8960", },
  741. + { /* sentinel */ }
  742. +};
  743. +MODULE_DEVICE_TABLE(of, mt7620_wm8960_dt_ids);
  744. +
  745. +static struct platform_driver mt7620_wm8960_driver = {
  746. + .driver = {
  747. + .name = "mt7620-wm8960",
  748. + .owner = THIS_MODULE,
  749. + .pm = &snd_soc_pm_ops,
  750. + .of_match_table = mt7620_wm8960_dt_ids,
  751. + },
  752. + .probe = mt7620_wm8960_probe,
  753. + .remove = mt7620_wm8960_remove,
  754. +};
  755. +module_platform_driver(mt7620_wm8960_driver);
  756. +
  757. +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
  758. +MODULE_DESCRIPTION("Freescale i.MX WM8962 ASoC machine driver");
  759. +MODULE_LICENSE("GPL v2");
  760. +MODULE_ALIAS("platform:mt7620-wm8962");