qcom-ipq8064-ap148.dts 3.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229
  1. #include "qcom-ipq8064-v1.0.dtsi"
  2. / {
  3. model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
  4. compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
  5. memory@0 {
  6. reg = <0x42000000 0x1e000000>;
  7. device_type = "memory";
  8. };
  9. reserved-memory {
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. ranges;
  13. rsvd@41200000 {
  14. reg = <0x41200000 0x300000>;
  15. no-map;
  16. };
  17. };
  18. aliases {
  19. serial0 = &gsbi4_serial;
  20. mdio-gpio0 = &mdio0;
  21. };
  22. chosen {
  23. stdout-path = "serial0:115200n8";
  24. };
  25. soc {
  26. mdio0: mdio {
  27. compatible = "virtual,mdio-gpio";
  28. #address-cells = <1>;
  29. #size-cells = <0>;
  30. gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
  31. <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
  32. pinctrl-0 = <&mdio0_pins>;
  33. pinctrl-names = "default";
  34. phy0: ethernet-phy@0 {
  35. reg = <0>;
  36. qca,ar8327-initvals = <
  37. 0x00004 0x7600000 /* PAD0_MODE */
  38. 0x00008 0x1000000 /* PAD5_MODE */
  39. 0x0000c 0x80 /* PAD6_MODE */
  40. 0x000e4 0x6a545 /* MAC_POWER_SEL */
  41. 0x000e0 0xc74164de /* SGMII_CTRL */
  42. 0x0007c 0x4e /* PORT0_STATUS */
  43. 0x00094 0x4e /* PORT6_STATUS */
  44. >;
  45. };
  46. phy4: ethernet-phy@4 {
  47. reg = <4>;
  48. };
  49. };
  50. };
  51. };
  52. &qcom_pinmux {
  53. i2c4_pins: i2c4_pinmux {
  54. pins = "gpio12", "gpio13";
  55. function = "gsbi4";
  56. bias-disable;
  57. };
  58. nand_pins: nand_pins {
  59. disable {
  60. pins = "gpio34", "gpio35", "gpio36",
  61. "gpio37", "gpio38";
  62. function = "nand";
  63. drive-strength = <10>;
  64. bias-disable;
  65. };
  66. pullups {
  67. pins = "gpio39";
  68. function = "nand";
  69. drive-strength = <10>;
  70. bias-pull-up;
  71. };
  72. hold {
  73. pins = "gpio40", "gpio41", "gpio42",
  74. "gpio43", "gpio44", "gpio45",
  75. "gpio46", "gpio47";
  76. function = "nand";
  77. drive-strength = <10>;
  78. bias-bus-hold;
  79. };
  80. };
  81. mdio0_pins: mdio0_pins {
  82. mux {
  83. pins = "gpio0", "gpio1";
  84. function = "gpio";
  85. drive-strength = <8>;
  86. bias-disable;
  87. };
  88. };
  89. rgmii2_pins: rgmii2_pins {
  90. mux {
  91. pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
  92. "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
  93. function = "rgmii2";
  94. drive-strength = <8>;
  95. bias-disable;
  96. };
  97. };
  98. };
  99. &adm_dma {
  100. status = "okay";
  101. };
  102. &gsbi4 {
  103. qcom,mode = <GSBI_PROT_I2C_UART>;
  104. status = "okay";
  105. serial@16340000 {
  106. status = "okay";
  107. };
  108. /*
  109. * The i2c device on gsbi4 should not be enabled.
  110. * On ipq806x designs gsbi4 i2c is meant for exclusive
  111. * RPM usage. Turning this on in kernel manifests as
  112. * i2c failure for the RPM.
  113. */
  114. };
  115. &gsbi5 {
  116. qcom,mode = <GSBI_PROT_SPI>;
  117. status = "okay";
  118. spi4: spi@1a280000 {
  119. status = "okay";
  120. spi-max-frequency = <50000000>;
  121. pinctrl-0 = <&spi_pins>;
  122. pinctrl-names = "default";
  123. cs-gpios = <&qcom_pinmux 20 0>;
  124. flash: m25p80@0 {
  125. compatible = "s25fl256s1";
  126. #address-cells = <1>;
  127. #size-cells = <1>;
  128. spi-max-frequency = <50000000>;
  129. reg = <0>;
  130. partitions {
  131. compatible = "qcom,smem";
  132. };
  133. };
  134. };
  135. };
  136. &usb3_0 {
  137. status = "okay";
  138. };
  139. &usb3_1 {
  140. status = "okay";
  141. };
  142. &pcie0 {
  143. status = "okay";
  144. };
  145. &pcie1 {
  146. status = "okay";
  147. force_gen1 = <1>;
  148. };
  149. &nand {
  150. status = "okay";
  151. pinctrl-0 = <&nand_pins>;
  152. pinctrl-names = "default";
  153. cs0 {
  154. reg = <0>;
  155. compatible = "qcom,nandcs";
  156. nand-ecc-strength = <4>;
  157. nand-bus-width = <8>;
  158. nand-ecc-step-size = <512>;
  159. partitions {
  160. compatible = "qcom,smem";
  161. };
  162. };
  163. };
  164. &gmac1 {
  165. status = "okay";
  166. phy-mode = "rgmii";
  167. qcom,id = <1>;
  168. pinctrl-0 = <&rgmii2_pins>;
  169. pinctrl-names = "default";
  170. fixed-link {
  171. speed = <1000>;
  172. full-duplex;
  173. };
  174. };
  175. &gmac2 {
  176. status = "okay";
  177. phy-mode = "sgmii";
  178. qcom,id = <2>;
  179. fixed-link {
  180. speed = <1000>;
  181. full-duplex;
  182. };
  183. };
  184. &sata_phy {
  185. status = "okay";
  186. };
  187. &sata {
  188. status = "okay";
  189. };