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qcom-ipq8064-db149.dts 3.6 KB

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  1. #include "qcom-ipq8064-v1.0.dtsi"
  2. / {
  3. model = "Qualcomm IPQ8064/DB149";
  4. compatible = "qcom,ipq8064-db149", "qcom,ipq8064";
  5. aliases {
  6. serial0 = &gsbi2_serial;
  7. };
  8. reserved-memory {
  9. #address-cells = <1>;
  10. #size-cells = <1>;
  11. ranges;
  12. rsvd@41200000 {
  13. reg = <0x41200000 0x300000>;
  14. no-map;
  15. };
  16. };
  17. chosen {
  18. stdout-path = "serial0:115200n8";
  19. };
  20. soc {
  21. pinmux@800000 {
  22. i2c4_pins: i2c4_pinmux {
  23. pins = "gpio12", "gpio13";
  24. function = "gsbi4";
  25. bias-disable;
  26. };
  27. spi_pins: spi_pins {
  28. mux {
  29. pins = "gpio18", "gpio19", "gpio21";
  30. function = "gsbi5";
  31. drive-strength = <10>;
  32. bias-none;
  33. };
  34. };
  35. mdio0_pins: mdio0_pins {
  36. mux {
  37. pins = "gpio0", "gpio1";
  38. function = "gpio";
  39. drive-strength = <8>;
  40. bias-disable;
  41. };
  42. };
  43. rgmii0_pins: rgmii0_pins {
  44. mux {
  45. pins = "gpio2", "gpio66";
  46. drive-strength = <8>;
  47. bias-disable;
  48. };
  49. };
  50. };
  51. gsbi2: gsbi@12480000 {
  52. qcom,mode = <GSBI_PROT_I2C_UART>;
  53. status = "okay";
  54. gsbi2_serial: serial@12490000 {
  55. status = "okay";
  56. };
  57. };
  58. gsbi5: gsbi@1a200000 {
  59. qcom,mode = <GSBI_PROT_SPI>;
  60. status = "okay";
  61. spi4: spi@1a280000 {
  62. status = "okay";
  63. spi-max-frequency = <50000000>;
  64. pinctrl-0 = <&spi_pins>;
  65. pinctrl-names = "default";
  66. cs-gpios = <&qcom_pinmux 20 0>;
  67. flash: m25p80@0 {
  68. compatible = "s25fl256s1";
  69. #address-cells = <1>;
  70. #size-cells = <1>;
  71. spi-max-frequency = <50000000>;
  72. reg = <0>;
  73. m25p,fast-read;
  74. partition@0 {
  75. label = "lowlevel_init";
  76. reg = <0x0 0x1b0000>;
  77. };
  78. partition@1 {
  79. label = "u-boot";
  80. reg = <0x1b0000 0x80000>;
  81. };
  82. partition@2 {
  83. label = "u-boot-env";
  84. reg = <0x230000 0x40000>;
  85. };
  86. partition@3 {
  87. label = "caldata";
  88. reg = <0x270000 0x40000>;
  89. };
  90. partition@4 {
  91. label = "firmware";
  92. reg = <0x2b0000 0x1d50000>;
  93. };
  94. };
  95. };
  96. };
  97. sata-phy@1b400000 {
  98. status = "okay";
  99. };
  100. sata@29000000 {
  101. status = "okay";
  102. };
  103. usb3_0: usb3@110f8800 {
  104. status = "okay";
  105. };
  106. usb3_1: usb3@100f8800 {
  107. status = "okay";
  108. };
  109. pcie0: pci@1b500000 {
  110. status = "okay";
  111. };
  112. pcie1: pci@1b700000 {
  113. status = "okay";
  114. };
  115. pcie2: pci@1b900000 {
  116. status = "okay";
  117. };
  118. mdio0: mdio {
  119. compatible = "virtual,mdio-gpio";
  120. #address-cells = <1>;
  121. #size-cells = <0>;
  122. gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>;
  123. pinctrl-0 = <&mdio0_pins>;
  124. pinctrl-names = "default";
  125. phy0: ethernet-phy@0 {
  126. reg = <0>;
  127. qca,ar8327-initvals = <
  128. 0x00004 0x7600000 /* PAD0_MODE */
  129. 0x00008 0x1000000 /* PAD5_MODE */
  130. 0x0000c 0x80 /* PAD6_MODE */
  131. 0x000e4 0x6a545 /* MAC_POWER_SEL */
  132. 0x000e0 0xc74164de /* SGMII_CTRL */
  133. 0x0007c 0x4e /* PORT0_STATUS */
  134. 0x00094 0x4e /* PORT6_STATUS */
  135. >;
  136. };
  137. phy4: ethernet-phy@4 {
  138. reg = <4>;
  139. };
  140. phy6: ethernet-phy@6 {
  141. reg = <6>;
  142. };
  143. phy7: ethernet-phy@7 {
  144. reg = <7>;
  145. };
  146. };
  147. gmac0: ethernet@37000000 {
  148. status = "okay";
  149. phy-mode = "rgmii";
  150. qcom,id = <0>;
  151. phy-handle = <&phy4>;
  152. pinctrl-0 = <&rgmii0_pins>;
  153. pinctrl-names = "default";
  154. };
  155. gmac1: ethernet@37200000 {
  156. status = "okay";
  157. phy-mode = "sgmii";
  158. qcom,id = <1>;
  159. fixed-link {
  160. speed = <1000>;
  161. full-duplex;
  162. };
  163. };
  164. gmac2: ethernet@37400000 {
  165. status = "okay";
  166. phy-mode = "sgmii";
  167. qcom,id = <2>;
  168. phy-handle = <&phy6>;
  169. };
  170. gmac3: ethernet@37600000 {
  171. status = "okay";
  172. phy-mode = "sgmii";
  173. qcom,id = <3>;
  174. phy-handle = <&phy7>;
  175. };
  176. };
  177. };