002-ARM-dts-imx-Add-GW5910-board-support.patch 14 KB

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  1. From a1fb69366bb16753f0fba6a891fbef5cdd97cfbe Mon Sep 17 00:00:00 2001
  2. From: Tim Harvey <[email protected]>
  3. Date: Wed, 8 Jan 2020 07:44:22 -0800
  4. Subject: [PATCH 2/4] ARM: dts: imx: Add GW5910 board support
  5. The Gateworks GW5910 is an IMX6 SoC based single board computer with:
  6. - IMX6Q or IMX6DL
  7. - 32bit DDR3 DRAM
  8. - FEC GbE RJ45 front-panel
  9. - 1x miniPCIe socket with PCI Gen2, USB2
  10. - 1x miniPCIe socket with PCI Gen2, USB2, nanoSIM
  11. - 5V to 60V DC input barrel jack
  12. - 3axis accelerometer (lis2de12)
  13. - GPS (ublox ZOE-M8Q)
  14. - bi-color front-panel LED
  15. - 256MB NAND boot device
  16. - microSD socket (with UHS-I support)
  17. - user pushbutton
  18. - Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
  19. - Dual-Band Wireless MCU (CC1352, UART/I2S interrconnect to IMX6)
  20. - WiFi/Bluetooth/BLE module (Sterling-LSW, SDIO/UART interconnect to IMX6)
  21. - RS232 transceiver (1x UART with flow-control or 2x UART (build option)
  22. - off-board SPI connector (1x chip-select)
  23. Signed-off-by: Tim Harvey <[email protected]>
  24. Signed-off-by: Robert Jones <[email protected]>
  25. Signed-off-by: Shawn Guo <[email protected]>
  26. ---
  27. arch/arm/boot/dts/Makefile | 2 +
  28. arch/arm/boot/dts/imx6dl-gw5910.dts | 14 +
  29. arch/arm/boot/dts/imx6q-gw5910.dts | 14 +
  30. arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 491 ++++++++++++++++++++++++++++++++++
  31. 4 files changed, 521 insertions(+)
  32. create mode 100644 arch/arm/boot/dts/imx6dl-gw5910.dts
  33. create mode 100644 arch/arm/boot/dts/imx6q-gw5910.dts
  34. create mode 100644 arch/arm/boot/dts/imx6qdl-gw5910.dtsi
  35. --- a/arch/arm/boot/dts/Makefile
  36. +++ b/arch/arm/boot/dts/Makefile
  37. @@ -419,6 +419,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
  38. imx6dl-gw5903.dtb \
  39. imx6dl-gw5904.dtb \
  40. imx6dl-gw5907.dtb \
  41. + imx6dl-gw5910.dtb \
  42. imx6dl-hummingboard.dtb \
  43. imx6dl-hummingboard-emmc-som-v15.dtb \
  44. imx6dl-hummingboard-som-v15.dtb \
  45. @@ -491,6 +492,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
  46. imx6q-gw5903.dtb \
  47. imx6q-gw5904.dtb \
  48. imx6q-gw5907.dtb \
  49. + imx6q-gw5910.dtb \
  50. imx6q-h100.dtb \
  51. imx6q-hummingboard.dtb \
  52. imx6q-hummingboard-emmc-som-v15.dtb \
  53. --- /dev/null
  54. +++ b/arch/arm/boot/dts/imx6dl-gw5910.dts
  55. @@ -0,0 +1,14 @@
  56. +// SPDX-License-Identifier: GPL-2.0
  57. +/*
  58. + * Copyright 2019 Gateworks Corporation
  59. + */
  60. +
  61. +/dts-v1/;
  62. +
  63. +#include "imx6dl.dtsi"
  64. +#include "imx6qdl-gw5910.dtsi"
  65. +
  66. +/ {
  67. + model = "Gateworks Ventana i.MX6 DualLite/Solo GW5910";
  68. + compatible = "gw,imx6dl-gw5910", "gw,ventana", "fsl,imx6dl";
  69. +};
  70. --- /dev/null
  71. +++ b/arch/arm/boot/dts/imx6q-gw5910.dts
  72. @@ -0,0 +1,14 @@
  73. +// SPDX-License-Identifier: GPL-2.0
  74. +/*
  75. + * Copyright 2019 Gateworks Corporation
  76. + */
  77. +
  78. +/dts-v1/;
  79. +
  80. +#include "imx6q.dtsi"
  81. +#include "imx6qdl-gw5910.dtsi"
  82. +
  83. +/ {
  84. + model = "Gateworks Ventana i.MX6 Dual/Quad GW5910";
  85. + compatible = "gw,imx6q-gw5910", "gw,ventana", "fsl,imx6q";
  86. +};
  87. --- /dev/null
  88. +++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
  89. @@ -0,0 +1,489 @@
  90. +// SPDX-License-Identifier: GPL-2.0
  91. +/*
  92. + * Copyright 2019 Gateworks Corporation
  93. + */
  94. +
  95. +#include <dt-bindings/gpio/gpio.h>
  96. +
  97. +/ {
  98. + /* these are used by bootloader for disabling nodes */
  99. + aliases {
  100. + led0 = &led0;
  101. + led1 = &led1;
  102. + led2 = &led2;
  103. + };
  104. +
  105. + chosen {
  106. + stdout-path = &uart2;
  107. + };
  108. +
  109. + memory@10000000 {
  110. + device_type = "memory";
  111. + reg = <0x10000000 0x20000000>;
  112. + };
  113. +
  114. + leds {
  115. + compatible = "gpio-leds";
  116. + pinctrl-names = "default";
  117. + pinctrl-0 = <&pinctrl_gpio_leds>;
  118. +
  119. + led0: user1 {
  120. + label = "user1";
  121. + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  122. + default-state = "on";
  123. + linux,default-trigger = "heartbeat";
  124. + };
  125. +
  126. + led1: user2 {
  127. + label = "user2";
  128. + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  129. + };
  130. +
  131. + led2: user3 {
  132. + label = "user3";
  133. + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  134. + };
  135. + };
  136. +
  137. + pps {
  138. + compatible = "pps-gpio";
  139. + pinctrl-names = "default";
  140. + pinctrl-0 = <&pinctrl_pps>;
  141. + gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
  142. + status = "okay";
  143. + };
  144. +
  145. + reg_3p3v: regulator-3p3v {
  146. + compatible = "regulator-fixed";
  147. + regulator-name = "3P3V";
  148. + regulator-min-microvolt = <3300000>;
  149. + regulator-max-microvolt = <3300000>;
  150. + regulator-always-on;
  151. + };
  152. +
  153. + reg_5p0v: regulator-5p0v {
  154. + compatible = "regulator-fixed";
  155. + regulator-name = "5P0V";
  156. + regulator-min-microvolt = <5000000>;
  157. + regulator-max-microvolt = <5000000>;
  158. + regulator-always-on;
  159. + };
  160. +
  161. + reg_wl: regulator-wl {
  162. + pinctrl-names = "default";
  163. + pinctrl-0 = <&pinctrl_reg_wl>;
  164. + compatible = "regulator-fixed";
  165. + regulator-name = "wl";
  166. + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  167. + startup-delay-us = <100>;
  168. + enable-active-high;
  169. + regulator-min-microvolt = <3300000>;
  170. + regulator-max-microvolt = <3300000>;
  171. + regulator-always-on;
  172. + };
  173. +
  174. + reg_bt: regulator-bt {
  175. + pinctrl-names = "default";
  176. + pinctrl-0 = <&pinctrl_reg_bt>;
  177. + compatible = "regulator-fixed";
  178. + regulator-name = "bt";
  179. + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
  180. + startup-delay-us = <100>;
  181. + enable-active-high;
  182. + regulator-min-microvolt = <3300000>;
  183. + regulator-max-microvolt = <3300000>;
  184. + regulator-always-on;
  185. + };
  186. +};
  187. +
  188. +
  189. +&ecspi3 {
  190. + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
  191. + pinctrl-names = "default";
  192. + pinctrl-0 = <&pinctrl_ecspi3>;
  193. + status = "okay";
  194. +};
  195. +
  196. +&fec {
  197. + pinctrl-names = "default";
  198. + pinctrl-0 = <&pinctrl_enet>;
  199. + phy-mode = "rgmii-id";
  200. + status = "okay";
  201. +};
  202. +
  203. +&gpmi {
  204. + pinctrl-names = "default";
  205. + pinctrl-0 = <&pinctrl_gpmi_nand>;
  206. + status = "okay";
  207. +};
  208. +
  209. +&i2c1 {
  210. + clock-frequency = <100000>;
  211. + pinctrl-names = "default";
  212. + pinctrl-0 = <&pinctrl_i2c1>;
  213. + status = "okay";
  214. +
  215. + gpio@23 {
  216. + compatible = "nxp,pca9555";
  217. + reg = <0x23>;
  218. + gpio-controller;
  219. + #gpio-cells = <2>;
  220. + };
  221. +
  222. + eeprom@50 {
  223. + compatible = "atmel,24c02";
  224. + reg = <0x50>;
  225. + pagesize = <16>;
  226. + };
  227. +
  228. + eeprom@51 {
  229. + compatible = "atmel,24c02";
  230. + reg = <0x51>;
  231. + pagesize = <16>;
  232. + };
  233. +
  234. + eeprom@52 {
  235. + compatible = "atmel,24c02";
  236. + reg = <0x52>;
  237. + pagesize = <16>;
  238. + };
  239. +
  240. + eeprom@53 {
  241. + compatible = "atmel,24c02";
  242. + reg = <0x53>;
  243. + pagesize = <16>;
  244. + };
  245. +
  246. + rtc@68 {
  247. + compatible = "dallas,ds1672";
  248. + reg = <0x68>;
  249. + };
  250. +};
  251. +
  252. +&i2c2 {
  253. + clock-frequency = <100000>;
  254. + pinctrl-names = "default";
  255. + pinctrl-0 = <&pinctrl_i2c2>;
  256. + status = "okay";
  257. +};
  258. +
  259. +&i2c3 {
  260. + clock-frequency = <100000>;
  261. + pinctrl-names = "default";
  262. + pinctrl-0 = <&pinctrl_i2c3>;
  263. + status = "okay";
  264. +
  265. + accel@19 {
  266. + pinctrl-names = "default";
  267. + pinctrl-0 = <&pinctrl_accel>;
  268. + compatible = "st,lis2de12";
  269. + reg = <0x19>;
  270. + st,drdy-int-pin = <1>;
  271. + interrupt-parent = <&gpio7>;
  272. + interrupts = <13 0>;
  273. + interrupt-names = "INT1";
  274. + };
  275. +};
  276. +
  277. +&pcie {
  278. + pinctrl-names = "default";
  279. + pinctrl-0 = <&pinctrl_pcie>;
  280. + reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
  281. + status = "okay";
  282. +};
  283. +
  284. +&pwm2 {
  285. + pinctrl-names = "default";
  286. + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  287. + status = "disabled";
  288. +};
  289. +
  290. +&pwm3 {
  291. + pinctrl-names = "default";
  292. + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  293. + status = "disabled";
  294. +};
  295. +
  296. +/* off-board RS232 */
  297. +&uart1 {
  298. + pinctrl-names = "default";
  299. + pinctrl-0 = <&pinctrl_uart1>;
  300. + status = "okay";
  301. +};
  302. +
  303. +/* serial console */
  304. +&uart2 {
  305. + pinctrl-names = "default";
  306. + pinctrl-0 = <&pinctrl_uart2>;
  307. + status = "okay";
  308. +};
  309. +
  310. +/* Sterling-LWB Bluetooth */
  311. +&uart4 {
  312. + pinctrl-names = "default";
  313. + pinctrl-0 = <&pinctrl_uart4>;
  314. + uart-has-rtscts;
  315. + status = "okay";
  316. +};
  317. +
  318. +/* GPS */
  319. +&uart5 {
  320. + pinctrl-names = "default";
  321. + pinctrl-0 = <&pinctrl_uart5>;
  322. + status = "okay";
  323. +};
  324. +
  325. +&usbotg {
  326. + vbus-supply = <&reg_5p0v>;
  327. + pinctrl-names = "default";
  328. + pinctrl-0 = <&pinctrl_usbotg>;
  329. + disable-over-current;
  330. + status = "okay";
  331. +};
  332. +
  333. +&usbh1 {
  334. + status = "okay";
  335. +};
  336. +
  337. +/* Sterling-LWB SDIO WiFi */
  338. +&usdhc2 {
  339. + pinctrl-names = "default";
  340. + pinctrl-0 = <&pinctrl_usdhc2>;
  341. + vmmc-supply = <&reg_3p3v>;
  342. + non-removable;
  343. + bus-width = <4>;
  344. + status = "okay";
  345. +};
  346. +
  347. +&usdhc3 {
  348. + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  349. + pinctrl-0 = <&pinctrl_usdhc3>;
  350. + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  351. + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  352. + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
  353. + vmmc-supply = <&reg_3p3v>;
  354. + status = "okay";
  355. +};
  356. +
  357. +&wdog1 {
  358. + pinctrl-names = "default";
  359. + pinctrl-0 = <&pinctrl_wdog>;
  360. + fsl,ext-reset-output;
  361. +};
  362. +
  363. +&iomuxc {
  364. + pinctrl_accel: accelmuxgrp {
  365. + fsl,pins = <
  366. + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
  367. + >;
  368. + };
  369. +
  370. + pinctrl_ecspi3: escpi3grp {
  371. + fsl,pins = <
  372. + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
  373. + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
  374. + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
  375. + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
  376. + >;
  377. + };
  378. +
  379. + pinctrl_enet: enetgrp {
  380. + fsl,pins = <
  381. + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
  382. + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
  383. + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
  384. + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
  385. + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
  386. + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
  387. + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
  388. + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
  389. + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
  390. + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
  391. + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
  392. + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
  393. + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  394. + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  395. + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  396. + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  397. + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
  398. + >;
  399. + };
  400. +
  401. + pinctrl_gpio_leds: gpioledsgrp {
  402. + fsl,pins = <
  403. + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
  404. + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
  405. + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
  406. + >;
  407. + };
  408. +
  409. + pinctrl_gpmi_nand: gpminandgrp {
  410. + fsl,pins = <
  411. + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  412. + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  413. + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  414. + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  415. + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  416. + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  417. + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  418. + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  419. + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  420. + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  421. + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  422. + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  423. + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  424. + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  425. + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  426. + >;
  427. + };
  428. +
  429. + pinctrl_i2c1: i2c1grp {
  430. + fsl,pins = <
  431. + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
  432. + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
  433. + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
  434. + >;
  435. + };
  436. +
  437. + pinctrl_i2c2: i2c2grp {
  438. + fsl,pins = <
  439. + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
  440. + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
  441. + >;
  442. + };
  443. +
  444. + pinctrl_i2c3: i2c3grp {
  445. + fsl,pins = <
  446. + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
  447. + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
  448. + >;
  449. + };
  450. +
  451. + pinctrl_pcie: pciegrp {
  452. + fsl,pins = <
  453. + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
  454. + >;
  455. + };
  456. +
  457. + pinctrl_pps: ppsgrp {
  458. + fsl,pins = <
  459. + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1
  460. + >;
  461. + };
  462. +
  463. + pinctrl_pwm2: pwm2grp {
  464. + fsl,pins = <
  465. + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  466. + >;
  467. + };
  468. +
  469. + pinctrl_pwm3: pwm3grp {
  470. + fsl,pins = <
  471. + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  472. + >;
  473. + };
  474. +
  475. + pinctrl_reg_bt: regbtgrp {
  476. + fsl,pins = <
  477. + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
  478. + >;
  479. + };
  480. +
  481. + pinctrl_reg_wl: regwlgrp {
  482. + fsl,pins = <
  483. + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
  484. + >;
  485. + };
  486. +
  487. + pinctrl_uart1: uart1grp {
  488. + fsl,pins = <
  489. + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  490. + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  491. + >;
  492. + };
  493. +
  494. + pinctrl_uart2: uart2grp {
  495. + fsl,pins = <
  496. + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  497. + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
  498. + >;
  499. + };
  500. +
  501. + pinctrl_uart4: uart4grp {
  502. + fsl,pins = <
  503. + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
  504. + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
  505. + MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
  506. + MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
  507. + >;
  508. + };
  509. +
  510. + pinctrl_uart5: uart5grp {
  511. + fsl,pins = <
  512. + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
  513. + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
  514. + >;
  515. + };
  516. +
  517. + pinctrl_usbotg: usbotggrp {
  518. + fsl,pins = <
  519. + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
  520. + >;
  521. + };
  522. +
  523. + pinctrl_usdhc2: usdhc2grp {
  524. + fsl,pins = <
  525. + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  526. + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  527. + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  528. + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  529. + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  530. + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  531. + >;
  532. + };
  533. +
  534. + pinctrl_usdhc3: usdhc3grp {
  535. + fsl,pins = <
  536. + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
  537. + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
  538. + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  539. + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  540. + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  541. + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  542. + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
  543. + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
  544. + >;
  545. + };
  546. +
  547. + pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  548. + fsl,pins = <
  549. + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
  550. + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
  551. + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
  552. + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
  553. + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
  554. + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
  555. + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
  556. + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
  557. + >;
  558. + };
  559. +
  560. + pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  561. + fsl,pins = <
  562. + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
  563. + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
  564. + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
  565. + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
  566. + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
  567. + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
  568. + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
  569. + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
  570. + >;
  571. + };
  572. +
  573. + pinctrl_wdog: wdoggrp {
  574. + fsl,pins = <
  575. + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
  576. + >;
  577. + };
  578. +};