402-mtd-support-layerscape.patch 13 KB

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  1. From c0e4767d3b26f21e5043fe2d15a24a1958de766e Mon Sep 17 00:00:00 2001
  2. From: Yangbo Lu <[email protected]>
  3. Date: Mon, 25 Sep 2017 10:17:28 +0800
  4. Subject: [PATCH] mtd: support layerscape
  5. This is a integrated patch for layerscape ifc-nor-nand support.
  6. Signed-off-by: Alison Wang <[email protected]>
  7. Signed-off-by: Prabhakar Kushwaha <[email protected]>
  8. Signed-off-by: Yangbo Lu <[email protected]>
  9. ---
  10. drivers/memory/Kconfig | 2 +-
  11. drivers/memory/fsl_ifc.c | 263 ++++++++++++++++++++++++++++++++++++++++
  12. drivers/mtd/maps/physmap_of.c | 4 +
  13. drivers/mtd/nand/Kconfig | 2 +-
  14. drivers/mtd/nand/fsl_ifc_nand.c | 5 +-
  15. include/linux/fsl_ifc.h | 7 ++
  16. 6 files changed, 280 insertions(+), 3 deletions(-)
  17. --- a/drivers/memory/Kconfig
  18. +++ b/drivers/memory/Kconfig
  19. @@ -115,7 +115,7 @@ config FSL_CORENET_CF
  20. config FSL_IFC
  21. bool
  22. - depends on FSL_SOC || ARCH_LAYERSCAPE
  23. + depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A
  24. config JZ4780_NEMC
  25. bool "Ingenic JZ4780 SoC NEMC driver"
  26. --- a/drivers/memory/fsl_ifc.c
  27. +++ b/drivers/memory/fsl_ifc.c
  28. @@ -24,6 +24,7 @@
  29. #include <linux/compiler.h>
  30. #include <linux/sched.h>
  31. #include <linux/spinlock.h>
  32. +#include <linux/delay.h>
  33. #include <linux/types.h>
  34. #include <linux/slab.h>
  35. #include <linux/io.h>
  36. @@ -37,6 +38,8 @@
  37. struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
  38. EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
  39. +#define FSL_IFC_V1_3_0 0x01030000
  40. +#define IFC_TIMEOUT_MSECS 1000 /* 1000ms */
  41. /*
  42. * convert_ifc_address - convert the base address
  43. @@ -311,6 +314,261 @@ err:
  44. return ret;
  45. }
  46. +#ifdef CONFIG_PM_SLEEP
  47. +/* save ifc registers */
  48. +static int fsl_ifc_suspend(struct device *dev)
  49. +{
  50. + struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
  51. + struct fsl_ifc_global __iomem *fcm = ctrl->gregs;
  52. + struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
  53. + __be32 nand_evter_intr_en, cm_evter_intr_en, nor_evter_intr_en,
  54. + gpcm_evter_intr_en;
  55. + uint32_t ifc_bank, i;
  56. +
  57. + ctrl->saved_gregs = kzalloc(sizeof(struct fsl_ifc_global), GFP_KERNEL);
  58. + if (!ctrl->saved_gregs)
  59. + return -ENOMEM;
  60. + ctrl->saved_rregs = kzalloc(sizeof(struct fsl_ifc_runtime), GFP_KERNEL);
  61. + if (!ctrl->saved_rregs)
  62. + return -ENOMEM;
  63. +
  64. + cm_evter_intr_en = ifc_in32(&fcm->cm_evter_intr_en);
  65. + nand_evter_intr_en = ifc_in32(&runtime->ifc_nand.nand_evter_intr_en);
  66. + nor_evter_intr_en = ifc_in32(&runtime->ifc_nor.nor_evter_intr_en);
  67. + gpcm_evter_intr_en = ifc_in32(&runtime->ifc_gpcm.gpcm_evter_intr_en);
  68. +
  69. +/* IFC interrupts disabled */
  70. +
  71. + ifc_out32(0x0, &fcm->cm_evter_intr_en);
  72. + ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
  73. + ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
  74. + ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
  75. +
  76. + if (ctrl->saved_gregs) {
  77. + for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
  78. + ctrl->saved_gregs->cspr_cs[ifc_bank].cspr_ext =
  79. + ifc_in32(&fcm->cspr_cs[ifc_bank].cspr_ext);
  80. + ctrl->saved_gregs->cspr_cs[ifc_bank].cspr =
  81. + ifc_in32(&fcm->cspr_cs[ifc_bank].cspr);
  82. + ctrl->saved_gregs->amask_cs[ifc_bank].amask =
  83. + ifc_in32(&fcm->amask_cs[ifc_bank].amask);
  84. + ctrl->saved_gregs->csor_cs[ifc_bank].csor_ext =
  85. + ifc_in32(&fcm->csor_cs[ifc_bank].csor_ext);
  86. + ctrl->saved_gregs->csor_cs[ifc_bank].csor =
  87. + ifc_in32(&fcm->csor_cs[ifc_bank].csor);
  88. + for (i = 0; i < 4; i++) {
  89. + ctrl->saved_gregs->ftim_cs[ifc_bank].ftim[i] =
  90. + ifc_in32(
  91. + &fcm->ftim_cs[ifc_bank].ftim[i]);
  92. + }
  93. + }
  94. +
  95. + ctrl->saved_gregs->rb_map = ifc_in32(&fcm->rb_map);
  96. + ctrl->saved_gregs->wb_map = ifc_in32(&fcm->wb_map);
  97. + ctrl->saved_gregs->ifc_gcr = ifc_in32(&fcm->ifc_gcr);
  98. + ctrl->saved_gregs->ddr_ccr_low = ifc_in32(&fcm->ddr_ccr_low);
  99. + ctrl->saved_gregs->cm_evter_en = ifc_in32(&fcm->cm_evter_en);
  100. + }
  101. +
  102. + if (ctrl->saved_rregs) {
  103. + /* IFC controller NAND machine registers */
  104. + ctrl->saved_rregs->ifc_nand.ncfgr =
  105. + ifc_in32(&runtime->ifc_nand.ncfgr);
  106. + ctrl->saved_rregs->ifc_nand.nand_fcr0 =
  107. + ifc_in32(&runtime->ifc_nand.nand_fcr0);
  108. + ctrl->saved_rregs->ifc_nand.nand_fcr1 =
  109. + ifc_in32(&runtime->ifc_nand.nand_fcr1);
  110. + ctrl->saved_rregs->ifc_nand.row0 =
  111. + ifc_in32(&runtime->ifc_nand.row0);
  112. + ctrl->saved_rregs->ifc_nand.row1 =
  113. + ifc_in32(&runtime->ifc_nand.row1);
  114. + ctrl->saved_rregs->ifc_nand.col0 =
  115. + ifc_in32(&runtime->ifc_nand.col0);
  116. + ctrl->saved_rregs->ifc_nand.col1 =
  117. + ifc_in32(&runtime->ifc_nand.col1);
  118. + ctrl->saved_rregs->ifc_nand.row2 =
  119. + ifc_in32(&runtime->ifc_nand.row2);
  120. + ctrl->saved_rregs->ifc_nand.col2 =
  121. + ifc_in32(&runtime->ifc_nand.col2);
  122. + ctrl->saved_rregs->ifc_nand.row3 =
  123. + ifc_in32(&runtime->ifc_nand.row3);
  124. + ctrl->saved_rregs->ifc_nand.col3 =
  125. + ifc_in32(&runtime->ifc_nand.col3);
  126. +
  127. + ctrl->saved_rregs->ifc_nand.nand_fbcr =
  128. + ifc_in32(&runtime->ifc_nand.nand_fbcr);
  129. + ctrl->saved_rregs->ifc_nand.nand_fir0 =
  130. + ifc_in32(&runtime->ifc_nand.nand_fir0);
  131. + ctrl->saved_rregs->ifc_nand.nand_fir1 =
  132. + ifc_in32(&runtime->ifc_nand.nand_fir1);
  133. + ctrl->saved_rregs->ifc_nand.nand_fir2 =
  134. + ifc_in32(&runtime->ifc_nand.nand_fir2);
  135. + ctrl->saved_rregs->ifc_nand.nand_csel =
  136. + ifc_in32(&runtime->ifc_nand.nand_csel);
  137. + ctrl->saved_rregs->ifc_nand.nandseq_strt =
  138. + ifc_in32(
  139. + &runtime->ifc_nand.nandseq_strt);
  140. + ctrl->saved_rregs->ifc_nand.nand_evter_en =
  141. + ifc_in32(
  142. + &runtime->ifc_nand.nand_evter_en);
  143. + ctrl->saved_rregs->ifc_nand.nanndcr =
  144. + ifc_in32(&runtime->ifc_nand.nanndcr);
  145. + ctrl->saved_rregs->ifc_nand.nand_dll_lowcfg0 =
  146. + ifc_in32(
  147. + &runtime->ifc_nand.nand_dll_lowcfg0);
  148. + ctrl->saved_rregs->ifc_nand.nand_dll_lowcfg1 =
  149. + ifc_in32(
  150. + &runtime->ifc_nand.nand_dll_lowcfg1);
  151. +
  152. + /* IFC controller NOR machine registers */
  153. + ctrl->saved_rregs->ifc_nor.nor_evter_en =
  154. + ifc_in32(
  155. + &runtime->ifc_nor.nor_evter_en);
  156. + ctrl->saved_rregs->ifc_nor.norcr =
  157. + ifc_in32(&runtime->ifc_nor.norcr);
  158. +
  159. + /* IFC controller GPCM Machine registers */
  160. + ctrl->saved_rregs->ifc_gpcm.gpcm_evter_en =
  161. + ifc_in32(
  162. + &runtime->ifc_gpcm.gpcm_evter_en);
  163. + }
  164. +
  165. +/* save the interrupt values */
  166. + ctrl->saved_gregs->cm_evter_intr_en = cm_evter_intr_en;
  167. + ctrl->saved_rregs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en;
  168. + ctrl->saved_rregs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en;
  169. + ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en;
  170. +
  171. + return 0;
  172. +}
  173. +
  174. +/* restore ifc registers */
  175. +static int fsl_ifc_resume(struct device *dev)
  176. +{
  177. + struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
  178. + struct fsl_ifc_global __iomem *fcm = ctrl->gregs;
  179. + struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
  180. + struct fsl_ifc_global *savd_gregs = ctrl->saved_gregs;
  181. + struct fsl_ifc_runtime *savd_rregs = ctrl->saved_rregs;
  182. + uint32_t ver = 0, ncfgr, timeout, ifc_bank, i;
  183. +
  184. +/*
  185. + * IFC interrupts disabled
  186. + */
  187. + ifc_out32(0x0, &fcm->cm_evter_intr_en);
  188. + ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
  189. + ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
  190. + ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
  191. +
  192. +
  193. + if (ctrl->saved_gregs) {
  194. + for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
  195. + ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr_ext,
  196. + &fcm->cspr_cs[ifc_bank].cspr_ext);
  197. + ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr,
  198. + &fcm->cspr_cs[ifc_bank].cspr);
  199. + ifc_out32(savd_gregs->amask_cs[ifc_bank].amask,
  200. + &fcm->amask_cs[ifc_bank].amask);
  201. + ifc_out32(savd_gregs->csor_cs[ifc_bank].csor_ext,
  202. + &fcm->csor_cs[ifc_bank].csor_ext);
  203. + ifc_out32(savd_gregs->csor_cs[ifc_bank].csor,
  204. + &fcm->csor_cs[ifc_bank].csor);
  205. + for (i = 0; i < 4; i++) {
  206. + ifc_out32(savd_gregs->ftim_cs[ifc_bank].ftim[i],
  207. + &fcm->ftim_cs[ifc_bank].ftim[i]);
  208. + }
  209. + }
  210. + ifc_out32(savd_gregs->rb_map, &fcm->rb_map);
  211. + ifc_out32(savd_gregs->wb_map, &fcm->wb_map);
  212. + ifc_out32(savd_gregs->ifc_gcr, &fcm->ifc_gcr);
  213. + ifc_out32(savd_gregs->ddr_ccr_low, &fcm->ddr_ccr_low);
  214. + ifc_out32(savd_gregs->cm_evter_en, &fcm->cm_evter_en);
  215. + }
  216. +
  217. + if (ctrl->saved_rregs) {
  218. + /* IFC controller NAND machine registers */
  219. + ifc_out32(savd_rregs->ifc_nand.ncfgr,
  220. + &runtime->ifc_nand.ncfgr);
  221. + ifc_out32(savd_rregs->ifc_nand.nand_fcr0,
  222. + &runtime->ifc_nand.nand_fcr0);
  223. + ifc_out32(savd_rregs->ifc_nand.nand_fcr1,
  224. + &runtime->ifc_nand.nand_fcr1);
  225. + ifc_out32(savd_rregs->ifc_nand.row0, &runtime->ifc_nand.row0);
  226. + ifc_out32(savd_rregs->ifc_nand.row1, &runtime->ifc_nand.row1);
  227. + ifc_out32(savd_rregs->ifc_nand.col0, &runtime->ifc_nand.col0);
  228. + ifc_out32(savd_rregs->ifc_nand.col1, &runtime->ifc_nand.col1);
  229. + ifc_out32(savd_rregs->ifc_nand.row2, &runtime->ifc_nand.row2);
  230. + ifc_out32(savd_rregs->ifc_nand.col2, &runtime->ifc_nand.col2);
  231. + ifc_out32(savd_rregs->ifc_nand.row3, &runtime->ifc_nand.row3);
  232. + ifc_out32(savd_rregs->ifc_nand.col3, &runtime->ifc_nand.col3);
  233. + ifc_out32(savd_rregs->ifc_nand.nand_fbcr,
  234. + &runtime->ifc_nand.nand_fbcr);
  235. + ifc_out32(savd_rregs->ifc_nand.nand_fir0,
  236. + &runtime->ifc_nand.nand_fir0);
  237. + ifc_out32(savd_rregs->ifc_nand.nand_fir1,
  238. + &runtime->ifc_nand.nand_fir1);
  239. + ifc_out32(savd_rregs->ifc_nand.nand_fir2,
  240. + &runtime->ifc_nand.nand_fir2);
  241. + ifc_out32(savd_rregs->ifc_nand.nand_csel,
  242. + &runtime->ifc_nand.nand_csel);
  243. + ifc_out32(savd_rregs->ifc_nand.nandseq_strt,
  244. + &runtime->ifc_nand.nandseq_strt);
  245. + ifc_out32(savd_rregs->ifc_nand.nand_evter_en,
  246. + &runtime->ifc_nand.nand_evter_en);
  247. + ifc_out32(savd_rregs->ifc_nand.nanndcr,
  248. + &runtime->ifc_nand.nanndcr);
  249. + ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg0,
  250. + &runtime->ifc_nand.nand_dll_lowcfg0);
  251. + ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg1,
  252. + &runtime->ifc_nand.nand_dll_lowcfg1);
  253. +
  254. + /* IFC controller NOR machine registers */
  255. + ifc_out32(savd_rregs->ifc_nor.nor_evter_en,
  256. + &runtime->ifc_nor.nor_evter_en);
  257. + ifc_out32(savd_rregs->ifc_nor.norcr, &runtime->ifc_nor.norcr);
  258. +
  259. + /* IFC controller GPCM Machine registers */
  260. + ifc_out32(savd_rregs->ifc_gpcm.gpcm_evter_en,
  261. + &runtime->ifc_gpcm.gpcm_evter_en);
  262. +
  263. + /* IFC interrupts enabled */
  264. + ifc_out32(ctrl->saved_gregs->cm_evter_intr_en,
  265. + &fcm->cm_evter_intr_en);
  266. + ifc_out32(ctrl->saved_rregs->ifc_nand.nand_evter_intr_en,
  267. + &runtime->ifc_nand.nand_evter_intr_en);
  268. + ifc_out32(ctrl->saved_rregs->ifc_nor.nor_evter_intr_en,
  269. + &runtime->ifc_nor.nor_evter_intr_en);
  270. + ifc_out32(ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en,
  271. + &runtime->ifc_gpcm.gpcm_evter_intr_en);
  272. +
  273. + kfree(ctrl->saved_gregs);
  274. + kfree(ctrl->saved_rregs);
  275. + ctrl->saved_gregs = NULL;
  276. + ctrl->saved_rregs = NULL;
  277. + }
  278. +
  279. + ver = ifc_in32(&fcm->ifc_rev);
  280. + ncfgr = ifc_in32(&runtime->ifc_nand.ncfgr);
  281. + if (ver >= FSL_IFC_V1_3_0) {
  282. +
  283. + ifc_out32(ncfgr | IFC_NAND_SRAM_INIT_EN,
  284. + &runtime->ifc_nand.ncfgr);
  285. + /* wait for SRAM_INIT bit to be clear or timeout */
  286. + timeout = 10;
  287. + while ((ifc_in32(&runtime->ifc_nand.ncfgr) &
  288. + IFC_NAND_SRAM_INIT_EN) && timeout) {
  289. + mdelay(IFC_TIMEOUT_MSECS);
  290. + timeout--;
  291. + }
  292. +
  293. + if (!timeout)
  294. + dev_err(ctrl->dev, "Timeout waiting for IFC SRAM INIT");
  295. + }
  296. +
  297. + return 0;
  298. +}
  299. +#endif /* CONFIG_PM_SLEEP */
  300. +
  301. static const struct of_device_id fsl_ifc_match[] = {
  302. {
  303. .compatible = "fsl,ifc",
  304. @@ -318,10 +576,15 @@ static const struct of_device_id fsl_ifc
  305. {},
  306. };
  307. +static const struct dev_pm_ops ifc_pm_ops = {
  308. + SET_SYSTEM_SLEEP_PM_OPS(fsl_ifc_suspend, fsl_ifc_resume)
  309. +};
  310. +
  311. static struct platform_driver fsl_ifc_ctrl_driver = {
  312. .driver = {
  313. .name = "fsl-ifc",
  314. .of_match_table = fsl_ifc_match,
  315. + .pm = &ifc_pm_ops,
  316. },
  317. .probe = fsl_ifc_ctrl_probe,
  318. .remove = fsl_ifc_ctrl_remove,
  319. --- a/drivers/mtd/maps/physmap_of.c
  320. +++ b/drivers/mtd/maps/physmap_of.c
  321. @@ -20,6 +20,7 @@
  322. #include <linux/mtd/map.h>
  323. #include <linux/mtd/partitions.h>
  324. #include <linux/mtd/concat.h>
  325. +#include <linux/mtd/cfi_endian.h>
  326. #include <linux/of.h>
  327. #include <linux/of_address.h>
  328. #include <linux/of_platform.h>
  329. @@ -209,6 +210,9 @@ static int of_flash_probe(struct platfor
  330. return err;
  331. }
  332. + if (of_property_read_bool(dp->parent, "big-endian"))
  333. + info->list[i].map.swap = CFI_BIG_ENDIAN;
  334. +
  335. err = -ENOMEM;
  336. info->list[i].map.virt = ioremap(info->list[i].map.phys,
  337. info->list[i].map.size);
  338. --- a/drivers/mtd/nand/Kconfig
  339. +++ b/drivers/mtd/nand/Kconfig
  340. @@ -438,7 +438,7 @@ config MTD_NAND_FSL_ELBC
  341. config MTD_NAND_FSL_IFC
  342. tristate "NAND support for Freescale IFC controller"
  343. - depends on FSL_SOC || ARCH_LAYERSCAPE
  344. + depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A
  345. select FSL_IFC
  346. select MEMORY
  347. help
  348. --- a/drivers/mtd/nand/fsl_ifc_nand.c
  349. +++ b/drivers/mtd/nand/fsl_ifc_nand.c
  350. @@ -904,9 +904,12 @@ static int fsl_ifc_chip_init(struct fsl_
  351. chip->ecc.algo = NAND_ECC_HAMMING;
  352. }
  353. - if (ctrl->version == FSL_IFC_VERSION_1_1_0)
  354. + if (ctrl->version >= FSL_IFC_VERSION_1_1_0)
  355. fsl_ifc_sram_init(priv);
  356. + if (ctrl->version >= FSL_IFC_VERSION_2_0_0)
  357. + priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
  358. +
  359. return 0;
  360. }
  361. --- a/include/linux/fsl_ifc.h
  362. +++ b/include/linux/fsl_ifc.h
  363. @@ -274,6 +274,8 @@
  364. */
  365. /* Auto Boot Mode */
  366. #define IFC_NAND_NCFGR_BOOT 0x80000000
  367. +/* SRAM INIT EN */
  368. +#define IFC_NAND_SRAM_INIT_EN 0x20000000
  369. /* Addressing Mode-ROW0+n/COL0 */
  370. #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
  371. /* Addressing Mode-ROW0+n/COL0+n */
  372. @@ -861,6 +863,11 @@ struct fsl_ifc_ctrl {
  373. u32 nand_stat;
  374. wait_queue_head_t nand_wait;
  375. bool little_endian;
  376. +#ifdef CONFIG_PM_SLEEP
  377. + /*save regs when system goes to deep sleep*/
  378. + struct fsl_ifc_global *saved_gregs;
  379. + struct fsl_ifc_runtime *saved_rregs;
  380. +#endif
  381. };
  382. extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;