openwrt/target/linux/ath79/dts/ar7100.dtsi

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include <dt-bindings/clock/ath79-clk.h>
#include "ath79.dtsi"

/ {
	compatible = "qca,ar7100";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "mips,mips24Kc";
			clocks = <&pll ATH79_CLK_CPU>;
			reg = <0>;
		};
	};

	ahb {
		apb {
			ddr_ctrl: memory-controller@18000000 {
				compatible = "qca,ar7100-ddr-controller";
				reg = <0x18000000 0x100>;

				#qca,ddr-wb-channel-cells = <1>;
			};

			uart: uart@18020000 {
				compatible = "ns16550a";
				reg = <0x18020000 0x20>;
				interrupts = <3>;

				clocks = <&pll ATH79_CLK_AHB>;
				clock-names = "uart";

				reg-io-width = <4>;
				reg-shift = <2>;
				no-loopback-test;

				status = "disabled";
			};

			usb_phy: usb-phy@18030000 {
				compatible = "qca,ar7100-usb-phy";
				reg = <0x18030000 0x10>;

				reset-names = "usb-phy", "usb-host", "usb-ohci-dll";
				resets = <&rst 4>, <&rst 5>, <&rst 6>;

				#phy-cells = <0>;

				status = "disabled";
			};

			gpio: gpio@18040000 {
				compatible = "qca,ar7100-gpio";
				reg = <0x18040000 0x30>;
				interrupts = <2>;

				ngpios = <16>;

				gpio-controller;
				#gpio-cells = <2>;

				interrupt-controller;
				#interrupt-cells = <2>;
			};

			pll: pll-controller@18050000 {
				compatible = "qca,ar7100-pll", "syscon";
				reg = <0x18050000 0x20>;

				clock-names = "ref";
				/* The board must provides the ref clock */

				#clock-cells = <1>;
				clock-output-names = "cpu", "ddr", "ahb";
			};

			wdt: wdt@18060008 {
				compatible = "qca,ar7130-wdt";
				reg = <0x18060008 0x8>;

				interrupts = <4>;

				clocks = <&pll ATH79_CLK_AHB>;
				clock-names = "wdt";
			};


			rst: reset-controller@18060024 {
				compatible = "qca,ar7100-reset";
				reg = <0x18060024 0x4>;

				#reset-cells = <1>;
			};

			pcie0: pcie-controller@180c0000 {
				compatible = "qca,ar7100-pci";
				#address-cells = <3>;
				#size-cells = <2>;
				bus-range = <0x0 0x0>;
				reg = <0x17010000 0x100>;
				reg-names = "cfg_base";
				ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000	/* pci memory */
					  0x1000000 0 0x00000000 0x0000000 0 0x000001>;		/* io space */
				interrupt-parent = <&cpuintc>;
				interrupts = <2>;

				interrupt-controller;
				#interrupt-cells = <1>;

				interrupt-map-mask = <0 0 0 1>;
				interrupt-map = <0 0 0 0 &pcie0 0>;
				status = "disabled";
			};
		};
	};

	usb2: usb@1b000000 {
		compatible = "generic-ehci";
		reg = <0x1b000000 0x1000>;

		interrupt-parent = <&cpuintc>;
		interrupts = <3>;

		phy-names = "usb-phy";
		phys = <&usb_phy>;

		has-synopsys-hc-bug;

		status = "disabled";
	};

	usb1: usb@1c000000 {
		compatible = "generic-ohci";
		reg = <0x1c000000 0x1000>;

		interrupt-parent = <&miscintc>;
		interrupts = <6>;

		phy-names = "usb-phy";
		phys = <&usb_phy>;

		status = "disabled";
	};

	spi: spi@1f000000 {
		compatible = "qca,ar7100-spi";
		reg = <0x1f000000 0x10>;

		clocks = <&pll ATH79_CLK_AHB>;
		clock-names = "ahb";

		#address-cells = <1>;
		#size-cells = <0>;

		status = "disabled";
	};
};

&cpuintc {
	qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
	qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
				<&ddr_ctrl 0>, <&ddr_ctrl 1>;
};

&miscintc {
	compatible = "qca,ar7100-misc-intc";
};

&eth0 {
	compatible = "qca,ar7100-eth";
	reg = <0x19000000 0x200
		0x18070000 0x4>;

	pll-data = <0x00110000 0x00001099 0x00991099>;
	pll-reg = <0x4 0x10 17>;
	pll-handle = <&pll>;
	phy-mode = "rgmii";

	resets = <&rst 8>, <&rst 9>;
	reset-names = "phy", "mac";
};

&mdio1 {
	builtin-switch;
};

&eth1 {
	compatible = "qca,ar7100-eth";
	reg = <0x1a000000 0x200
		0x18070004 0x4>;

	pll-data = <0x00110000 0x00001099 0x00991099>;
	pll-reg = <0x4 0x14 19>;
	pll-handle = <&pll>;

	phy-mode = "rgmii";

	resets = <&rst 12>, <&rst 13>;
	reset-names = "phy", "mac";
};