650-rt2x00-add-support-for-external-PA-on-MT7620.patch 4.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118
  1. From 9782a7f7488443568fa4d6088b73c9aff7eb8510 Mon Sep 17 00:00:00 2001
  2. From: Daniel Golle <[email protected]>
  3. Date: Wed, 19 Apr 2017 16:14:53 +0200
  4. Subject: [PATCH] rt2x00: add support for external PA on MT7620
  5. To: Stanislaw Gruszka <[email protected]>
  6. Cc: Helmut Schaa <[email protected]>,
  7. [email protected],
  8. Kalle Valo <[email protected]>
  9. Signed-off-by: Daniel Golle <[email protected]>
  10. ---
  11. drivers/net/wireless/ralink/rt2x00/rt2800.h | 1 +
  12. drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 70 +++++++++++++++++++++++++-
  13. 2 files changed, 70 insertions(+), 1 deletion(-)
  14. --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
  15. +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
  16. @@ -2750,6 +2750,7 @@ enum rt2800_eeprom_word {
  17. #define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f)
  18. #define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0)
  19. #define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600)
  20. +#define EEPROM_NIC_CONF2_EXTERNAL_PA FIELD16(0xc000)
  21. /*
  22. * EEPROM LNA
  23. --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  24. +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  25. @@ -4123,6 +4123,61 @@ static void rt2800_config_channel(struct
  26. rt2800_iq_calibrate(rt2x00dev, rf->channel);
  27. }
  28. + if (rt2x00_rt(rt2x00dev, RT6352)) {
  29. + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0,
  30. + &rt2x00dev->cap_flags)) {
  31. + rt2x00_warn(rt2x00dev, "Using incomplete support for " \
  32. + "external PA\n");
  33. + reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
  34. + reg |= 0x00000101;
  35. + rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
  36. +
  37. + reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
  38. + reg |= 0x00000101;
  39. + rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
  40. +
  41. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 43, 0x73);
  42. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 43, 0x73);
  43. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 44, 0x73);
  44. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 44, 0x73);
  45. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 45, 0x73);
  46. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0x73);
  47. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 46, 0x27);
  48. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 46, 0x27);
  49. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0xC8);
  50. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0xC8);
  51. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 48, 0xA4);
  52. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 48, 0xA4);
  53. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 49, 0x05);
  54. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 49, 0x05);
  55. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
  56. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x27);
  57. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 55, 0xC8);
  58. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 55, 0xC8);
  59. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 56, 0xA4);
  60. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 56, 0xA4);
  61. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 57, 0x05);
  62. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 57, 0x05);
  63. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 58, 0x27);
  64. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 58, 0x27);
  65. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 59, 0xC8);
  66. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 59, 0xC8);
  67. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 60, 0xA4);
  68. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 60, 0xA4);
  69. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 61, 0x05);
  70. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 61, 0x05);
  71. + rt2800_rfcsr_write_bank(rt2x00dev, 5, 05, 0x00);
  72. + rt2800_rfcsr_write_bank(rt2x00dev, 7, 05, 0x00);
  73. +
  74. + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
  75. + 0x36303636);
  76. + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
  77. + 0x6C6C6B6C);
  78. + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
  79. + 0x6C6C6B6C);
  80. + }
  81. + }
  82. +
  83. bbp = rt2800_bbp_read(rt2x00dev, 4);
  84. rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
  85. rt2800_bbp_write(rt2x00dev, 4, bbp);
  86. @@ -9320,7 +9375,8 @@ static int rt2800_init_eeprom(struct rt2
  87. */
  88. eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
  89. - if (rt2x00_rt(rt2x00dev, RT3352)) {
  90. + if (rt2x00_rt(rt2x00dev, RT3352) ||
  91. + rt2x00_rt(rt2x00dev, RT6352)) {
  92. if (rt2x00_get_field16(eeprom,
  93. EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
  94. __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
  95. @@ -9331,6 +9387,18 @@ static int rt2800_init_eeprom(struct rt2
  96. &rt2x00dev->cap_flags);
  97. }
  98. + eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF2);
  99. +
  100. + if (rt2x00_rt(rt2x00dev, RT6352) && eeprom != 0 && eeprom != 0xffff) {
  101. + if (rt2x00_get_field16(eeprom,
  102. + EEPROM_NIC_CONF2_EXTERNAL_PA)) {
  103. + __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
  104. + &rt2x00dev->cap_flags);
  105. + __set_bit(CAPABILITY_EXTERNAL_PA_TX1,
  106. + &rt2x00dev->cap_flags);
  107. + }
  108. + }
  109. +
  110. return 0;
  111. }