mt7628an.dtsi 5.6 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "ralink,mtk7628an-soc";
  5. cpus {
  6. cpu@0 {
  7. compatible = "mips,mips24KEc";
  8. };
  9. };
  10. chosen {
  11. bootargs = "console=ttyS0,57600";
  12. };
  13. cpuintc: cpuintc@0 {
  14. #address-cells = <0>;
  15. #interrupt-cells = <1>;
  16. interrupt-controller;
  17. compatible = "mti,cpu-interrupt-controller";
  18. };
  19. palmbus@10000000 {
  20. compatible = "palmbus";
  21. reg = <0x10000000 0x200000>;
  22. ranges = <0x0 0x10000000 0x1FFFFF>;
  23. #address-cells = <1>;
  24. #size-cells = <1>;
  25. sysc@0 {
  26. compatible = "ralink,mt7620a-sysc";
  27. reg = <0x0 0x100>;
  28. };
  29. watchdog@120 {
  30. compatible = "ralink,mt7628an-wdt", "mtk,mt7621-wdt";
  31. reg = <0x120 0x10>;
  32. resets = <&rstctrl 8>;
  33. reset-names = "wdt";
  34. interrupt-parent = <&intc>;
  35. interrupts = <24>;
  36. };
  37. intc: intc@200 {
  38. compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
  39. reg = <0x200 0x100>;
  40. resets = <&rstctrl 9>;
  41. reset-names = "intc";
  42. interrupt-controller;
  43. #interrupt-cells = <1>;
  44. interrupt-parent = <&cpuintc>;
  45. interrupts = <2>;
  46. ralink,intc-registers = <0x9c 0xa0
  47. 0x6c 0xa4
  48. 0x80 0x78>;
  49. };
  50. memc@300 {
  51. compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
  52. reg = <0x300 0x100>;
  53. resets = <&rstctrl 20>;
  54. reset-names = "mc";
  55. interrupt-parent = <&intc>;
  56. interrupts = <3>;
  57. };
  58. gpio@600 {
  59. #address-cells = <1>;
  60. #size-cells = <0>;
  61. compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
  62. reg = <0x600 0x100>;
  63. interrupt-parent = <&intc>;
  64. interrupts = <6>;
  65. gpio0: bank@0 {
  66. reg = <0>;
  67. compatible = "mtk,mt7621-gpio-bank";
  68. gpio-controller;
  69. #gpio-cells = <2>;
  70. };
  71. gpio1: bank@1 {
  72. reg = <1>;
  73. compatible = "mtk,mt7621-gpio-bank";
  74. gpio-controller;
  75. #gpio-cells = <2>;
  76. };
  77. gpio2: bank@2 {
  78. reg = <2>;
  79. compatible = "mtk,mt7621-gpio-bank";
  80. gpio-controller;
  81. #gpio-cells = <2>;
  82. };
  83. };
  84. spi@b00 {
  85. compatible = "ralink,mt7621-spi";
  86. reg = <0xb00 0x100>;
  87. resets = <&rstctrl 18>;
  88. reset-names = "spi";
  89. #address-cells = <1>;
  90. #size-cells = <1>;
  91. pinctrl-names = "default";
  92. pinctrl-0 = <&spi_pins>;
  93. status = "disabled";
  94. };
  95. uartlite@c00 {
  96. compatible = "ns16550a";
  97. reg = <0xc00 0x100>;
  98. reg-shift = <2>;
  99. reg-io-width = <4>;
  100. no-loopback-test;
  101. resets = <&rstctrl 12>;
  102. reset-names = "uartl";
  103. interrupt-parent = <&intc>;
  104. interrupts = <20>;
  105. pinctrl-names = "default";
  106. pinctrl-0 = <&uart0_pins>;
  107. };
  108. uart1@d00 {
  109. compatible = "ns16550a";
  110. reg = <0xd00 0x100>;
  111. reg-shift = <2>;
  112. reg-io-width = <4>;
  113. no-loopback-test;
  114. resets = <&rstctrl 19>;
  115. reset-names = "uart1";
  116. interrupt-parent = <&intc>;
  117. interrupts = <21>;
  118. pinctrl-names = "default";
  119. pinctrl-0 = <&uart1_pins>;
  120. status = "disabled";
  121. };
  122. uart2@e00 {
  123. compatible = "ns16550a";
  124. reg = <0xe00 0x100>;
  125. reg-shift = <2>;
  126. reg-io-width = <4>;
  127. no-loopback-test;
  128. resets = <&rstctrl 20>;
  129. reset-names = "uart2";
  130. interrupt-parent = <&intc>;
  131. interrupts = <22>;
  132. pinctrl-names = "default";
  133. pinctrl-0 = <&uart2_pins>;
  134. status = "disabled";
  135. };
  136. };
  137. pinctrl {
  138. compatible = "ralink,rt2880-pinmux";
  139. pinctrl-names = "default";
  140. pinctrl-0 = <&state_default>;
  141. state_default: pinctrl0 {
  142. };
  143. spi_pins: spi {
  144. spi {
  145. ralink,group = "spi";
  146. ralink,function = "spi";
  147. };
  148. };
  149. uart0_pins: uartlite {
  150. uartlite {
  151. ralink,group = "uart0";
  152. ralink,function = "uart0";
  153. };
  154. };
  155. uart1_pins: uart1 {
  156. uart1 {
  157. ralink,group = "uart1";
  158. ralink,function = "uart1";
  159. };
  160. };
  161. uart2_pins: uart2 {
  162. uart2 {
  163. ralink,group = "uart2";
  164. ralink,function = "uart2";
  165. };
  166. };
  167. sdxc_pins: sdxc {
  168. sdxc {
  169. ralink,group = "sdmode";
  170. ralink,function = "sdxc";
  171. };
  172. };
  173. };
  174. rstctrl: rstctrl {
  175. compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
  176. #reset-cells = <1>;
  177. };
  178. usbphy: usbphy {
  179. compatible = "ralink,mt7628an-usbphy", "ralink,mt7620a-usbphy";
  180. #phy-cells = <1>;
  181. resets = <&rstctrl 22>;
  182. reset-names = "host";
  183. };
  184. sdhci@10130000 {
  185. compatible = "ralink,mt7620-sdhci";
  186. reg = <0x10130000 4000>;
  187. interrupt-parent = <&intc>;
  188. interrupts = <14>;
  189. pinctrl-names = "default";
  190. pinctrl-0 = <&sdxc_pins>;
  191. status = "disabled";
  192. };
  193. ehci@101c0000 {
  194. compatible = "ralink,rt3xxx-ehci";
  195. reg = <0x101c0000 0x1000>;
  196. phys = <&usbphy 1>;
  197. phy-names = "usb";
  198. interrupt-parent = <&intc>;
  199. interrupts = <18>;
  200. };
  201. ohci@101c1000 {
  202. compatible = "ralink,rt3xxx-ohci";
  203. reg = <0x101c1000 0x1000>;
  204. phys = <&usbphy 1>;
  205. phy-names = "usb";
  206. interrupt-parent = <&intc>;
  207. interrupts = <18>;
  208. };
  209. ethernet@10100000 {
  210. compatible = "ralink,rt5350-eth";
  211. reg = <0x10100000 10000>;
  212. interrupt-parent = <&cpuintc>;
  213. interrupts = <5>;
  214. resets = <&rstctrl 21 &rstctrl 23>;
  215. reset-names = "fe", "esw";
  216. };
  217. esw@10110000 {
  218. compatible = "ralink,rt3050-esw";
  219. reg = <0x10110000 8000>;
  220. resets = <&rstctrl 23>;
  221. reset-names = "esw";
  222. interrupt-parent = <&intc>;
  223. interrupts = <17>;
  224. };
  225. pcie@10140000 {
  226. compatible = "mediatek,mt7620-pci";
  227. reg = <0x10140000 0x100
  228. 0x10142000 0x100>;
  229. #address-cells = <3>;
  230. #size-cells = <2>;
  231. resets = <&rstctrl 26>;
  232. reset-names = "pcie0";
  233. interrupt-parent = <&cpuintc>;
  234. interrupts = <4>;
  235. status = "disabled";
  236. device_type = "pci";
  237. bus-range = <0 255>;
  238. ranges = <
  239. 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
  240. 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
  241. >;
  242. pcie-bridge {
  243. reg = <0x0000 0 0 0 0>;
  244. #address-cells = <3>;
  245. #size-cells = <2>;
  246. device_type = "pci";
  247. };
  248. };
  249. };