389-MIPS-BCM63XX-add-clkdev-lookups-for-device-tree.patch 4.7 KB

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  1. From cad8f63047c0691e8185d3c9c6a2705b83310c9c Mon Sep 17 00:00:00 2001
  2. From: Jonas Gorski <[email protected]>
  3. Date: Mon, 31 Jul 2017 20:10:36 +0200
  4. Subject: [PATCH] MIPS: BCM63XX: add clkdev lookups for device tree
  5. ---
  6. arch/mips/bcm63xx/clk.c | 15 +++++++++++++++
  7. 1 file changed, 15 insertions(+)
  8. --- a/arch/mips/bcm63xx/clk.c
  9. +++ b/arch/mips/bcm63xx/clk.c
  10. @@ -488,6 +488,8 @@ static struct clk_lookup bcm3368_clks[]
  11. CLKDEV_INIT(NULL, "periph", &clk_periph),
  12. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  13. CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
  14. + CLKDEV_INIT("fff8c100.serial", "refclk", &clk_periph),
  15. + CLKDEV_INIT("fff8c120.serial", "refclk", &clk_periph),
  16. /* gated clocks */
  17. CLKDEV_INIT(NULL, "enet0", &clk_enet0),
  18. CLKDEV_INIT(NULL, "enet1", &clk_enet1),
  19. @@ -504,7 +506,9 @@ static struct clk_lookup bcm6318_clks[]
  20. /* fixed rate clocks */
  21. CLKDEV_INIT(NULL, "periph", &clk_periph),
  22. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  23. + CLKDEV_INIT("10000100.serial", "refclk", &clk_periph),
  24. CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
  25. + CLKDEV_INIT("10003000.spi", "pll", &clk_hsspi_pll),
  26. /* gated clocks */
  27. CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
  28. CLKDEV_INIT(NULL, "usbh", &clk_usbh),
  29. @@ -518,7 +522,10 @@ static struct clk_lookup bcm6328_clks[]
  30. CLKDEV_INIT(NULL, "periph", &clk_periph),
  31. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  32. CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
  33. + CLKDEV_INIT("10000100.serial", "refclk", &clk_periph),
  34. + CLKDEV_INIT("10000120.serial", "refclk", &clk_periph),
  35. CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
  36. + CLKDEV_INIT("10001000.spi", "pll", &clk_hsspi_pll),
  37. /* gated clocks */
  38. CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
  39. CLKDEV_INIT(NULL, "usbh", &clk_usbh),
  40. @@ -531,6 +538,7 @@ static struct clk_lookup bcm6338_clks[]
  41. /* fixed rate clocks */
  42. CLKDEV_INIT(NULL, "periph", &clk_periph),
  43. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  44. + CLKDEV_INIT("fffe0300.serial", "refclk", &clk_periph),
  45. /* gated clocks */
  46. CLKDEV_INIT(NULL, "enet0", &clk_enet0),
  47. CLKDEV_INIT(NULL, "enet1", &clk_enet1),
  48. @@ -545,6 +553,7 @@ static struct clk_lookup bcm6345_clks[]
  49. /* fixed rate clocks */
  50. CLKDEV_INIT(NULL, "periph", &clk_periph),
  51. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  52. + CLKDEV_INIT("fffe0300.serial", "refclk", &clk_periph),
  53. /* gated clocks */
  54. CLKDEV_INIT(NULL, "enet0", &clk_enet0),
  55. CLKDEV_INIT(NULL, "enet1", &clk_enet1),
  56. @@ -559,6 +568,7 @@ static struct clk_lookup bcm6348_clks[]
  57. /* fixed rate clocks */
  58. CLKDEV_INIT(NULL, "periph", &clk_periph),
  59. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  60. + CLKDEV_INIT("fffe0300.serial", "refclk", &clk_periph),
  61. /* gated clocks */
  62. CLKDEV_INIT(NULL, "enet0", &clk_enet0),
  63. CLKDEV_INIT(NULL, "enet1", &clk_enet1),
  64. @@ -575,6 +585,8 @@ static struct clk_lookup bcm6358_clks[]
  65. CLKDEV_INIT(NULL, "periph", &clk_periph),
  66. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  67. CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
  68. + CLKDEV_INIT("fffe0100.serial", "refclk", &clk_periph),
  69. + CLKDEV_INIT("fffe0120.serial", "refclk", &clk_periph),
  70. /* gated clocks */
  71. CLKDEV_INIT(NULL, "enet0", &clk_enet0),
  72. CLKDEV_INIT(NULL, "enet1", &clk_enet1),
  73. @@ -594,7 +606,10 @@ static struct clk_lookup bcm6362_clks[]
  74. CLKDEV_INIT(NULL, "periph", &clk_periph),
  75. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  76. CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
  77. + CLKDEV_INIT("10000100.serial", "refclk", &clk_periph),
  78. + CLKDEV_INIT("10000120.serial", "refclk", &clk_periph),
  79. CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
  80. + CLKDEV_INIT("10001000.spi", "pll", &clk_hsspi_pll),
  81. /* gated clocks */
  82. CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
  83. CLKDEV_INIT(NULL, "usbh", &clk_usbh),
  84. @@ -610,6 +625,8 @@ static struct clk_lookup bcm6368_clks[]
  85. CLKDEV_INIT(NULL, "periph", &clk_periph),
  86. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  87. CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
  88. + CLKDEV_INIT("10000100.serial", "refclk", &clk_periph),
  89. + CLKDEV_INIT("10000120.serial", "refclk", &clk_periph),
  90. /* gated clocks */
  91. CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
  92. CLKDEV_INIT(NULL, "usbh", &clk_usbh),
  93. @@ -624,7 +641,10 @@ static struct clk_lookup bcm63268_clks[]
  94. CLKDEV_INIT(NULL, "periph", &clk_periph),
  95. CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
  96. CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
  97. + CLKDEV_INIT("10000180.serial", "refclk", &clk_periph),
  98. + CLKDEV_INIT("100001a0.serial", "refclk", &clk_periph),
  99. CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
  100. + CLKDEV_INIT("10001000.spi", "pll", &clk_hsspi_pll),
  101. /* gated clocks */
  102. CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
  103. CLKDEV_INIT(NULL, "usbh", &clk_usbh),