0113-remoteproc-qcom-Add-secure-PIL-support.patch 4.1 KB

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  1. From 7358d42dfbdfdb5d4f1d0d4c2e5c2bb4143a29b0 Mon Sep 17 00:00:00 2001
  2. From: Gokul Sriram Palanisamy <[email protected]>
  3. Date: Sat, 30 Jan 2021 10:50:06 +0530
  4. Subject: [PATCH] remoteproc: qcom: Add secure PIL support
  5. IPQ8074 uses secure PIL. Hence, adding the support for the same.
  6. Signed-off-by: Gokul Sriram Palanisamy <[email protected]>
  7. Signed-off-by: Sricharan R <[email protected]>
  8. Signed-off-by: Nikhil Prakash V <[email protected]>
  9. ---
  10. drivers/remoteproc/qcom_q6v5_wcss.c | 43 +++++++++++++++++++++++++++--
  11. 1 file changed, 40 insertions(+), 3 deletions(-)
  12. --- a/drivers/remoteproc/qcom_q6v5_wcss.c
  13. +++ b/drivers/remoteproc/qcom_q6v5_wcss.c
  14. @@ -18,6 +18,7 @@
  15. #include <linux/regulator/consumer.h>
  16. #include <linux/reset.h>
  17. #include <linux/soc/qcom/mdt_loader.h>
  18. +#include <linux/firmware/qcom/qcom_scm.h>
  19. #include "qcom_common.h"
  20. #include "qcom_pil_info.h"
  21. #include "qcom_q6v5.h"
  22. @@ -86,6 +87,9 @@
  23. #define TCSR_WCSS_CLK_ENABLE 0x14
  24. #define MAX_HALT_REG 3
  25. +
  26. +#define WCNSS_PAS_ID 6
  27. +
  28. enum {
  29. WCSS_IPQ8074,
  30. WCSS_QCS404,
  31. @@ -134,6 +138,7 @@ struct q6v5_wcss {
  32. unsigned int crash_reason_smem;
  33. u32 version;
  34. bool requires_force_stop;
  35. + bool need_mem_protection;
  36. struct qcom_rproc_glink glink_subdev;
  37. struct qcom_rproc_ssr ssr_subdev;
  38. @@ -152,6 +157,7 @@ struct wcss_data {
  39. int ssctl_id;
  40. const struct rproc_ops *ops;
  41. bool requires_force_stop;
  42. + bool need_mem_protection;
  43. };
  44. static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
  45. @@ -251,6 +257,15 @@ static int q6v5_wcss_start(struct rproc
  46. qcom_q6v5_prepare(&wcss->q6v5);
  47. + if (wcss->need_mem_protection) {
  48. + ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
  49. + if (ret) {
  50. + dev_err(wcss->dev, "wcss_reset failed\n");
  51. + return ret;
  52. + }
  53. + goto wait_for_reset;
  54. + }
  55. +
  56. /* Release Q6 and WCSS reset */
  57. ret = reset_control_deassert(wcss->wcss_reset);
  58. if (ret) {
  59. @@ -285,6 +300,7 @@ static int q6v5_wcss_start(struct rproc
  60. if (ret)
  61. goto wcss_q6_reset;
  62. +wait_for_reset:
  63. ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
  64. if (ret == -ETIMEDOUT)
  65. dev_err(wcss->dev, "start timed out\n");
  66. @@ -718,6 +734,15 @@ static int q6v5_wcss_stop(struct rproc *
  67. struct q6v5_wcss *wcss = rproc->priv;
  68. int ret;
  69. + if (wcss->need_mem_protection) {
  70. + ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
  71. + if (ret) {
  72. + dev_err(wcss->dev, "not able to shutdown\n");
  73. + return ret;
  74. + }
  75. + goto pas_done;
  76. + }
  77. +
  78. /* WCSS powerdown */
  79. if (wcss->requires_force_stop) {
  80. ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL);
  81. @@ -742,6 +767,7 @@ static int q6v5_wcss_stop(struct rproc *
  82. return ret;
  83. }
  84. +pas_done:
  85. clk_disable_unprepare(wcss->prng_clk);
  86. qcom_q6v5_unprepare(&wcss->q6v5);
  87. @@ -765,9 +791,15 @@ static int q6v5_wcss_load(struct rproc *
  88. struct q6v5_wcss *wcss = rproc->priv;
  89. int ret;
  90. - ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
  91. - 0, wcss->mem_region, wcss->mem_phys,
  92. - wcss->mem_size, &wcss->mem_reloc);
  93. + if (wcss->need_mem_protection)
  94. + ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
  95. + WCNSS_PAS_ID, wcss->mem_region,
  96. + wcss->mem_phys, wcss->mem_size,
  97. + &wcss->mem_reloc);
  98. + else
  99. + ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
  100. + 0, wcss->mem_region, wcss->mem_phys,
  101. + wcss->mem_size, &wcss->mem_reloc);
  102. if (ret)
  103. return ret;
  104. @@ -1035,6 +1067,9 @@ static int q6v5_wcss_probe(struct platfo
  105. if (!desc)
  106. return -EINVAL;
  107. + if (desc->need_mem_protection && !qcom_scm_is_available())
  108. + return -EPROBE_DEFER;
  109. +
  110. rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
  111. desc->firmware_name, sizeof(*wcss));
  112. if (!rproc) {
  113. @@ -1048,6 +1083,7 @@ static int q6v5_wcss_probe(struct platfo
  114. wcss->version = desc->version;
  115. wcss->requires_force_stop = desc->requires_force_stop;
  116. + wcss->need_mem_protection = desc->need_mem_protection;
  117. ret = q6v5_wcss_init_mmio(wcss, pdev);
  118. if (ret)
  119. @@ -1117,6 +1153,7 @@ static const struct wcss_data wcss_ipq80
  120. .wcss_q6_reset_required = true,
  121. .ops = &q6v5_wcss_ipq8074_ops,
  122. .requires_force_stop = true,
  123. + .need_mem_protection = true,
  124. };
  125. static const struct wcss_data wcss_qcs404_res_init = {