WR1200JS.dts 2.2 KB

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  1. /dts-v1/;
  2. #include "mt7621.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. / {
  6. compatible = "youhua,wr1200js", "mediatek,mt7621-soc";
  7. model = "YouHua WR1200JS";
  8. aliases {
  9. led-status = &led_wps;
  10. };
  11. memory@0 {
  12. device_type = "memory";
  13. reg = <0x0 0x8000000>;
  14. };
  15. chosen {
  16. bootargs = "console=ttyS0,115200";
  17. };
  18. gpio-leds {
  19. compatible = "gpio-leds";
  20. internet {
  21. label = "wr1200js:blue:internet";
  22. gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
  23. };
  24. led_wps: wps {
  25. label = "wr1200js:blue:wps";
  26. gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
  27. };
  28. usb {
  29. label = "wr1200js:blue:usb";
  30. gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
  31. };
  32. };
  33. gpio-keys-polled {
  34. compatible = "gpio-keys-polled";
  35. poll-interval = <20>;
  36. reset {
  37. label = "reset";
  38. gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
  39. linux,code = <KEY_RESTART>;
  40. };
  41. wps {
  42. label = "wps";
  43. gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
  44. linux,code = <KEY_WPS_BUTTON>;
  45. };
  46. wifi {
  47. label = "wifi";
  48. gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
  49. linux,code = <KEY_RFKILL>;
  50. };
  51. };
  52. };
  53. &spi0 {
  54. status = "okay";
  55. m25p80@0 {
  56. compatible = "jedec,spi-nor";
  57. reg = <0>;
  58. spi-max-frequency = <10000000>;
  59. m25p,chunked-io = <32>;
  60. partitions {
  61. compatible = "fixed-partitions";
  62. #address-cells = <1>;
  63. #size-cells = <1>;
  64. partition@0 {
  65. label = "u-boot";
  66. reg = <0x0 0x30000>;
  67. read-only;
  68. };
  69. partition@30000 {
  70. label = "u-boot-env";
  71. reg = <0x30000 0x10000>;
  72. read-only;
  73. };
  74. factory: partition@40000 {
  75. label = "factory";
  76. reg = <0x40000 0x10000>;
  77. read-only;
  78. };
  79. partition@50000 {
  80. label = "firmware";
  81. reg = <0x50000 0xfb0000>;
  82. };
  83. };
  84. };
  85. };
  86. &pcie {
  87. status = "okay";
  88. };
  89. &pcie0 {
  90. mt76@0,0 {
  91. reg = <0x0000 0 0 0 0>;
  92. mediatek,mtd-eeprom = <&factory 0x0000>;
  93. };
  94. };
  95. &pcie1 {
  96. mt76@0,0 {
  97. reg = <0x0000 0 0 0 0>;
  98. mediatek,mtd-eeprom = <&factory 0x8000>;
  99. ieee80211-freq-limit = <5000000 6000000>;
  100. led {
  101. led-sources = <2>;
  102. led-active-low;
  103. };
  104. };
  105. };
  106. &ethernet {
  107. mtd-mac-address = <&factory 0xe000>;
  108. };
  109. &pinctrl {
  110. state_default: pinctrl0 {
  111. gpio {
  112. ralink,group = "i2c", "uart2", "uart3", "wdt";
  113. ralink,function = "gpio";
  114. };
  115. };
  116. };