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- From 77b0e8ded57e7fb5d742fb533d7a9bb3f3788513 Mon Sep 17 00:00:00 2001
- From: Maxime Ripard <[email protected]>
- Date: Wed, 13 Jan 2021 11:20:08 +0100
- Subject: [PATCH] drm/vc4: hdmi: Replace CSC_CTL hardcoded value by
- defines
- On BCM2711, the HDMI_CSC_CTL register value has been hardcoded to an
- opaque value. Let's replace it with properly defined values.
- Acked-by: Thomas Zimmermann <[email protected]>
- Signed-off-by: Maxime Ripard <[email protected]>
- ---
- drivers/gpu/drm/vc4/vc4_hdmi.c | 5 ++---
- drivers/gpu/drm/vc4/vc4_regs.h | 3 +++
- 2 files changed, 5 insertions(+), 3 deletions(-)
- --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
- +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
- @@ -786,9 +786,8 @@ static void vc5_hdmi_csc_setup(struct vc
- const struct drm_display_mode *mode)
- {
- unsigned long flags;
- - u32 csc_ctl;
- -
- - csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
- + u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
- + VC5_MT_CP_CSC_CTL_MODE);
-
- spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
-
- --- a/drivers/gpu/drm/vc4/vc4_regs.h
- +++ b/drivers/gpu/drm/vc4/vc4_regs.h
- @@ -810,6 +810,9 @@ enum {
- # define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
- # define VC4_HD_CSC_CTL_ENABLE BIT(0)
-
- +# define VC5_MT_CP_CSC_CTL_ENABLE BIT(2)
- +# define VC5_MT_CP_CSC_CTL_MODE_MASK VC4_MASK(1, 0)
- +
- # define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1)
-
- /* HVS display list information. */
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