950-0790-vc4-drm-plane-Make-use-of-chroma-siting-parameter.patch 2.4 KB

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  1. From bb6fb3a029e8d745640aedce2ee57fc3fee73ea9 Mon Sep 17 00:00:00 2001
  2. From: Dom Cobley <[email protected]>
  3. Date: Thu, 27 Jan 2022 15:32:04 +0000
  4. Subject: [PATCH] vc4/drm:plane: Make use of chroma siting parameter
  5. Signed-off-by: Dom Cobley <[email protected]>
  6. ---
  7. drivers/gpu/drm/vc4/vc4_plane.c | 13 +++++++++----
  8. 1 file changed, 9 insertions(+), 4 deletions(-)
  9. --- a/drivers/gpu/drm/vc4/vc4_plane.c
  10. +++ b/drivers/gpu/drm/vc4/vc4_plane.c
  11. @@ -463,17 +463,18 @@ static void vc4_write_tpz(struct vc4_pla
  12. /* phase magnitude bits */
  13. #define PHASE_BITS 6
  14. -static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst, u32 xy, int channel)
  15. +static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst, u32 xy, int channel, int chroma_offset)
  16. {
  17. u32 scale = src / dst;
  18. s32 offset, offset2;
  19. s32 phase;
  20. /* Start the phase at 1/2 pixel from the 1st pixel at src_x.
  21. - 1/4 pixel for YUV. */
  22. + 1/4 pixel for YUV, plus the offset for chroma siting */
  23. if (channel) {
  24. /* the phase is relative to scale_src->x, so shift it for display list's x value */
  25. offset = (xy & 0x1ffff) >> (16 - PHASE_BITS) >> 1;
  26. + offset -= chroma_offset >> (17 - PHASE_BITS);
  27. offset += -(1 << PHASE_BITS >> 2);
  28. } else {
  29. /* the phase is relative to scale_src->x, so shift it for display list's x value */
  30. @@ -559,13 +560,15 @@ static void vc4_write_scaling_parameters
  31. /* Ch0 H-PPF Word 0: Scaling Parameters */
  32. if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
  33. vc4_write_ppf(vc4_state,
  34. - vc4_state->src_w[channel], vc4_state->crtc_w, vc4_state->src_x, channel);
  35. + vc4_state->src_w[channel], vc4_state->crtc_w, vc4_state->src_x, channel,
  36. + state->chroma_siting_h);
  37. }
  38. /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
  39. if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
  40. vc4_write_ppf(vc4_state,
  41. - vc4_state->src_h[channel], vc4_state->crtc_h, vc4_state->src_y, channel);
  42. + vc4_state->src_h[channel], vc4_state->crtc_h, vc4_state->src_y, channel,
  43. + state->chroma_siting_v);
  44. vc4_dlist_write(vc4_state, 0xc0c0c0c0);
  45. }
  46. @@ -1624,6 +1627,8 @@ struct drm_plane *vc4_plane_init(struct
  47. DRM_COLOR_YCBCR_BT709,
  48. DRM_COLOR_YCBCR_LIMITED_RANGE);
  49. + drm_plane_create_chroma_siting_properties(plane, 0, 0);
  50. +
  51. if (type == DRM_PLANE_TYPE_PRIMARY)
  52. drm_plane_create_zpos_immutable_property(plane, 0);