qcom-ipq8064-fap-421e.dts 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq8064-smb208.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/leds/common.h>
  5. / {
  6. model = "Fortinet FAP-421E";
  7. compatible = "fortinet,fap-421e", "qcom,ipq8064";
  8. memory@42000000 {
  9. device_type = "memory";
  10. reg = <0x42000000 0xe000000>;
  11. };
  12. reserved-memory {
  13. rsvd@41200000 {
  14. no-map;
  15. reg = <0x41200000 0x300000>;
  16. };
  17. wifi_dump@44000000 {
  18. no-map;
  19. reg = <0x44000000 0x600000>;
  20. };
  21. };
  22. aliases {
  23. led-boot = &led_power_yellow;
  24. led-failsafe = &led_power_yellow;
  25. led-running = &led_power_yellow;
  26. led-upgrade = &led_power_yellow;
  27. label-mac-device = &gmac0;
  28. };
  29. chosen {
  30. bootargs-override = "console=ttyMSM0,9600n8";
  31. };
  32. keys {
  33. compatible = "gpio-keys";
  34. pinctrl-0 = <&button_pins>;
  35. pinctrl-names = "default";
  36. reset {
  37. label = "reset";
  38. gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>;
  39. linux,code = <KEY_RESTART>;
  40. };
  41. };
  42. leds {
  43. compatible = "gpio-leds";
  44. pinctrl-0 = <&led_pins>;
  45. pinctrl-names = "default";
  46. eth1-amber {
  47. label = "amber:eth1";
  48. gpios = <&qcom_pinmux 27 GPIO_ACTIVE_LOW>;
  49. };
  50. eth1-yellow {
  51. label = "yellow:eth1";
  52. gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
  53. };
  54. eth2-amber {
  55. label = "amber:eth2";
  56. gpios = <&qcom_pinmux 29 GPIO_ACTIVE_LOW>;
  57. };
  58. eth2-yellow {
  59. label = "yellow:eth2";
  60. gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>;
  61. };
  62. power-amber {
  63. function = LED_FUNCTION_POWER;
  64. color = <LED_COLOR_ID_AMBER>;
  65. gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;
  66. };
  67. led_power_yellow: power-yellow {
  68. function = LED_FUNCTION_POWER;
  69. color = <LED_COLOR_ID_YELLOW>;
  70. gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>;
  71. };
  72. 2g-yellow {
  73. label = "yellow:2g";
  74. gpios = <&qcom_pinmux 30 GPIO_ACTIVE_LOW>;
  75. };
  76. 5g-yellow {
  77. label = "yellow:5g";
  78. gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
  79. };
  80. };
  81. };
  82. &qcom_pinmux {
  83. button_pins: button_pins {
  84. mux {
  85. bias-pull-up;
  86. drive-strength = <2>;
  87. pins = "gpio56";
  88. };
  89. };
  90. led_pins: led_pins {
  91. mux {
  92. bias-pull-down;
  93. drive-strength = <2>;
  94. function = "gpio";
  95. output-low;
  96. pins = "gpio23";
  97. };
  98. };
  99. rgmii2_pins: rgmii2-pins {
  100. mux {
  101. bias-disable;
  102. drive-strength = <16>;
  103. function = "rgmii2";
  104. pins = "gpio66";
  105. };
  106. };
  107. spi_pins: spi_pins {
  108. mux {
  109. pins = "gpio18", "gpio19", "gpio21";
  110. function = "gsbi5";
  111. bias-pull-down;
  112. };
  113. data {
  114. pins = "gpio18", "gpio19";
  115. drive-strength = <10>;
  116. };
  117. cs {
  118. pins = "gpio20";
  119. drive-strength = <10>;
  120. bias-pull-up;
  121. };
  122. clk {
  123. pins = "gpio21";
  124. drive-strength = <12>;
  125. };
  126. };
  127. uart0_pins: uart0_pins {
  128. mux {
  129. bias-disable;
  130. drive-strength = <12>;
  131. function = "gsbi7";
  132. pins = "gpio6", "gpio7";
  133. };
  134. };
  135. usb_pwr_en_pins: usb_pwr_en_pins {
  136. mux {
  137. pins = "gpio22";
  138. function = "gpio";
  139. drive-strength = <12>;
  140. bias-pull-down;
  141. output-low;
  142. };
  143. };
  144. };
  145. &gsbi7 {
  146. qcom,mode = <GSBI_PROT_I2C_UART>;
  147. status = "okay";
  148. };
  149. &gsbi7_serial{
  150. pinctrl-0 = <&uart0_pins>;
  151. pinctrl-names = "default";
  152. status = "okay";
  153. };
  154. &gsbi5 {
  155. qcom,mode = <GSBI_PROT_SPI>;
  156. status = "okay";
  157. spi@1a280000 {
  158. status = "okay";
  159. pinctrl-0 = <&spi_pins>;
  160. pinctrl-names = "default";
  161. cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
  162. flash@0 {
  163. compatible = "jedec,spi-nor";
  164. #address-cells = <1>;
  165. #size-cells = <1>;
  166. spi-max-frequency = <50000000>;
  167. reg = <0>;
  168. m25p,fast-read;
  169. partition@0 {
  170. label = "SBL1";
  171. reg = <0x0 0x20000>;
  172. read-only;
  173. };
  174. partition@20000 {
  175. label = "MIBIB";
  176. reg = <0x20000 0x20000>;
  177. read-only;
  178. };
  179. partition@40000 {
  180. label = "SBL2";
  181. reg = <0x40000 0x40000>;
  182. read-only;
  183. };
  184. partition@80000 {
  185. label = "SBL3";
  186. reg = <0x80000 0x80000>;
  187. read-only;
  188. };
  189. partition@100000 {
  190. label = "DDRCONFIG";
  191. reg = <0x100000 0x10000>;
  192. read-only;
  193. };
  194. partition@110000 {
  195. label = "SSD";
  196. reg = <0x110000 0x10000>;
  197. read-only;
  198. };
  199. partition@120000 {
  200. label = "TZ";
  201. reg = <0x120000 0x80000>;
  202. read-only;
  203. };
  204. partition@1a0000 {
  205. label = "RPM";
  206. reg = <0x1a0000 0x80000>;
  207. read-only;
  208. };
  209. partition@220000 {
  210. label = "APPSBL";
  211. reg = <0x220000 0x80000>;
  212. read-only;
  213. nvmem-layout {
  214. compatible = "fixed-layout";
  215. #address-cells = <1>;
  216. #size-cells = <1>;
  217. macaddr_appsbl_7ff80: mac-address@7ff80 {
  218. compatible = "mac-base";
  219. reg = <0x7ff80 0xc>;
  220. #nvmem-cell-cells = <1>;
  221. };
  222. };
  223. };
  224. partition@2a0000 {
  225. label = "APPSBLENV";
  226. reg = <0x2a0000 0x40000>;
  227. };
  228. partition@2e0000 {
  229. label = "ART";
  230. reg = <0x2e0000 0x40000>;
  231. read-only;
  232. };
  233. partition@320000 {
  234. label = "kernel";
  235. reg = <0x320000 0x600000>;
  236. };
  237. partition@920000 {
  238. label = "ubi";
  239. reg = <0x920000 0x1400000>;
  240. };
  241. partition@1d20000 {
  242. label = "reserved";
  243. reg = <0x1d20000 0x260000>;
  244. read-only;
  245. };
  246. partition@1f80000 {
  247. label = "config";
  248. reg = <0x1f80000 0x80000>;
  249. read-only;
  250. };
  251. };
  252. };
  253. };
  254. &hs_phy_1 {
  255. status = "okay";
  256. };
  257. &ss_phy_1 {
  258. status = "okay";
  259. };
  260. &usb3_1 {
  261. status = "okay";
  262. pinctrl-0 = <&usb_pwr_en_pins>;
  263. pinctrl-names = "default";
  264. };
  265. &pcie0 {
  266. status = "okay";
  267. bridge@0,0 {
  268. reg = <0x00000000 0 0 0 0>;
  269. #address-cells = <3>;
  270. #size-cells = <2>;
  271. ranges;
  272. wifi@1,0 {
  273. compatible = "pci168c,0040";
  274. reg = <0x00010000 0 0 0 0>;
  275. nvmem-cells = <&macaddr_appsbl_7ff80 8>;
  276. nvmem-cell-names = "mac-address";
  277. };
  278. };
  279. };
  280. &pcie1 {
  281. status = "okay";
  282. max-link-speed = <1>;
  283. bridge@0,0 {
  284. reg = <0x00000000 0 0 0 0>;
  285. #address-cells = <3>;
  286. #size-cells = <2>;
  287. ranges;
  288. wifi@1,0 {
  289. compatible = "pci168c,0040";
  290. reg = <0x00010000 0 0 0 0>;
  291. nvmem-cells = <&macaddr_appsbl_7ff80 16>;
  292. nvmem-cell-names = "mac-address";
  293. };
  294. };
  295. };
  296. &adm_dma {
  297. status = "okay";
  298. };
  299. &mdio0 {
  300. status = "okay";
  301. #address-cells = <0x1>;
  302. #size-cells = <0x0>;
  303. gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
  304. <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
  305. pinctrl-0 = <&mdio0_pins>;
  306. pinctrl-names = "default";
  307. phy1: ethernet-phy@1 {
  308. reg = <1>;
  309. };
  310. phy2: ethernet-phy@2 {
  311. reg = <2>;
  312. };
  313. };
  314. &gmac0 {
  315. status = "okay";
  316. phy-mode = "rgmii";
  317. qcom,id = <0>;
  318. pinctrl-0 = <&rgmii2_pins>;
  319. pinctrl-names = "default";
  320. nvmem-cells = <&macaddr_appsbl_7ff80 0>;
  321. nvmem-cell-names = "mac-address";
  322. fixed-link {
  323. speed = <1000>;
  324. full-duplex;
  325. };
  326. };
  327. &gmac2 {
  328. status = "okay";
  329. phy-mode = "sgmii";
  330. qcom,id = <2>;
  331. nvmem-cells = <&macaddr_appsbl_7ff80 1>;
  332. nvmem-cell-names = "mac-address";
  333. fixed-link {
  334. speed = <1000>;
  335. full-duplex;
  336. };
  337. };