qcom-ipq8064-g10.dts 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include "qcom-ipq8064-v2.0-smb208.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/leds/common.h>
  5. #include <dt-bindings/soc/qcom,tcsr.h>
  6. / {
  7. compatible = "asrock,g10", "qcom,ipq8064";
  8. model = "ASRock G10";
  9. aliases {
  10. ethernet0 = &gmac1;
  11. ethernet1 = &gmac0;
  12. led-boot = &led_status_blue;
  13. led-failsafe = &led_status_amber;
  14. led-running = &led_status_blue;
  15. led-upgrade = &led_status_amber;
  16. };
  17. chosen {
  18. bootargs-override = "console=ttyMSM0,115200n8";
  19. };
  20. leds {
  21. compatible = "gpio-leds";
  22. pinctrl-0 = <&led_pins>;
  23. pinctrl-names = "default";
  24. /*
  25. * this is a bit misleading. Because there are about seven
  26. * multicolor LEDs connected all wired together in parallel.
  27. */
  28. status_yellow {
  29. function = LED_FUNCTION_STATUS;
  30. color = <LED_COLOR_ID_YELLOW>;
  31. gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
  32. };
  33. led_status_amber: status_amber {
  34. function = LED_FUNCTION_STATUS;
  35. color = <LED_COLOR_ID_AMBER>;
  36. gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
  37. };
  38. led_status_blue: status_blue {
  39. function = LED_FUNCTION_STATUS;
  40. color = <LED_COLOR_ID_BLUE>;
  41. gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
  42. };
  43. /*
  44. * LED is declared in vendors boardfile but it's not
  45. * working and the manual doesn't mention anything
  46. * about the LED being white.
  47. status_white {
  48. function = LED_FUNCTION_STATUS;
  49. color = <LED_COLOR_ID_WHITE>;
  50. gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
  51. };
  52. */
  53. };
  54. i2c-gpio {
  55. #address-cells = <1>;
  56. #size-cells = <0>;
  57. compatible = "i2c-gpio";
  58. gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>, /* sda */
  59. <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; /* scl */
  60. i2c-gpio,delay-us = <5>;
  61. i2c-gpio,scl-output-only;
  62. mcu@50 {
  63. reg = <0x50>;
  64. compatible = "sonix,sn8f25e21";
  65. };
  66. };
  67. keys {
  68. compatible = "gpio-keys";
  69. pinctrl-0 = <&button_pins>;
  70. pinctrl-names = "default";
  71. ir-remote {
  72. label = "ir-remote";
  73. gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
  74. linux,code = <BTN_0>;
  75. debounce-interval = <60>;
  76. wakeup-source;
  77. };
  78. reset {
  79. label = "reset";
  80. gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
  81. linux,code = <KEY_RESTART>;
  82. debounce-interval = <60>;
  83. wakeup-source;
  84. };
  85. wps5g {
  86. label = "wps5g";
  87. gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
  88. linux,code = <KEY_WPS_BUTTON>;
  89. debounce-interval = <60>;
  90. wakeup-source;
  91. };
  92. wps2g {
  93. label = "wps2g";
  94. gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
  95. linux,code = <KEY_WPS_BUTTON>;
  96. debounce-interval = <60>;
  97. wakeup-source;
  98. };
  99. };
  100. };
  101. &adm_dma {
  102. status = "okay";
  103. };
  104. &gmac1 {
  105. status = "okay";
  106. pinctrl-0 = <&rgmii2_pins>;
  107. pinctrl-names = "default";
  108. phy-mode = "rgmii";
  109. qcom,id = <1>;
  110. fixed-link {
  111. speed = <1000>;
  112. full-duplex;
  113. };
  114. };
  115. &gmac2 {
  116. status = "okay";
  117. phy-mode = "sgmii";
  118. qcom,id = <2>;
  119. fixed-link {
  120. speed = <1000>;
  121. full-duplex;
  122. };
  123. };
  124. &gsbi4_serial {
  125. pinctrl-0 = <&uart0_pins>;
  126. pinctrl-names = "default";
  127. };
  128. &mdio0 {
  129. status = "okay";
  130. pinctrl-0 = <&mdio0_pins>;
  131. pinctrl-names = "default";
  132. switch@10 {
  133. compatible = "qca,qca8337";
  134. #address-cells = <1>;
  135. #size-cells = <0>;
  136. reg = <0x10>;
  137. ports {
  138. #address-cells = <1>;
  139. #size-cells = <0>;
  140. port@0 {
  141. reg = <0>;
  142. label = "cpu";
  143. ethernet = <&gmac1>;
  144. phy-mode = "rgmii";
  145. tx-internal-delay-ps = <1000>;
  146. rx-internal-delay-ps = <1000>;
  147. fixed-link {
  148. speed = <1000>;
  149. full-duplex;
  150. };
  151. };
  152. port@1 {
  153. reg = <1>;
  154. label = "wan";
  155. phy-mode = "internal";
  156. phy-handle = <&phy_port1>;
  157. };
  158. port@2 {
  159. reg = <2>;
  160. label = "lan1";
  161. phy-mode = "internal";
  162. phy-handle = <&phy_port2>;
  163. };
  164. port@3 {
  165. reg = <3>;
  166. label = "lan2";
  167. phy-mode = "internal";
  168. phy-handle = <&phy_port3>;
  169. };
  170. port@4 {
  171. reg = <4>;
  172. label = "lan3";
  173. phy-mode = "internal";
  174. phy-handle = <&phy_port4>;
  175. };
  176. port@5 {
  177. reg = <5>;
  178. label = "lan4";
  179. phy-mode = "internal";
  180. phy-handle = <&phy_port5>;
  181. };
  182. port@6 {
  183. reg = <6>;
  184. label = "cpu";
  185. ethernet = <&gmac2>;
  186. phy-mode = "sgmii";
  187. qca,sgmii-enable-pll;
  188. fixed-link {
  189. speed = <1000>;
  190. full-duplex;
  191. };
  192. };
  193. };
  194. mdio {
  195. #address-cells = <1>;
  196. #size-cells = <0>;
  197. phy_port1: phy@0 {
  198. reg = <0>;
  199. };
  200. phy_port2: phy@1 {
  201. reg = <1>;
  202. };
  203. phy_port3: phy@2 {
  204. reg = <2>;
  205. };
  206. phy_port4: phy@3 {
  207. reg = <3>;
  208. };
  209. phy_port5: phy@4 {
  210. reg = <4>;
  211. };
  212. };
  213. };
  214. };
  215. &nand {
  216. status = "okay";
  217. nand@0 {
  218. reg = <0>;
  219. compatible = "qcom,nandcs";
  220. nand-ecc-strength = <4>;
  221. nand-bus-width = <8>;
  222. nand-ecc-step-size = <512>;
  223. nand-is-boot-medium;
  224. qcom,boot-partitions = <0x0 0x1200000>;
  225. partitions {
  226. compatible = "qcom,smem-part";
  227. };
  228. };
  229. };
  230. &pcie0 {
  231. status = "okay";
  232. bridge@0,0 {
  233. reg = <0x00000000 0 0 0 0>;
  234. #address-cells = <3>;
  235. #size-cells = <2>;
  236. ranges;
  237. wifi5g: wifi@1,0 {
  238. reg = <0x00010000 0 0 0 0>;
  239. compatible = "qcom,ath10k";
  240. qcom,ath10k-calibration-variant = "ASRock-G10";
  241. };
  242. };
  243. };
  244. &pcie1 {
  245. status = "okay";
  246. bridge@0,0 {
  247. reg = <0x00000000 0 0 0 0>;
  248. #address-cells = <3>;
  249. #size-cells = <2>;
  250. ranges;
  251. wifi2g: wifi@1,0 {
  252. reg = <0x00010000 0 0 0 0>;
  253. compatible = "qcom,ath10k";
  254. qcom,ath10k-calibration-variant = "ASRock-G10";
  255. };
  256. };
  257. };
  258. &qcom_pinmux {
  259. led_pins: led_pins {
  260. mux {
  261. pins = "gpio7", "gpio8", "gpio9", "gpio26";
  262. function = "gpio";
  263. drive-strength = <2>;
  264. bias-pull-up;
  265. };
  266. };
  267. button_pins: button_pins {
  268. mux {
  269. pins = "gpio15", "gpio16", "gpio64", "gpio65";
  270. function = "gpio";
  271. drive-strength = <2>;
  272. bias-pull-up;
  273. };
  274. };
  275. uart0_pins: uart0_pins {
  276. mux {
  277. pins = "gpio10", "gpio11";
  278. function = "gsbi4";
  279. drive-strength = <10>;
  280. bias-disable;
  281. };
  282. };
  283. };
  284. &rpm {
  285. pinctrl-0 = <&i2c4_pins>;
  286. pinctrl-names = "default";
  287. };
  288. &hs_phy_0 {
  289. status = "okay";
  290. };
  291. &ss_phy_0 {
  292. status = "okay";
  293. };
  294. &usb3_0 {
  295. status = "okay";
  296. };
  297. &hs_phy_1 {
  298. status = "okay";
  299. };
  300. &ss_phy_1 {
  301. status = "okay";
  302. };
  303. &usb3_1 {
  304. status = "okay";
  305. };
  306. &tcsr {
  307. qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
  308. };
  309. /delete-node/ &pcie2_pins;
  310. /delete-node/ &pcie2;