qcom-ipq8064-onhub.dtsi 8.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2014 The ChromiumOS Authors
  4. */
  5. #include "qcom-ipq8064-smb208.dtsi"
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/input/input.h>
  8. #include <dt-bindings/soc/qcom,tcsr.h>
  9. / {
  10. aliases {
  11. ethernet0 = &gmac0;
  12. ethernet1 = &gmac2;
  13. mdio-gpio0 = &mdio;
  14. serial0 = &gsbi4_serial;
  15. };
  16. chosen {
  17. stdout-path = "serial0:115200n8";
  18. };
  19. reserved-memory {
  20. #address-cells = <1>;
  21. #size-cells = <1>;
  22. ranges;
  23. rsvd@41200000 {
  24. reg = <0x41200000 0x300000>;
  25. no-map;
  26. };
  27. };
  28. keys {
  29. compatible = "gpio-keys";
  30. pinctrl-0 = <&button_pins>;
  31. pinctrl-names = "default";
  32. reset {
  33. label = "reset";
  34. gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
  35. linux,code = <KEY_RESTART>;
  36. debounce-interval = <60>;
  37. wakeup-source;
  38. };
  39. dev {
  40. label = "dev";
  41. gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
  42. linux,code = <KEY_CONFIG>;
  43. debounce-interval = <60>;
  44. wakeup-source;
  45. };
  46. };
  47. mdio: mdio {
  48. compatible = "virtual,mdio-gpio";
  49. #address-cells = <1>;
  50. #size-cells = <0>;
  51. gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
  52. <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
  53. pinctrl-0 = <&mdio_pins>;
  54. pinctrl-names = "default";
  55. switch@10 {
  56. compatible = "qca,qca8337";
  57. #address-cells = <1>;
  58. #size-cells = <0>;
  59. reg = <0x10>;
  60. ports {
  61. #address-cells = <1>;
  62. #size-cells = <0>;
  63. port@0 {
  64. reg = <0>;
  65. label = "cpu";
  66. ethernet = <&gmac0>;
  67. phy-mode = "rgmii";
  68. tx-internal-delay-ps = <1000>;
  69. rx-internal-delay-ps = <1000>;
  70. fixed-link {
  71. speed = <1000>;
  72. full-duplex;
  73. };
  74. };
  75. port@1 {
  76. reg = <1>;
  77. label = "lan1";
  78. phy-mode = "internal";
  79. phy-handle = <&phy_port1>;
  80. };
  81. port@2 {
  82. reg = <2>;
  83. label = "wan";
  84. phy-mode = "internal";
  85. phy-handle = <&phy_port2>;
  86. };
  87. port@6 {
  88. reg = <6>;
  89. label = "cpu";
  90. ethernet = <&gmac2>;
  91. phy-mode = "sgmii";
  92. qca,sgmii-enable-pll;
  93. fixed-link {
  94. speed = <1000>;
  95. full-duplex;
  96. };
  97. };
  98. };
  99. mdio {
  100. #address-cells = <1>;
  101. #size-cells = <0>;
  102. phy_port1: phy@0 {
  103. reg = <0>;
  104. };
  105. phy_port2: phy@1 {
  106. reg = <1>;
  107. };
  108. };
  109. };
  110. };
  111. soc {
  112. rng@1a500000 {
  113. status = "disabled";
  114. };
  115. sound {
  116. compatible = "google,storm-audio";
  117. qcom,model = "ipq806x-storm";
  118. cpu = <&lpass>;
  119. codec = <&max98357a>;
  120. };
  121. lpass: lpass@28100000 {
  122. status = "okay";
  123. pinctrl-names = "default", "idle";
  124. pinctrl-0 = <&mi2s_default>;
  125. pinctrl-1 = <&mi2s_idle>;
  126. };
  127. max98357a: max98357a {
  128. compatible = "maxim,max98357a";
  129. #sound-dai-cells = <1>;
  130. pinctrl-names = "default";
  131. pinctrl-0 = <&sdmode_pins>;
  132. sdmode-gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
  133. };
  134. };
  135. };
  136. &qcom_pinmux {
  137. rgmii0_pins: rgmii0_pins {
  138. mux {
  139. pins = "gpio2", "gpio66";
  140. drive-strength = <8>;
  141. bias-disable;
  142. };
  143. };
  144. mi2s_pins {
  145. mi2s_default: mi2s_default {
  146. dout {
  147. pins = "gpio32";
  148. function = "mi2s";
  149. drive-strength = <16>;
  150. bias-disable;
  151. };
  152. sync {
  153. pins = "gpio27";
  154. function = "mi2s";
  155. drive-strength = <16>;
  156. bias-disable;
  157. };
  158. clk {
  159. pins = "gpio28";
  160. function = "mi2s";
  161. drive-strength = <16>;
  162. bias-disable;
  163. };
  164. };
  165. mi2s_idle: mi2s_idle {
  166. dout {
  167. pins = "gpio32";
  168. function = "mi2s";
  169. drive-strength = <2>;
  170. bias-pull-down;
  171. };
  172. sync {
  173. pins = "gpio27";
  174. function = "mi2s";
  175. drive-strength = <2>;
  176. bias-pull-down;
  177. };
  178. clk {
  179. pins = "gpio28";
  180. function = "mi2s";
  181. drive-strength = <2>;
  182. bias-pull-down;
  183. };
  184. };
  185. };
  186. mdio_pins: mdio_pins {
  187. mux {
  188. pins = "gpio0", "gpio1";
  189. function = "gpio";
  190. drive-strength = <8>;
  191. bias-disable;
  192. };
  193. rst {
  194. pins = "gpio26";
  195. output-low;
  196. };
  197. };
  198. sdmode_pins: sdmode_pinmux {
  199. pins = "gpio25";
  200. function = "gpio";
  201. drive-strength = <16>;
  202. bias-disable;
  203. };
  204. sdcc1_pins: sdcc1_pinmux {
  205. mux {
  206. pins = "gpio38", "gpio39", "gpio40",
  207. "gpio41", "gpio42", "gpio43",
  208. "gpio44", "gpio45", "gpio46",
  209. "gpio47";
  210. function = "sdc1";
  211. };
  212. cmd {
  213. pins = "gpio45";
  214. drive-strength = <10>;
  215. bias-pull-up;
  216. };
  217. data {
  218. pins = "gpio38", "gpio39", "gpio40",
  219. "gpio41", "gpio43", "gpio44",
  220. "gpio46", "gpio47";
  221. drive-strength = <10>;
  222. bias-pull-up;
  223. };
  224. clk {
  225. pins = "gpio42";
  226. drive-strength = <16>;
  227. bias-pull-down;
  228. };
  229. };
  230. i2c1_pins: i2c1_pinmux {
  231. pins = "gpio53", "gpio54";
  232. function = "gsbi1";
  233. bias-disable;
  234. };
  235. rpm_i2c_pinmux: rpm_i2c_pinmux {
  236. mux {
  237. pins = "gpio12", "gpio13";
  238. function = "gsbi4";
  239. drive-strength = <12>;
  240. bias-disable;
  241. };
  242. };
  243. spi_pins: spi_pins {
  244. mux {
  245. pins = "gpio18", "gpio19", "gpio21";
  246. function = "gsbi5";
  247. bias-pull-down;
  248. /delete-property/ bias-none;
  249. /delete-property/ drive-strength;
  250. };
  251. data {
  252. pins = "gpio18", "gpio19";
  253. drive-strength = <10>;
  254. };
  255. cs {
  256. pins = "gpio20";
  257. drive-strength = <10>;
  258. bias-pull-up;
  259. };
  260. clk {
  261. pins = "gpio21";
  262. drive-strength = <12>;
  263. };
  264. };
  265. fw_pinmux {
  266. wp {
  267. pins = "gpio17";
  268. output-low;
  269. };
  270. };
  271. button_pins: button_pins {
  272. recovery {
  273. pins = "gpio16";
  274. function = "gpio";
  275. bias-none;
  276. };
  277. developer {
  278. pins = "gpio15";
  279. function = "gpio";
  280. bias-none;
  281. };
  282. };
  283. spi6_pins: spi6_pins {
  284. mux {
  285. pins = "gpio55", "gpio56", "gpio58";
  286. function = "gsbi6";
  287. bias-pull-down;
  288. };
  289. data {
  290. pins = "gpio55", "gpio56";
  291. drive-strength = <10>;
  292. };
  293. cs {
  294. pins = "gpio57";
  295. drive-strength = <10>;
  296. bias-pull-up;
  297. output-high;
  298. };
  299. clk {
  300. pins = "gpio58";
  301. drive-strength = <12>;
  302. };
  303. };
  304. };
  305. &adm_dma {
  306. status = "okay";
  307. };
  308. &gmac0 {
  309. status = "okay";
  310. phy-mode = "rgmii";
  311. qcom,id = <0>;
  312. pinctrl-0 = <&rgmii0_pins>;
  313. pinctrl-names = "default";
  314. fixed-link {
  315. speed = <1000>;
  316. full-duplex;
  317. };
  318. };
  319. &gmac2 {
  320. status = "okay";
  321. phy-mode = "sgmii";
  322. qcom,id = <2>;
  323. fixed-link {
  324. speed = <1000>;
  325. full-duplex;
  326. };
  327. };
  328. &gsbi1 {
  329. status = "okay";
  330. qcom,mode = <GSBI_PROT_I2C_UART>;
  331. };
  332. &gsbi1_i2c {
  333. status = "okay";
  334. clock-frequency = <100000>;
  335. pinctrl-0 = <&i2c1_pins>;
  336. pinctrl-names = "default";
  337. tpm@20 {
  338. compatible = "infineon,slb9645tt";
  339. reg = <0x20>;
  340. powered-while-suspended;
  341. };
  342. };
  343. &gsbi4 {
  344. status = "okay";
  345. qcom,mode = <GSBI_PROT_I2C_UART>;
  346. };
  347. &gsbi4_serial {
  348. status = "okay";
  349. };
  350. &gsbi5 {
  351. status = "okay";
  352. qcom,mode = <GSBI_PROT_SPI>;
  353. spi4: spi@1a280000 {
  354. status = "okay";
  355. spi-max-frequency = <50000000>;
  356. pinctrl-0 = <&spi_pins>;
  357. pinctrl-names = "default";
  358. cs-gpios = <&qcom_pinmux 20 0>;
  359. flash: flash@0 {
  360. compatible = "jedec,spi-nor";
  361. spi-max-frequency = <50000000>;
  362. reg = <0>;
  363. };
  364. };
  365. };
  366. &gsbi6 {
  367. status = "okay";
  368. qcom,mode = <GSBI_PROT_SPI>;
  369. };
  370. &gsbi6_spi {
  371. status = "okay";
  372. spi-max-frequency = <25000000>;
  373. pinctrl-0 = <&spi6_pins>;
  374. pinctrl-names = "default";
  375. cs-gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
  376. dmas = <&adm_dma 8 0xb>,
  377. <&adm_dma 7 0x14>;
  378. dma-names = "rx", "tx";
  379. /*
  380. * This "spidev" was included in the manufacturer device tree. I suspect
  381. * it's the (unused) Zigbee radio -- SiliconLabs EM3581 Zigbee? There's
  382. * no driver or binding for this at the moment.
  383. */
  384. spidev@0 {
  385. compatible = "spidev";
  386. reg = <0>;
  387. spi-max-frequency = <25000000>;
  388. };
  389. };
  390. &pcie0 {
  391. status = "okay";
  392. pcie@0 {
  393. reg = <0 0 0 0 0>;
  394. #interrupt-cells = <1>;
  395. #size-cells = <2>;
  396. #address-cells = <3>;
  397. device_type = "pci";
  398. interrupt-controller;
  399. ath10k@0,0 {
  400. reg = <0 0 0 0 0>;
  401. device_type = "pci";
  402. qcom,ath10k-sa-gpio = <2 3 4 0>;
  403. qcom,ath10k-sa-gpio-func = <5 5 5 0>;
  404. };
  405. };
  406. };
  407. &pcie1 {
  408. status = "okay";
  409. pcie@0 {
  410. reg = <0 0 0 0 0>;
  411. #interrupt-cells = <1>;
  412. #size-cells = <2>;
  413. #address-cells = <3>;
  414. device_type = "pci";
  415. interrupt-controller;
  416. ath10k@0,0 {
  417. reg = <0 0 0 0 0>;
  418. device_type = "pci";
  419. qcom,ath10k-sa-gpio = <2 3 4 0>;
  420. qcom,ath10k-sa-gpio-func = <5 5 5 0>;
  421. };
  422. };
  423. };
  424. &pcie2 {
  425. status = "okay";
  426. pcie@0 {
  427. reg = <0 0 0 0 0>;
  428. #interrupt-cells = <1>;
  429. #size-cells = <2>;
  430. #address-cells = <3>;
  431. device_type = "pci";
  432. interrupt-controller;
  433. ath10k@0,0 {
  434. reg = <0 0 0 0 0>;
  435. device_type = "pci";
  436. };
  437. };
  438. };
  439. &rpm {
  440. pinctrl-0 = <&rpm_i2c_pinmux>;
  441. pinctrl-names = "default";
  442. };
  443. &sdcc1 {
  444. status = "okay";
  445. pinctrl-0 = <&sdcc1_pins>;
  446. pinctrl-names = "default";
  447. /delete-property/ mmc-ddr-1_8v;
  448. };
  449. &tcsr {
  450. compatible = "qcom,tcsr-ipq8064", "qcom,tcsr", "syscon";
  451. qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
  452. };
  453. &hs_phy_0 {
  454. status = "okay";
  455. };
  456. &ss_phy_0 {
  457. status = "okay";
  458. };
  459. &usb3_0 {
  460. status = "okay";
  461. };
  462. &hs_phy_1 {
  463. status = "okay";
  464. };
  465. &ss_phy_1 {
  466. status = "okay";
  467. };
  468. &usb3_1 {
  469. status = "okay";
  470. };