qcom-ipq8064-r7500.dts 6.4 KB

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  1. #include "qcom-ipq8064-v1.0.dtsi"
  2. #include <dt-bindings/input/input.h>
  3. #include <dt-bindings/leds/common.h>
  4. #include <dt-bindings/soc/qcom,tcsr.h>
  5. / {
  6. model = "Netgear Nighthawk X4 R7500";
  7. compatible = "netgear,r7500", "qcom,ipq8064";
  8. memory@0 {
  9. reg = <0x42000000 0xe000000>;
  10. device_type = "memory";
  11. };
  12. reserved-memory {
  13. #address-cells = <1>;
  14. #size-cells = <1>;
  15. ranges;
  16. rsvd@41200000 {
  17. reg = <0x41200000 0x300000>;
  18. no-map;
  19. };
  20. };
  21. aliases {
  22. mdio-gpio0 = &mdio0;
  23. led-boot = &power_white;
  24. led-failsafe = &power_amber;
  25. led-running = &power_white;
  26. led-upgrade = &power_amber;
  27. };
  28. chosen {
  29. bootargs = "rootfstype=squashfs noinitrd";
  30. };
  31. keys {
  32. compatible = "gpio-keys";
  33. pinctrl-0 = <&button_pins>;
  34. pinctrl-names = "default";
  35. wifi {
  36. label = "wifi";
  37. gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
  38. linux,code = <KEY_RFKILL>;
  39. debounce-interval = <60>;
  40. wakeup-source;
  41. };
  42. reset {
  43. label = "reset";
  44. gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  45. linux,code = <KEY_RESTART>;
  46. debounce-interval = <60>;
  47. wakeup-source;
  48. };
  49. wps {
  50. label = "wps";
  51. gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
  52. linux,code = <KEY_WPS_BUTTON>;
  53. debounce-interval = <60>;
  54. wakeup-source;
  55. };
  56. };
  57. leds {
  58. compatible = "gpio-leds";
  59. pinctrl-0 = <&led_pins>;
  60. pinctrl-names = "default";
  61. usb1 {
  62. label = "white:usb1";
  63. gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
  64. };
  65. usb2 {
  66. label = "white:usb2";
  67. gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
  68. };
  69. power_amber: power_amber {
  70. function = LED_FUNCTION_POWER;
  71. color = <LED_COLOR_ID_AMBER>;
  72. gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
  73. };
  74. wan_white {
  75. function = LED_FUNCTION_WAN;
  76. color = <LED_COLOR_ID_WHITE>;
  77. gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
  78. };
  79. wan_amber {
  80. function = LED_FUNCTION_WAN;
  81. color = <LED_COLOR_ID_AMBER>;
  82. gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
  83. };
  84. wps {
  85. function = LED_FUNCTION_WPS;
  86. color = <LED_COLOR_ID_WHITE>;
  87. gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
  88. };
  89. esata {
  90. label = "white:esata";
  91. gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
  92. };
  93. power_white: power_white {
  94. function = LED_FUNCTION_POWER;
  95. color = <LED_COLOR_ID_WHITE>;
  96. gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
  97. default-state = "keep";
  98. };
  99. wifi {
  100. label = "white:wifi";
  101. gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
  102. };
  103. };
  104. };
  105. &qcom_pinmux {
  106. button_pins: button_pins {
  107. mux {
  108. pins = "gpio6", "gpio54", "gpio65";
  109. function = "gpio";
  110. drive-strength = <2>;
  111. bias-pull-up;
  112. };
  113. };
  114. led_pins: led_pins {
  115. mux {
  116. pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
  117. "gpio24","gpio26", "gpio53", "gpio64";
  118. function = "gpio";
  119. drive-strength = <2>;
  120. bias-pull-up;
  121. };
  122. };
  123. };
  124. &gsbi5 {
  125. status = "disabled";
  126. spi@1a280000 {
  127. status = "disabled";
  128. };
  129. };
  130. &hs_phy_0 {
  131. status = "okay";
  132. };
  133. &ss_phy_0 {
  134. status = "okay";
  135. };
  136. &usb3_0 {
  137. status = "okay";
  138. };
  139. &hs_phy_1 {
  140. status = "okay";
  141. };
  142. &ss_phy_1 {
  143. status = "okay";
  144. };
  145. &usb3_1 {
  146. status = "okay";
  147. };
  148. &pcie0 {
  149. status = "okay";
  150. };
  151. &pcie1 {
  152. status = "okay";
  153. max-link-speed = <1>;
  154. };
  155. &nand {
  156. status = "okay";
  157. nand@0 {
  158. reg = <0>;
  159. compatible = "qcom,nandcs";
  160. nand-ecc-strength = <4>;
  161. nand-bus-width = <8>;
  162. nand-ecc-step-size = <512>;
  163. nand-is-boot-medium;
  164. qcom,boot-partitions = <0x0 0x1180000>;
  165. partitions {
  166. compatible = "fixed-partitions";
  167. #address-cells = <1>;
  168. #size-cells = <1>;
  169. qcadata@0 {
  170. label = "qcadata";
  171. reg = <0x0000000 0x0c80000>;
  172. read-only;
  173. };
  174. APPSBL@c80000 {
  175. label = "APPSBL";
  176. reg = <0x0c80000 0x0500000>;
  177. read-only;
  178. };
  179. APPSBLENV@1180000 {
  180. label = "APPSBLENV";
  181. reg = <0x1180000 0x0080000>;
  182. read-only;
  183. };
  184. art: art@1200000 {
  185. label = "art";
  186. reg = <0x1200000 0x0140000>;
  187. read-only;
  188. nvmem-layout {
  189. compatible = "fixed-layout";
  190. #address-cells = <1>;
  191. #size-cells = <1>;
  192. macaddr_art_0: macaddr@0 {
  193. reg = <0x0 0x6>;
  194. };
  195. macaddr_art_6: macaddr@6 {
  196. reg = <0x6 0x6>;
  197. };
  198. };
  199. };
  200. kernel@1340000 {
  201. label = "kernel";
  202. reg = <0x1340000 0x0400000>;
  203. };
  204. ubi@1740000 {
  205. label = "ubi";
  206. reg = <0x1740000 0x1600000>;
  207. };
  208. netgear@2d40000 {
  209. label = "netgear";
  210. reg = <0x2d40000 0x0c00000>;
  211. read-only;
  212. };
  213. reserve@3940000 {
  214. label = "reserve";
  215. reg = <0x3940000 0x46c0000>;
  216. read-only;
  217. };
  218. };
  219. };
  220. };
  221. &mdio0 {
  222. status = "okay";
  223. pinctrl-0 = <&mdio0_pins>;
  224. pinctrl-names = "default";
  225. switch@10 {
  226. compatible = "qca,qca8337";
  227. #address-cells = <1>;
  228. #size-cells = <0>;
  229. reg = <0x10>;
  230. ports {
  231. #address-cells = <1>;
  232. #size-cells = <0>;
  233. port@0 {
  234. reg = <0>;
  235. label = "cpu";
  236. ethernet = <&gmac1>;
  237. phy-mode = "rgmii";
  238. tx-internal-delay-ps = <1000>;
  239. rx-internal-delay-ps = <1000>;
  240. fixed-link {
  241. speed = <1000>;
  242. full-duplex;
  243. };
  244. };
  245. port@1 {
  246. reg = <1>;
  247. label = "lan1";
  248. phy-mode = "internal";
  249. phy-handle = <&phy_port1>;
  250. };
  251. port@2 {
  252. reg = <2>;
  253. label = "lan2";
  254. phy-mode = "internal";
  255. phy-handle = <&phy_port2>;
  256. };
  257. port@3 {
  258. reg = <3>;
  259. label = "lan3";
  260. phy-mode = "internal";
  261. phy-handle = <&phy_port3>;
  262. };
  263. port@4 {
  264. reg = <4>;
  265. label = "lan4";
  266. phy-mode = "internal";
  267. phy-handle = <&phy_port4>;
  268. };
  269. port@5 {
  270. reg = <5>;
  271. label = "wan";
  272. phy-mode = "internal";
  273. phy-handle = <&phy_port5>;
  274. };
  275. port@6 {
  276. reg = <6>;
  277. label = "cpu";
  278. ethernet = <&gmac2>;
  279. phy-mode = "sgmii";
  280. qca,sgmii-enable-pll;
  281. fixed-link {
  282. speed = <1000>;
  283. full-duplex;
  284. };
  285. };
  286. };
  287. mdio {
  288. #address-cells = <1>;
  289. #size-cells = <0>;
  290. phy_port1: phy@0 {
  291. reg = <0>;
  292. };
  293. phy_port2: phy@1 {
  294. reg = <1>;
  295. };
  296. phy_port3: phy@2 {
  297. reg = <2>;
  298. };
  299. phy_port4: phy@3 {
  300. reg = <3>;
  301. };
  302. phy_port5: phy@4 {
  303. reg = <4>;
  304. };
  305. };
  306. };
  307. };
  308. &gmac1 {
  309. status = "okay";
  310. phy-mode = "rgmii";
  311. qcom,id = <1>;
  312. pinctrl-0 = <&rgmii2_pins>;
  313. pinctrl-names = "default";
  314. nvmem-cells = <&macaddr_art_6>;
  315. nvmem-cell-names = "mac-address";
  316. fixed-link {
  317. speed = <1000>;
  318. full-duplex;
  319. };
  320. };
  321. &gmac2 {
  322. status = "okay";
  323. phy-mode = "sgmii";
  324. qcom,id = <2>;
  325. nvmem-cells = <&macaddr_art_0>;
  326. nvmem-cell-names = "mac-address";
  327. fixed-link {
  328. speed = <1000>;
  329. full-duplex;
  330. };
  331. };
  332. &tcsr {
  333. qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
  334. compatible = "qcom,tcsr";
  335. };
  336. &adm_dma {
  337. status = "okay";
  338. };