qcom-ipq8064-r7500v2.dts 7.6 KB

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  1. #include "qcom-ipq8064-v2.0-smb208.dtsi"
  2. #include <dt-bindings/input/input.h>
  3. #include <dt-bindings/leds/common.h>
  4. / {
  5. model = "Netgear Nighthawk X4 R7500v2";
  6. compatible = "netgear,r7500v2", "qcom,ipq8064";
  7. memory@0 {
  8. reg = <0x42000000 0x1e000000>;
  9. device_type = "memory";
  10. };
  11. reserved-memory {
  12. rsvd@5fe00000 {
  13. reg = <0x5fe00000 0x200000>;
  14. reusable;
  15. };
  16. };
  17. aliases {
  18. mdio-gpio0 = &mdio0;
  19. led-boot = &power;
  20. led-failsafe = &power;
  21. led-running = &power;
  22. led-upgrade = &power;
  23. };
  24. chosen {
  25. bootargs = "rootfstype=squashfs noinitrd";
  26. };
  27. keys {
  28. compatible = "gpio-keys";
  29. pinctrl-0 = <&button_pins>;
  30. pinctrl-names = "default";
  31. wifi {
  32. label = "wifi";
  33. gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
  34. linux,code = <KEY_RFKILL>;
  35. debounce-interval = <60>;
  36. wakeup-source;
  37. };
  38. reset {
  39. label = "reset";
  40. gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  41. linux,code = <KEY_RESTART>;
  42. debounce-interval = <60>;
  43. wakeup-source;
  44. };
  45. wps {
  46. label = "wps";
  47. gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
  48. linux,code = <KEY_WPS_BUTTON>;
  49. debounce-interval = <60>;
  50. wakeup-source;
  51. };
  52. };
  53. leds {
  54. compatible = "gpio-leds";
  55. pinctrl-0 = <&led_pins>;
  56. pinctrl-names = "default";
  57. usb1 {
  58. label = "amber:usb1";
  59. gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
  60. };
  61. usb3 {
  62. label = "amber:usb3";
  63. gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
  64. };
  65. status {
  66. function = LED_FUNCTION_STATUS;
  67. color = <LED_COLOR_ID_AMBER>;
  68. gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
  69. };
  70. internet {
  71. label = "white:internet";
  72. gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
  73. };
  74. wan {
  75. function = LED_FUNCTION_WAN;
  76. color = <LED_COLOR_ID_WHITE>;
  77. gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
  78. };
  79. wps {
  80. function = LED_FUNCTION_WPS;
  81. color = <LED_COLOR_ID_WHITE>;
  82. gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
  83. };
  84. esata {
  85. label = "white:esata";
  86. gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
  87. };
  88. power: power {
  89. function = LED_FUNCTION_POWER;
  90. color = <LED_COLOR_ID_WHITE>;
  91. gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
  92. default-state = "keep";
  93. };
  94. wifi {
  95. label = "white:wifi";
  96. gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
  97. };
  98. };
  99. };
  100. &adm_dma {
  101. status = "okay";
  102. };
  103. &qcom_pinmux {
  104. button_pins: button_pins {
  105. mux {
  106. pins = "gpio6", "gpio54", "gpio65";
  107. function = "gpio";
  108. drive-strength = <2>;
  109. bias-pull-up;
  110. };
  111. };
  112. led_pins: led_pins {
  113. mux {
  114. pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
  115. "gpio24","gpio26", "gpio53", "gpio64";
  116. function = "gpio";
  117. drive-strength = <2>;
  118. bias-pull-up;
  119. };
  120. };
  121. usb0_pwr_en_pins: usb0_pwr_en_pins {
  122. mux {
  123. pins = "gpio15";
  124. function = "gpio";
  125. drive-strength = <12>;
  126. bias-pull-down;
  127. output-high;
  128. };
  129. };
  130. usb1_pwr_en_pins: usb1_pwr_en_pins {
  131. mux {
  132. pins = "gpio16", "gpio68";
  133. function = "gpio";
  134. drive-strength = <12>;
  135. bias-pull-down;
  136. output-high;
  137. };
  138. };
  139. };
  140. &sata_phy {
  141. status = "okay";
  142. };
  143. &sata {
  144. status = "okay";
  145. };
  146. &hs_phy_0 {
  147. status = "okay";
  148. };
  149. &ss_phy_0 {
  150. status = "okay";
  151. };
  152. &usb3_0 {
  153. status = "okay";
  154. pinctrl-0 = <&usb0_pwr_en_pins>;
  155. pinctrl-names = "default";
  156. };
  157. &hs_phy_1 {
  158. status = "okay";
  159. };
  160. &ss_phy_1 {
  161. status = "okay";
  162. };
  163. &usb3_1 {
  164. status = "okay";
  165. pinctrl-0 = <&usb1_pwr_en_pins>;
  166. pinctrl-names = "default";
  167. };
  168. &pcie0 {
  169. status = "okay";
  170. reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
  171. pinctrl-0 = <&pcie0_pins>;
  172. pinctrl-names = "default";
  173. bridge@0,0 {
  174. reg = <0x00000000 0 0 0 0>;
  175. #address-cells = <3>;
  176. #size-cells = <2>;
  177. ranges;
  178. wifi@1,0 {
  179. compatible = "pci168c,0040";
  180. reg = <0x00010000 0 0 0 0>;
  181. nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>;
  182. nvmem-cell-names = "mac-address", "pre-calibration";
  183. };
  184. };
  185. };
  186. &pcie1 {
  187. status = "okay";
  188. reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
  189. pinctrl-0 = <&pcie1_pins>;
  190. pinctrl-names = "default";
  191. max-link-speed = <1>;
  192. bridge@0,0 {
  193. reg = <0x00000000 0 0 0 0>;
  194. #address-cells = <3>;
  195. #size-cells = <2>;
  196. ranges;
  197. wifi@1,0 {
  198. compatible = "pci168c,0040";
  199. reg = <0x00010000 0 0 0 0>;
  200. nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>;
  201. nvmem-cell-names = "mac-address", "pre-calibration";
  202. };
  203. };
  204. };
  205. &nand {
  206. status = "okay";
  207. nand@0 {
  208. reg = <0>;
  209. compatible = "qcom,nandcs";
  210. nand-ecc-strength = <4>;
  211. nand-bus-width = <8>;
  212. nand-ecc-step-size = <512>;
  213. nand-is-boot-medium;
  214. qcom,boot-partitions = <0x0 0x1180000>;
  215. partitions {
  216. compatible = "fixed-partitions";
  217. #address-cells = <1>;
  218. #size-cells = <1>;
  219. qcadata@0 {
  220. label = "qcadata";
  221. reg = <0x0000000 0x0c80000>;
  222. read-only;
  223. };
  224. APPSBL@c80000 {
  225. label = "APPSBL";
  226. reg = <0x0c80000 0x0500000>;
  227. read-only;
  228. };
  229. APPSBLENV@1180000 {
  230. label = "APPSBLENV";
  231. reg = <0x1180000 0x0080000>;
  232. read-only;
  233. };
  234. art@1200000 {
  235. label = "art";
  236. reg = <0x1200000 0x0140000>;
  237. read-only;
  238. nvmem-layout {
  239. compatible = "fixed-layout";
  240. #address-cells = <1>;
  241. #size-cells = <1>;
  242. macaddr_art_0: macaddr@0 {
  243. reg = <0x0 0x6>;
  244. };
  245. macaddr_art_6: macaddr@6 {
  246. compatible = "mac-base";
  247. reg = <0x6 0x6>;
  248. #nvmem-cell-cells = <1>;
  249. };
  250. precal_art_1000: precal@1000 {
  251. reg = <0x1000 0x2f20>;
  252. };
  253. precal_art_5000: precal@5000 {
  254. reg = <0x5000 0x2f20>;
  255. };
  256. };
  257. };
  258. artbak: art@1340000 {
  259. label = "artbak";
  260. reg = <0x1340000 0x0140000>;
  261. read-only;
  262. };
  263. kernel@1480000 {
  264. label = "kernel";
  265. reg = <0x1480000 0x0400000>;
  266. };
  267. ubi@1880000 {
  268. label = "ubi";
  269. reg = <0x1880000 0x6080000>;
  270. };
  271. reserve@7900000 {
  272. label = "reserve";
  273. reg = <0x7900000 0x0700000>;
  274. read-only;
  275. };
  276. };
  277. };
  278. };
  279. &mdio0 {
  280. status = "okay";
  281. pinctrl-0 = <&mdio0_pins>;
  282. pinctrl-names = "default";
  283. switch@10 {
  284. compatible = "qca,qca8337";
  285. #address-cells = <1>;
  286. #size-cells = <0>;
  287. reg = <0x10>;
  288. ports {
  289. #address-cells = <1>;
  290. #size-cells = <0>;
  291. port@0 {
  292. reg = <0>;
  293. label = "cpu";
  294. ethernet = <&gmac1>;
  295. phy-mode = "rgmii";
  296. tx-internal-delay-ps = <1000>;
  297. rx-internal-delay-ps = <1000>;
  298. fixed-link {
  299. speed = <1000>;
  300. full-duplex;
  301. };
  302. };
  303. port@1 {
  304. reg = <1>;
  305. label = "lan1";
  306. phy-mode = "internal";
  307. phy-handle = <&phy_port1>;
  308. };
  309. port@2 {
  310. reg = <2>;
  311. label = "lan2";
  312. phy-mode = "internal";
  313. phy-handle = <&phy_port2>;
  314. };
  315. port@3 {
  316. reg = <3>;
  317. label = "lan3";
  318. phy-mode = "internal";
  319. phy-handle = <&phy_port3>;
  320. };
  321. port@4 {
  322. reg = <4>;
  323. label = "lan4";
  324. phy-mode = "internal";
  325. phy-handle = <&phy_port4>;
  326. };
  327. port@5 {
  328. reg = <5>;
  329. label = "wan";
  330. phy-mode = "internal";
  331. phy-handle = <&phy_port5>;
  332. };
  333. port@6 {
  334. reg = <6>;
  335. label = "cpu";
  336. ethernet = <&gmac2>;
  337. phy-mode = "sgmii";
  338. qca,sgmii-enable-pll;
  339. fixed-link {
  340. speed = <1000>;
  341. full-duplex;
  342. };
  343. };
  344. };
  345. mdio {
  346. #address-cells = <1>;
  347. #size-cells = <0>;
  348. phy_port1: phy@0 {
  349. reg = <0>;
  350. };
  351. phy_port2: phy@1 {
  352. reg = <1>;
  353. };
  354. phy_port3: phy@2 {
  355. reg = <2>;
  356. };
  357. phy_port4: phy@3 {
  358. reg = <3>;
  359. };
  360. phy_port5: phy@4 {
  361. reg = <4>;
  362. };
  363. };
  364. };
  365. };
  366. &gmac1 {
  367. status = "okay";
  368. phy-mode = "rgmii";
  369. qcom,id = <1>;
  370. pinctrl-0 = <&rgmii2_pins>;
  371. pinctrl-names = "default";
  372. nvmem-cells = <&macaddr_art_6 0>;
  373. nvmem-cell-names = "mac-address";
  374. fixed-link {
  375. speed = <1000>;
  376. full-duplex;
  377. };
  378. };
  379. &gmac2 {
  380. status = "okay";
  381. phy-mode = "sgmii";
  382. qcom,id = <2>;
  383. nvmem-cells = <&macaddr_art_0>;
  384. nvmem-cell-names = "mac-address";
  385. fixed-link {
  386. speed = <1000>;
  387. full-duplex;
  388. };
  389. };