qcom-ipq8064-vr2600v.dts 8.4 KB

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  1. #include "qcom-ipq8064-v2.0-smb208.dtsi"
  2. #include <dt-bindings/input/input.h>
  3. #include <dt-bindings/leds/common.h>
  4. / {
  5. model = "TP-Link Archer VR2600v";
  6. compatible = "tplink,vr2600v", "qcom,ipq8064";
  7. memory@0 {
  8. reg = <0x42000000 0x1e000000>;
  9. device_type = "memory";
  10. };
  11. aliases {
  12. mdio-gpio0 = &mdio0;
  13. led-boot = &power;
  14. led-failsafe = &general;
  15. led-running = &power;
  16. led-upgrade = &general;
  17. };
  18. keys {
  19. compatible = "gpio-keys";
  20. pinctrl-0 = <&button_pins>;
  21. pinctrl-names = "default";
  22. wifi {
  23. label = "wifi";
  24. gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  25. linux,code = <KEY_RFKILL>;
  26. debounce-interval = <60>;
  27. wakeup-source;
  28. };
  29. reset {
  30. label = "reset";
  31. gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
  32. linux,code = <KEY_RESTART>;
  33. debounce-interval = <60>;
  34. wakeup-source;
  35. };
  36. wps {
  37. label = "wps";
  38. gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
  39. linux,code = <KEY_WPS_BUTTON>;
  40. debounce-interval = <60>;
  41. wakeup-source;
  42. };
  43. dect {
  44. label = "dect";
  45. gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
  46. linux,code = <KEY_PHONE>;
  47. debounce-interval = <60>;
  48. wakeup-source;
  49. };
  50. ledswitch {
  51. label = "ledswitch";
  52. gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
  53. linux,code = <KEY_LIGHTS_TOGGLE>;
  54. debounce-interval = <60>;
  55. wakeup-source;
  56. };
  57. };
  58. leds {
  59. compatible = "gpio-leds";
  60. pinctrl-0 = <&led_pins>;
  61. pinctrl-names = "default";
  62. dsl {
  63. label = "white:dsl";
  64. gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
  65. };
  66. usb {
  67. function = LED_FUNCTION_USB;
  68. color = <LED_COLOR_ID_WHITE>;
  69. gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
  70. };
  71. lan {
  72. function = LED_FUNCTION_LAN;
  73. color = <LED_COLOR_ID_WHITE>;
  74. gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
  75. };
  76. wlan2g {
  77. label = "white:wlan2g";
  78. gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
  79. };
  80. wlan5g {
  81. label = "white:wlan5g";
  82. gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>;
  83. };
  84. power: power {
  85. function = LED_FUNCTION_POWER;
  86. color = <LED_COLOR_ID_WHITE>;
  87. gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
  88. default-state = "keep";
  89. };
  90. phone {
  91. label = "white:phone";
  92. gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
  93. };
  94. wan {
  95. function = LED_FUNCTION_WAN;
  96. color = <LED_COLOR_ID_WHITE>;
  97. gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
  98. };
  99. general: general {
  100. label = "white:general";
  101. gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
  102. };
  103. };
  104. };
  105. &qcom_pinmux {
  106. led_pins: led_pins {
  107. mux {
  108. pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio17",
  109. "gpio26", "gpio53", "gpio56", "gpio66";
  110. function = "gpio";
  111. drive-strength = <2>;
  112. bias-pull-up;
  113. };
  114. };
  115. button_pins: button_pins {
  116. mux {
  117. pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68";
  118. function = "gpio";
  119. drive-strength = <2>;
  120. bias-pull-up;
  121. };
  122. };
  123. spi_pins: spi_pins {
  124. mux {
  125. pins = "gpio18", "gpio19", "gpio21";
  126. function = "gsbi5";
  127. bias-pull-down;
  128. };
  129. data {
  130. pins = "gpio18", "gpio19";
  131. drive-strength = <10>;
  132. };
  133. cs {
  134. pins = "gpio20";
  135. drive-strength = <10>;
  136. bias-pull-up;
  137. };
  138. clk {
  139. pins = "gpio21";
  140. drive-strength = <12>;
  141. };
  142. };
  143. };
  144. &gsbi5 {
  145. qcom,mode = <GSBI_PROT_SPI>;
  146. status = "okay";
  147. spi4: spi@1a280000 {
  148. status = "okay";
  149. pinctrl-0 = <&spi_pins>;
  150. pinctrl-names = "default";
  151. cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
  152. flash@0 {
  153. compatible = "jedec,spi-nor";
  154. #address-cells = <1>;
  155. #size-cells = <1>;
  156. spi-max-frequency = <50000000>;
  157. reg = <0>;
  158. partitions {
  159. compatible = "fixed-partitions";
  160. #address-cells = <1>;
  161. #size-cells = <1>;
  162. partition@0 {
  163. label = "SBL1";
  164. reg = <0x0 0x20000>;
  165. read-only;
  166. };
  167. partition@20000 {
  168. label = "MIBIB";
  169. reg = <0x20000 0x20000>;
  170. read-only;
  171. };
  172. partition@40000 {
  173. label = "SBL2";
  174. reg = <0x40000 0x40000>;
  175. read-only;
  176. };
  177. partition@80000 {
  178. label = "SBL3";
  179. reg = <0x80000 0x80000>;
  180. read-only;
  181. };
  182. partition@100000 {
  183. label = "DDRCONFIG";
  184. reg = <0x100000 0x10000>;
  185. read-only;
  186. };
  187. partition@110000 {
  188. label = "SSD";
  189. reg = <0x110000 0x10000>;
  190. read-only;
  191. };
  192. partition@120000 {
  193. label = "TZ";
  194. reg = <0x120000 0x80000>;
  195. read-only;
  196. };
  197. partition@1a0000 {
  198. label = "RPM";
  199. reg = <0x1a0000 0x80000>;
  200. read-only;
  201. };
  202. partition@220000 {
  203. label = "APPSBL";
  204. reg = <0x220000 0x80000>;
  205. read-only;
  206. };
  207. partition@2a0000 {
  208. label = "APPSBLENV";
  209. reg = <0x2a0000 0x40000>;
  210. read-only;
  211. };
  212. partition@2e0000 {
  213. label = "OLDART";
  214. reg = <0x2e0000 0x40000>;
  215. read-only;
  216. };
  217. partition@320000 {
  218. label = "firmware";
  219. reg = <0x320000 0xc60000>;
  220. compatible = "openwrt,uimage";
  221. openwrt,offset = <512>; /* account for pad-extra 512 */
  222. };
  223. /* hole 0xf80000 - 0xfaf100 */
  224. partition@faf100 {
  225. label = "default-mac";
  226. reg = <0xfaf100 0x00200>;
  227. read-only;
  228. nvmem-layout {
  229. compatible = "fixed-layout";
  230. #address-cells = <1>;
  231. #size-cells = <1>;
  232. macaddr_defaultmac_0: macaddr@0 {
  233. compatible = "mac-base";
  234. reg = <0x0 0x6>;
  235. #nvmem-cell-cells = <1>;
  236. };
  237. };
  238. };
  239. partition@fc0000 {
  240. label = "ART";
  241. reg = <0xfc0000 0x40000>;
  242. read-only;
  243. nvmem-layout {
  244. compatible = "fixed-layout";
  245. #address-cells = <1>;
  246. #size-cells = <1>;
  247. precal_ART_1000: precal@1000 {
  248. reg = <0x1000 0x2f20>;
  249. };
  250. precal_ART_5000: precal@5000 {
  251. reg = <0x5000 0x2f20>;
  252. };
  253. };
  254. };
  255. };
  256. };
  257. };
  258. };
  259. &hs_phy_0 {
  260. status = "okay";
  261. };
  262. &ss_phy_0 {
  263. status = "okay";
  264. };
  265. &usb3_0 {
  266. status = "okay";
  267. };
  268. &hs_phy_1 {
  269. status = "okay";
  270. };
  271. &ss_phy_1 {
  272. status = "okay";
  273. };
  274. &usb3_1 {
  275. status = "okay";
  276. };
  277. &pcie0 {
  278. status = "okay";
  279. bridge@0,0 {
  280. reg = <0x00000000 0 0 0 0>;
  281. #address-cells = <3>;
  282. #size-cells = <2>;
  283. ranges;
  284. wifi@1,0 {
  285. compatible = "pci168c,0040";
  286. reg = <0x00010000 0 0 0 0>;
  287. nvmem-cells = <&macaddr_defaultmac_0 (-1)>, <&precal_ART_1000>;
  288. nvmem-cell-names = "mac-address", "pre-calibration";
  289. };
  290. };
  291. };
  292. &pcie1 {
  293. status = "okay";
  294. max-link-speed = <1>;
  295. bridge@0,0 {
  296. reg = <0x00000000 0 0 0 0>;
  297. #address-cells = <3>;
  298. #size-cells = <2>;
  299. ranges;
  300. wifi@1,0 {
  301. compatible = "pci168c,0040";
  302. reg = <0x00010000 0 0 0 0>;
  303. nvmem-cells = <&macaddr_defaultmac_0 0>, <&precal_ART_5000>;
  304. nvmem-cell-names = "mac-address", "pre-calibration";
  305. };
  306. };
  307. };
  308. &mdio0 {
  309. status = "okay";
  310. pinctrl-0 = <&mdio0_pins>;
  311. pinctrl-names = "default";
  312. switch@10 {
  313. compatible = "qca,qca8337";
  314. #address-cells = <1>;
  315. #size-cells = <0>;
  316. reg = <0x10>;
  317. ports {
  318. #address-cells = <1>;
  319. #size-cells = <0>;
  320. port@0 {
  321. reg = <0>;
  322. label = "cpu";
  323. ethernet = <&gmac1>;
  324. phy-mode = "rgmii";
  325. tx-internal-delay-ps = <1000>;
  326. rx-internal-delay-ps = <1000>;
  327. fixed-link {
  328. speed = <1000>;
  329. full-duplex;
  330. };
  331. };
  332. port@1 {
  333. reg = <1>;
  334. label = "lan4";
  335. phy-mode = "internal";
  336. phy-handle = <&phy_port1>;
  337. };
  338. port@2 {
  339. reg = <2>;
  340. label = "lan3";
  341. phy-mode = "internal";
  342. phy-handle = <&phy_port2>;
  343. };
  344. port@3 {
  345. reg = <3>;
  346. label = "lan2";
  347. phy-mode = "internal";
  348. phy-handle = <&phy_port3>;
  349. };
  350. port@4 {
  351. reg = <4>;
  352. label = "lan1";
  353. phy-mode = "internal";
  354. phy-handle = <&phy_port4>;
  355. };
  356. port@5 {
  357. reg = <5>;
  358. label = "wan";
  359. phy-mode = "internal";
  360. phy-handle = <&phy_port5>;
  361. };
  362. port@6 {
  363. reg = <6>;
  364. label = "cpu";
  365. ethernet = <&gmac2>;
  366. phy-mode = "sgmii";
  367. qca,sgmii-enable-pll;
  368. fixed-link {
  369. speed = <1000>;
  370. full-duplex;
  371. };
  372. };
  373. };
  374. mdio {
  375. #address-cells = <1>;
  376. #size-cells = <0>;
  377. phy_port1: phy@0 {
  378. reg = <0>;
  379. };
  380. phy_port2: phy@1 {
  381. reg = <1>;
  382. };
  383. phy_port3: phy@2 {
  384. reg = <2>;
  385. };
  386. phy_port4: phy@3 {
  387. reg = <3>;
  388. };
  389. phy_port5: phy@4 {
  390. reg = <4>;
  391. };
  392. };
  393. };
  394. };
  395. &gmac1 {
  396. status = "okay";
  397. phy-mode = "rgmii";
  398. qcom,id = <1>;
  399. pinctrl-0 = <&rgmii2_pins>;
  400. pinctrl-names = "default";
  401. nvmem-cells = <&macaddr_defaultmac_0 1>;
  402. nvmem-cell-names = "mac-address";
  403. fixed-link {
  404. speed = <1000>;
  405. full-duplex;
  406. };
  407. };
  408. &gmac2 {
  409. status = "okay";
  410. phy-mode = "sgmii";
  411. qcom,id = <2>;
  412. nvmem-cells = <&macaddr_defaultmac_0 0>;
  413. nvmem-cell-names = "mac-address";
  414. fixed-link {
  415. speed = <1000>;
  416. full-duplex;
  417. };
  418. };
  419. &adm_dma {
  420. status = "okay";
  421. };