qcom-ipq8064-wxr-2533dhp.dts 10.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq8064-v2.0-smb208.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/leds/common.h>
  5. / {
  6. model = "Buffalo WXR-2533DHP";
  7. compatible = "buffalo,wxr-2533dhp", "qcom,ipq8064";
  8. memory@42000000 {
  9. reg = <0x42000000 0x1e000000>;
  10. device_type = "memory";
  11. };
  12. aliases {
  13. led-boot = &power;
  14. led-failsafe = &diag;
  15. led-running = &power;
  16. led-upgrade = &power;
  17. };
  18. chosen {
  19. /* use "ubi_rootfs" volume in "ubi" partition as rootfs */
  20. bootargs = "ubi.block=0,1 root=/dev/ubiblock0_1 rootfstype=squashfs";
  21. };
  22. leds {
  23. compatible = "gpio-leds";
  24. pinctrl-0 = <&led_pins>;
  25. pinctrl-names = "default";
  26. usb {
  27. function = LED_FUNCTION_USB;
  28. color = <LED_COLOR_ID_GREEN>;
  29. gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
  30. linux,default-trigger = "usbport";
  31. trigger-sources = <&hub_port0 &hub_port1>;
  32. };
  33. guestport {
  34. label = "green:guestport";
  35. gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
  36. };
  37. diag: diag {
  38. label = "orange:diag";
  39. gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
  40. };
  41. internet_orange {
  42. label = "orange:internet";
  43. gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
  44. };
  45. internet_white {
  46. label = "white:internet";
  47. gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
  48. };
  49. wireless_orange {
  50. label = "orange:wireless";
  51. gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
  52. };
  53. wireless_white {
  54. label = "white:wireless";
  55. gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
  56. };
  57. router_orange {
  58. label = "orange:router";
  59. gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
  60. };
  61. router_white {
  62. label = "white:router";
  63. gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
  64. };
  65. power: power {
  66. function = LED_FUNCTION_POWER;
  67. color = <LED_COLOR_ID_WHITE>;
  68. gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
  69. };
  70. };
  71. keys {
  72. compatible = "gpio-keys";
  73. pinctrl-0 = <&button_pins>;
  74. pinctrl-names = "default";
  75. power {
  76. label = "power";
  77. gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>;
  78. linux,code = <KEY_POWER>;
  79. debounce-interval = <60>;
  80. wakeup-source;
  81. };
  82. reset {
  83. label = "reset";
  84. gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  85. linux,code = <KEY_RESTART>;
  86. debounce-interval = <60>;
  87. wakeup-source;
  88. };
  89. wps {
  90. label = "wps";
  91. gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
  92. linux,code = <KEY_WPS_BUTTON>;
  93. debounce-interval = <60>;
  94. wakeup-source;
  95. };
  96. eject {
  97. label = "eject";
  98. gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
  99. linux,code = <KEY_EJECTCD>;
  100. debounce-interval = <60>;
  101. wakeup-source;
  102. };
  103. guest {
  104. label = "guest";
  105. gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
  106. linux,code = <BTN_0>;
  107. debounce-interval = <60>;
  108. wakeup-source;
  109. };
  110. ap {
  111. label = "ap";
  112. gpios = <&qcom_pinmux 55 GPIO_ACTIVE_LOW>;
  113. linux,code = <BTN_1>;
  114. linux,input-type = <EV_SW>;
  115. debounce-interval = <60>;
  116. wakeup-source;
  117. };
  118. router {
  119. label = "router";
  120. gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>;
  121. linux,code = <BTN_1>;
  122. linux,input-type = <EV_SW>;
  123. debounce-interval = <60>;
  124. wakeup-source;
  125. };
  126. auto {
  127. label = "auto";
  128. gpios = <&qcom_pinmux 57 GPIO_ACTIVE_LOW>;
  129. linux,code = <BTN_1>;
  130. linux,input-type = <EV_SW>;
  131. debounce-interval = <60>;
  132. wakeup-source;
  133. };
  134. };
  135. };
  136. &nand {
  137. status = "okay";
  138. cs@0 {
  139. reg = <0>;
  140. compatible = "qcom,nandcs";
  141. nand-ecc-strength = <4>;
  142. nand-bus-width = <8>;
  143. nand-ecc-step-size = <512>;
  144. partitions {
  145. compatible = "fixed-partitions";
  146. #address-cells = <1>;
  147. #size-cells = <1>;
  148. ubi@0 {
  149. label = "ubi";
  150. reg = <0x0000000 0x4000000>;
  151. };
  152. rootfs_1@4000000 {
  153. label = "rootfs_1";
  154. reg = <0x4000000 0x4000000>;
  155. };
  156. };
  157. };
  158. };
  159. &adm_dma {
  160. status = "okay";
  161. };
  162. &mdio0 {
  163. status = "okay";
  164. pinctrl-0 = <&mdio0_pins>;
  165. pinctrl-names = "default";
  166. switch@10 {
  167. compatible = "qca,qca8337";
  168. #address-cells = <1>;
  169. #size-cells = <0>;
  170. reg = <0x10>;
  171. ports {
  172. #address-cells = <1>;
  173. #size-cells = <0>;
  174. port@0 {
  175. reg = <0>;
  176. label = "cpu";
  177. ethernet = <&gmac1>;
  178. phy-mode = "rgmii";
  179. tx-internal-delay-ps = <1000>;
  180. rx-internal-delay-ps = <1000>;
  181. fixed-link {
  182. speed = <1000>;
  183. full-duplex;
  184. };
  185. };
  186. port@1 {
  187. reg = <1>;
  188. label = "lan1";
  189. phy-mode = "internal";
  190. phy-handle = <&phy_port1>;
  191. };
  192. port@2 {
  193. reg = <2>;
  194. label = "lan2";
  195. phy-mode = "internal";
  196. phy-handle = <&phy_port2>;
  197. };
  198. port@3 {
  199. reg = <3>;
  200. label = "lan3";
  201. phy-mode = "internal";
  202. phy-handle = <&phy_port3>;
  203. };
  204. port@4 {
  205. reg = <4>;
  206. label = "lan4";
  207. phy-mode = "internal";
  208. phy-handle = <&phy_port4>;
  209. };
  210. port@5 {
  211. reg = <5>;
  212. label = "wan";
  213. phy-mode = "internal";
  214. phy-handle = <&phy_port5>;
  215. };
  216. port@6 {
  217. reg = <6>;
  218. label = "cpu";
  219. ethernet = <&gmac2>;
  220. phy-mode = "sgmii";
  221. qca,sgmii-enable-pll;
  222. fixed-link {
  223. speed = <1000>;
  224. full-duplex;
  225. };
  226. };
  227. };
  228. mdio {
  229. #address-cells = <1>;
  230. #size-cells = <0>;
  231. phy_port1: phy@0 {
  232. reg = <0>;
  233. };
  234. phy_port2: phy@1 {
  235. reg = <1>;
  236. };
  237. phy_port3: phy@2 {
  238. reg = <2>;
  239. };
  240. phy_port4: phy@3 {
  241. reg = <3>;
  242. };
  243. phy_port5: phy@4 {
  244. reg = <4>;
  245. };
  246. };
  247. };
  248. };
  249. &gmac1 {
  250. status = "okay";
  251. phy-mode = "rgmii";
  252. qcom,id = <1>;
  253. pinctrl-0 = <&rgmii2_pins>;
  254. pinctrl-names = "default";
  255. nvmem-cells = <&macaddr_ART_6>;
  256. nvmem-cell-names = "mac-address";
  257. fixed-link {
  258. speed = <1000>;
  259. full-duplex;
  260. };
  261. };
  262. &gmac2 {
  263. status = "okay";
  264. phy-mode = "sgmii";
  265. qcom,id = <2>;
  266. nvmem-cells = <&macaddr_ART_0>;
  267. nvmem-cell-names = "mac-address";
  268. fixed-link {
  269. speed = <1000>;
  270. full-duplex;
  271. };
  272. };
  273. &gsbi4_serial {
  274. pinctrl-0 = <&uart0_pins>;
  275. pinctrl-names = "default";
  276. };
  277. &gsbi5 {
  278. status = "okay";
  279. qcom,mode = <GSBI_PROT_SPI>;
  280. spi@1a280000 {
  281. status = "okay";
  282. pinctrl-0 = <&spi_pins>;
  283. pinctrl-names = "default";
  284. cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
  285. flash@0 {
  286. compatible = "jedec,spi-nor";
  287. spi-max-frequency = <50000000>;
  288. reg = <0>;
  289. partitions {
  290. compatible = "fixed-partitions";
  291. #address-cells = <1>;
  292. #size-cells = <1>;
  293. SBL1@0 {
  294. label = "SBL1";
  295. reg = <0x0 0x10000>;
  296. read-only;
  297. };
  298. MIBIB@10000 {
  299. label = "MIBIB";
  300. reg = <0x10000 0x20000>;
  301. read-only;
  302. };
  303. SBL2@30000 {
  304. label = "SBL2";
  305. reg = <0x30000 0x30000>;
  306. read-only;
  307. };
  308. SBL3@60000 {
  309. label = "SBL3";
  310. reg = <0x60000 0x30000>;
  311. read-only;
  312. };
  313. DDRCONFIG@90000 {
  314. label = "DDRCONFIG";
  315. reg = <0x90000 0x10000>;
  316. read-only;
  317. };
  318. SSD@a0000 {
  319. label = "SSD";
  320. reg = <0xa0000 0x10000>;
  321. read-only;
  322. };
  323. TZ@b0000 {
  324. label = "TZ";
  325. reg = <0xb0000 0x30000>;
  326. read-only;
  327. };
  328. RPM@e0000 {
  329. label = "RPM";
  330. reg = <0xe0000 0x20000>;
  331. read-only;
  332. };
  333. APPSBL@100000 {
  334. label = "APPSBL";
  335. reg = <0x100000 0x70000>;
  336. read-only;
  337. };
  338. APPSBLENV@170000 {
  339. label = "APPSBLENV";
  340. reg = <0x170000 0x10000>;
  341. read-only;
  342. };
  343. ART@180000 {
  344. label = "ART";
  345. reg = <0x180000 0x40000>;
  346. read-only;
  347. nvmem-layout {
  348. compatible = "fixed-layout";
  349. #address-cells = <1>;
  350. #size-cells = <1>;
  351. macaddr_ART_0: macaddr@0 {
  352. reg = <0x0 0x6>;
  353. };
  354. macaddr_ART_6: macaddr@6 {
  355. reg = <0x6 0x6>;
  356. };
  357. macaddr_ART_18: macaddr@18 {
  358. reg = <0x18 0x6>;
  359. };
  360. macaddr_ART_1e: macaddr@1e {
  361. reg = <0x1e 0x6>;
  362. };
  363. precal_ART_1000: precal@1000 {
  364. reg = <0x1000 0x2f20>;
  365. };
  366. precal_ART_5000: precal@5000 {
  367. reg = <0x5000 0x2f20>;
  368. };
  369. };
  370. };
  371. BOOTCONFIG@1c0000 {
  372. label = "BOOTCONFIG";
  373. reg = <0x1c0000 0x10000>;
  374. read-only;
  375. };
  376. APPSBL_1@1d0000 {
  377. label = "APPSBL_1";
  378. reg = <0x1d0000 0x70000>;
  379. read-only;
  380. };
  381. };
  382. };
  383. };
  384. };
  385. &hs_phy_0 {
  386. status = "okay";
  387. };
  388. &ss_phy_0 {
  389. status = "okay";
  390. };
  391. &usb3_0 {
  392. status = "okay";
  393. pinctrl-0 = <&usb_pwr_en_pins>;
  394. pinctrl-names = "default";
  395. };
  396. &hs_phy_1 {
  397. status = "okay";
  398. };
  399. &ss_phy_1 {
  400. status = "okay";
  401. };
  402. &usb3_1 {
  403. status = "okay";
  404. };
  405. &dwc3_0 {
  406. #address-cells = <1>;
  407. #size-cells = <0>;
  408. hub_port0: port@1 {
  409. reg = <1>;
  410. #trigger-source-cells = <0>;
  411. };
  412. };
  413. &dwc3_1 {
  414. #address-cells = <1>;
  415. #size-cells = <0>;
  416. hub_port1: port@1 {
  417. reg = <1>;
  418. #trigger-source-cells = <0>;
  419. };
  420. };
  421. &pcie0 {
  422. status = "okay";
  423. bridge@0,0 {
  424. reg = <0x00000000 0 0 0 0>;
  425. #address-cells = <3>;
  426. #size-cells = <2>;
  427. ranges;
  428. wifi@1,0 {
  429. compatible = "pci168c,0040";
  430. reg = <0x00010000 0 0 0 0>;
  431. nvmem-cells = <&macaddr_ART_1e>, <&precal_ART_1000>;
  432. nvmem-cell-names = "mac-address", "pre-calibration";
  433. };
  434. };
  435. };
  436. &pcie1 {
  437. status = "okay";
  438. max-link-speed = <1>;
  439. bridge@0,0 {
  440. reg = <0x00000000 0 0 0 0>;
  441. #address-cells = <3>;
  442. #size-cells = <2>;
  443. ranges;
  444. wifi@1,0 {
  445. compatible = "pci168c,0040";
  446. reg = <0x00010000 0 0 0 0>;
  447. nvmem-cells = <&macaddr_ART_18>, <&precal_ART_5000>;
  448. nvmem-cell-names = "mac-address", "pre-calibration";
  449. };
  450. };
  451. };
  452. &qcom_pinmux {
  453. button_pins: button_pins {
  454. mux {
  455. pins = "gpio6", "gpio54", "gpio55", "gpio56", "gpio57",
  456. "gpio58", "gpio64", "gpio65";
  457. function = "gpio";
  458. drive-strength = <2>;
  459. bias-pull-up;
  460. };
  461. };
  462. led_pins: led_pins {
  463. mux {
  464. pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio22",
  465. "gpio23", "gpio24", "gpio25", "gpio26", "gpio53";
  466. function = "gpio";
  467. drive-strength = <2>;
  468. bias-pull-up;
  469. };
  470. };
  471. uart0_pins: uart0_pins {
  472. mux {
  473. pins = "gpio10", "gpio11";
  474. function = "gsbi4";
  475. drive-strength = <12>;
  476. bias-disable;
  477. };
  478. };
  479. spi_pins: spi_pins {
  480. mux {
  481. pins = "gpio18", "gpio19", "gpio21";
  482. function = "gsbi5";
  483. bias-pull-down;
  484. };
  485. data {
  486. pins = "gpio18", "gpio19";
  487. drive-strength = <10>;
  488. };
  489. cs{
  490. pins = "gpio20";
  491. drive-strength = <10>;
  492. bias-pull-up;
  493. };
  494. clk {
  495. pins = "gpio21";
  496. drive-strength = <12>;
  497. };
  498. };
  499. usb_pwr_en_pins: usb_pwr_en_pins {
  500. mux{
  501. pins = "gpio68";
  502. function = "gpio";
  503. drive-strength = <2>;
  504. bias-pull-up;
  505. output-high;
  506. };
  507. };
  508. };