qcom-ipq8064-d7800.dts 7.8 KB

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  1. #include "qcom-ipq8064-v2.0-smb208.dtsi"
  2. #include <dt-bindings/input/input.h>
  3. #include <dt-bindings/leds/common.h>
  4. / {
  5. model = "Netgear Nighthawk X4 D7800";
  6. compatible = "netgear,d7800", "qcom,ipq8064";
  7. memory@0 {
  8. reg = <0x42000000 0x1e000000>;
  9. device_type = "memory";
  10. };
  11. reserved-memory {
  12. rsvd@5fe00000 {
  13. reg = <0x5fe00000 0x200000>;
  14. reusable;
  15. };
  16. };
  17. aliases {
  18. mdio-gpio0 = &mdio0;
  19. led-boot = &power_white;
  20. led-failsafe = &power_amber;
  21. led-running = &power_white;
  22. led-upgrade = &power_amber;
  23. };
  24. chosen {
  25. bootargs = "rootfstype=squashfs noinitrd";
  26. };
  27. keys {
  28. compatible = "gpio-keys";
  29. pinctrl-0 = <&button_pins>;
  30. pinctrl-names = "default";
  31. wifi {
  32. label = "wifi";
  33. gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
  34. linux,code = <KEY_RFKILL>;
  35. debounce-interval = <60>;
  36. wakeup-source;
  37. };
  38. reset {
  39. label = "reset";
  40. gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  41. linux,code = <KEY_RESTART>;
  42. debounce-interval = <60>;
  43. wakeup-source;
  44. };
  45. wps {
  46. label = "wps";
  47. gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
  48. linux,code = <KEY_WPS_BUTTON>;
  49. debounce-interval = <60>;
  50. wakeup-source;
  51. };
  52. };
  53. leds {
  54. compatible = "gpio-leds";
  55. pinctrl-0 = <&led_pins>;
  56. pinctrl-names = "default";
  57. usb1 {
  58. label = "white:usb1";
  59. gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
  60. };
  61. usb2 {
  62. label = "white:usb2";
  63. gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
  64. };
  65. power_amber: power_amber {
  66. function = LED_FUNCTION_POWER;
  67. color = <LED_COLOR_ID_AMBER>;
  68. gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
  69. };
  70. wan_white {
  71. function = LED_FUNCTION_WAN;
  72. color = <LED_COLOR_ID_WHITE>;
  73. gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
  74. };
  75. wan_amber {
  76. function = LED_FUNCTION_WAN;
  77. color = <LED_COLOR_ID_AMBER>;
  78. gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
  79. };
  80. wps {
  81. function = LED_FUNCTION_WPS;
  82. color = <LED_COLOR_ID_WHITE>;
  83. gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
  84. };
  85. esata {
  86. label = "white:esata";
  87. gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
  88. };
  89. power_white: power_white {
  90. function = LED_FUNCTION_POWER;
  91. color = <LED_COLOR_ID_WHITE>;
  92. gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
  93. default-state = "keep";
  94. };
  95. wifi {
  96. label = "white:wifi";
  97. gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
  98. };
  99. };
  100. };
  101. &qcom_pinmux {
  102. button_pins: button_pins {
  103. mux {
  104. pins = "gpio6", "gpio54", "gpio65";
  105. function = "gpio";
  106. drive-strength = <2>;
  107. bias-pull-up;
  108. };
  109. };
  110. led_pins: led_pins {
  111. mux {
  112. pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
  113. "gpio24","gpio26", "gpio53", "gpio64";
  114. function = "gpio";
  115. drive-strength = <2>;
  116. bias-pull-up;
  117. };
  118. };
  119. usb0_pwr_en_pins: usb0_pwr_en_pins {
  120. mux {
  121. pins = "gpio15";
  122. function = "gpio";
  123. drive-strength = <12>;
  124. bias-pull-down;
  125. output-high;
  126. };
  127. };
  128. usb1_pwr_en_pins: usb1_pwr_en_pins {
  129. mux {
  130. pins = "gpio16", "gpio68";
  131. function = "gpio";
  132. drive-strength = <12>;
  133. bias-pull-down;
  134. output-high;
  135. };
  136. };
  137. };
  138. &sata_phy {
  139. status = "okay";
  140. };
  141. &sata {
  142. status = "okay";
  143. };
  144. &hs_phy_0 {
  145. status = "okay";
  146. };
  147. &ss_phy_0 {
  148. status = "okay";
  149. };
  150. &usb3_0 {
  151. status = "okay";
  152. pinctrl-0 = <&usb0_pwr_en_pins>;
  153. pinctrl-names = "default";
  154. };
  155. &hs_phy_1 {
  156. status = "okay";
  157. };
  158. &ss_phy_1 {
  159. status = "okay";
  160. };
  161. &usb3_1 {
  162. status = "okay";
  163. pinctrl-0 = <&usb1_pwr_en_pins>;
  164. pinctrl-names = "default";
  165. };
  166. &pcie0 {
  167. status = "okay";
  168. reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
  169. pinctrl-0 = <&pcie0_pins>;
  170. pinctrl-names = "default";
  171. bridge@0,0 {
  172. reg = <0x00000000 0 0 0 0>;
  173. #address-cells = <3>;
  174. #size-cells = <2>;
  175. ranges;
  176. wifi@1,0 {
  177. compatible = "pci168c,0040";
  178. reg = <0x00010000 0 0 0 0>;
  179. nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>;
  180. nvmem-cell-names = "mac-address", "pre-calibration";
  181. };
  182. };
  183. };
  184. &pcie1 {
  185. status = "okay";
  186. reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
  187. pinctrl-0 = <&pcie1_pins>;
  188. pinctrl-names = "default";
  189. max-link-speed = <1>;
  190. bridge@0,0 {
  191. reg = <0x00000000 0 0 0 0>;
  192. #address-cells = <3>;
  193. #size-cells = <2>;
  194. ranges;
  195. wifi@1,0 {
  196. compatible = "pci168c,0040";
  197. reg = <0x00010000 0 0 0 0>;
  198. nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>;
  199. nvmem-cell-names = "mac-address", "pre-calibration";
  200. };
  201. };
  202. };
  203. &pcie2 {
  204. status = "okay";
  205. reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
  206. pinctrl-0 = <&pcie2_pins>;
  207. pinctrl-names = "default";
  208. };
  209. &nand {
  210. status = "okay";
  211. nand@0 {
  212. reg = <0>;
  213. compatible = "qcom,nandcs";
  214. nand-ecc-strength = <4>;
  215. nand-bus-width = <8>;
  216. nand-ecc-step-size = <512>;
  217. nand-is-boot-medium;
  218. qcom,boot-partitions = <0x0 0x1180000>;
  219. partitions {
  220. compatible = "fixed-partitions";
  221. #address-cells = <1>;
  222. #size-cells = <1>;
  223. qcadata@0 {
  224. label = "qcadata";
  225. reg = <0x0000000 0x0c80000>;
  226. read-only;
  227. };
  228. APPSBL@c80000 {
  229. label = "APPSBL";
  230. reg = <0x0c80000 0x0500000>;
  231. read-only;
  232. };
  233. APPSBLENV@1180000 {
  234. label = "APPSBLENV";
  235. reg = <0x1180000 0x0080000>;
  236. read-only;
  237. };
  238. art@1200000 {
  239. label = "art";
  240. reg = <0x1200000 0x0140000>;
  241. read-only;
  242. nvmem-layout {
  243. compatible = "fixed-layout";
  244. #address-cells = <1>;
  245. #size-cells = <1>;
  246. macaddr_art_0: macaddr@0 {
  247. reg = <0x0 0x6>;
  248. };
  249. macaddr_art_6: macaddr@6 {
  250. compatible = "mac-base";
  251. reg = <0x6 0x6>;
  252. #nvmem-cell-cells = <1>;
  253. };
  254. precal_art_1000: precal@1000 {
  255. reg = <0x1000 0x2f20>;
  256. };
  257. precal_art_5000: precal@5000 {
  258. reg = <0x5000 0x2f20>;
  259. };
  260. };
  261. };
  262. artbak: art@1340000 {
  263. label = "artbak";
  264. reg = <0x1340000 0x0140000>;
  265. read-only;
  266. };
  267. kernel@1480000 {
  268. label = "kernel";
  269. reg = <0x1480000 0x0400000>;
  270. };
  271. ubi@1880000 {
  272. label = "ubi";
  273. reg = <0x1880000 0x6080000>;
  274. };
  275. reserve@7900000 {
  276. label = "reserve";
  277. reg = <0x7900000 0x0700000>;
  278. read-only;
  279. };
  280. };
  281. };
  282. };
  283. &mdio0 {
  284. status = "okay";
  285. pinctrl-0 = <&mdio0_pins>;
  286. pinctrl-names = "default";
  287. switch@10 {
  288. compatible = "qca,qca8337";
  289. #address-cells = <1>;
  290. #size-cells = <0>;
  291. reg = <0x10>;
  292. ports {
  293. #address-cells = <1>;
  294. #size-cells = <0>;
  295. port@0 {
  296. reg = <0>;
  297. label = "cpu";
  298. ethernet = <&gmac1>;
  299. phy-mode = "rgmii";
  300. tx-internal-delay-ps = <1000>;
  301. rx-internal-delay-ps = <1000>;
  302. fixed-link {
  303. speed = <1000>;
  304. full-duplex;
  305. };
  306. };
  307. port@1 {
  308. reg = <1>;
  309. label = "lan1";
  310. phy-mode = "internal";
  311. phy-handle = <&phy_port1>;
  312. };
  313. port@2 {
  314. reg = <2>;
  315. label = "lan2";
  316. phy-mode = "internal";
  317. phy-handle = <&phy_port2>;
  318. };
  319. port@3 {
  320. reg = <3>;
  321. label = "lan3";
  322. phy-mode = "internal";
  323. phy-handle = <&phy_port3>;
  324. };
  325. port@4 {
  326. reg = <4>;
  327. label = "lan4";
  328. phy-mode = "internal";
  329. phy-handle = <&phy_port4>;
  330. };
  331. port@5 {
  332. reg = <5>;
  333. label = "wan";
  334. phy-mode = "internal";
  335. phy-handle = <&phy_port5>;
  336. };
  337. port@6 {
  338. reg = <6>;
  339. label = "cpu";
  340. ethernet = <&gmac2>;
  341. phy-mode = "sgmii";
  342. qca,sgmii-enable-pll;
  343. fixed-link {
  344. speed = <1000>;
  345. full-duplex;
  346. };
  347. };
  348. };
  349. mdio {
  350. #address-cells = <1>;
  351. #size-cells = <0>;
  352. phy_port1: phy@0 {
  353. reg = <0>;
  354. };
  355. phy_port2: phy@1 {
  356. reg = <1>;
  357. };
  358. phy_port3: phy@2 {
  359. reg = <2>;
  360. };
  361. phy_port4: phy@3 {
  362. reg = <3>;
  363. };
  364. phy_port5: phy@4 {
  365. reg = <4>;
  366. };
  367. };
  368. };
  369. };
  370. &gmac1 {
  371. status = "okay";
  372. phy-mode = "rgmii";
  373. qcom,id = <1>;
  374. pinctrl-0 = <&rgmii2_pins>;
  375. pinctrl-names = "default";
  376. nvmem-cells = <&macaddr_art_6 0>;
  377. nvmem-cell-names = "mac-address";
  378. fixed-link {
  379. speed = <1000>;
  380. full-duplex;
  381. };
  382. };
  383. &gmac2 {
  384. status = "okay";
  385. phy-mode = "sgmii";
  386. qcom,id = <2>;
  387. nvmem-cells = <&macaddr_art_0>;
  388. nvmem-cell-names = "mac-address";
  389. fixed-link {
  390. speed = <1000>;
  391. full-duplex;
  392. };
  393. };
  394. &adm_dma {
  395. status = "okay";
  396. };