qcom-ipq8064-eax500.dtsi 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq8064-v2.0-smb208.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. / {
  5. chosen {
  6. bootargs = "console=ttyMSM0,115200n8";
  7. /* append to bootargs adding the root deviceblock nbr from bootloader */
  8. append-rootblock = "ubi.mtd=";
  9. };
  10. };
  11. &qcom_pinmux {
  12. /* eax500 routers reuse the pcie2 reset pin for switch reset pin */
  13. switch_reset: switch_reset_pins {
  14. mux {
  15. pins = "gpio63";
  16. function = "gpio";
  17. drive-strength = <12>;
  18. bias-pull-up;
  19. };
  20. };
  21. };
  22. &hs_phy_0 {
  23. status = "okay";
  24. };
  25. &ss_phy_0 {
  26. status = "okay";
  27. };
  28. &usb3_0 {
  29. status = "okay";
  30. };
  31. &hs_phy_1 {
  32. status = "okay";
  33. };
  34. &ss_phy_1 {
  35. status = "okay";
  36. };
  37. &usb3_1 {
  38. status = "okay";
  39. };
  40. &pcie0 {
  41. status = "okay";
  42. max-link-speed = <1>;
  43. };
  44. &pcie1 {
  45. status = "okay";
  46. };
  47. &nand {
  48. status = "okay";
  49. nand@0 {
  50. reg = <0>;
  51. compatible = "qcom,nandcs";
  52. nand-ecc-strength = <4>;
  53. nand-bus-width = <8>;
  54. nand-ecc-step-size = <512>;
  55. nand-is-boot-medium;
  56. qcom,boot-partitions = <0x0 0x0c80000>;
  57. partitions: partitions {
  58. compatible = "fixed-partitions";
  59. #address-cells = <1>;
  60. #size-cells = <1>;
  61. partition@0 {
  62. label = "SBL1";
  63. reg = <0x0000000 0x0040000>;
  64. read-only;
  65. };
  66. partition@40000 {
  67. label = "MIBIB";
  68. reg = <0x0040000 0x0140000>;
  69. read-only;
  70. };
  71. partition@180000 {
  72. label = "SBL2";
  73. reg = <0x0180000 0x0140000>;
  74. read-only;
  75. };
  76. partition@2c0000 {
  77. label = "SBL3";
  78. reg = <0x02c0000 0x0280000>;
  79. read-only;
  80. };
  81. partition@540000 {
  82. label = "DDRCONFIG";
  83. reg = <0x0540000 0x0120000>;
  84. read-only;
  85. };
  86. partition@660000 {
  87. label = "SSD";
  88. reg = <0x0660000 0x0120000>;
  89. read-only;
  90. };
  91. partition@780000 {
  92. label = "TZ";
  93. reg = <0x0780000 0x0280000>;
  94. read-only;
  95. };
  96. partition@a00000 {
  97. label = "RPM";
  98. reg = <0x0a00000 0x0280000>;
  99. read-only;
  100. };
  101. art: partition@c80000 {
  102. label = "art";
  103. reg = <0x0c80000 0x0140000>;
  104. read-only;
  105. };
  106. partition@dc0000 {
  107. label = "APPSBL";
  108. reg = <0x0dc0000 0x0100000>;
  109. read-only;
  110. };
  111. partition@ec0000 {
  112. label = "u_env";
  113. reg = <0x0ec0000 0x0040000>;
  114. };
  115. partition@f00000 {
  116. label = "s_env";
  117. reg = <0x0f00000 0x0040000>;
  118. };
  119. partition@f40000 {
  120. label = "devinfo";
  121. reg = <0x0f40000 0x0040000>;
  122. };
  123. partition@f80000 {
  124. label = "kernel1";
  125. reg = <0x0f80000 0x2800000>; /* 4 MB, spill to rootfs */
  126. };
  127. partition@1380000 {
  128. label = "rootfs1";
  129. reg = <0x1380000 0x2400000>;
  130. };
  131. partition@3780000 {
  132. label = "kernel2";
  133. reg = <0x3780000 0x2800000>;
  134. };
  135. partition@3b80000 {
  136. label = "rootfs2";
  137. reg = <0x3b80000 0x2400000>;
  138. };
  139. };
  140. };
  141. };
  142. &mdio0 {
  143. status = "okay";
  144. pinctrl-0 = <&mdio0_pins>;
  145. pinctrl-names = "default";
  146. /* Switch from documentation require at least 10ms for reset */
  147. reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
  148. reset-post-delay-us = <12000>;
  149. switch@10 {
  150. compatible = "qca,qca8337";
  151. #address-cells = <1>;
  152. #size-cells = <0>;
  153. reg = <0x10>;
  154. ports {
  155. #address-cells = <1>;
  156. #size-cells = <0>;
  157. port@0 {
  158. reg = <0>;
  159. label = "cpu";
  160. ethernet = <&gmac1>;
  161. phy-mode = "rgmii";
  162. tx-internal-delay-ps = <1000>;
  163. rx-internal-delay-ps = <1000>;
  164. fixed-link {
  165. speed = <1000>;
  166. full-duplex;
  167. };
  168. };
  169. port@1 {
  170. reg = <1>;
  171. label = "lan1";
  172. phy-mode = "internal";
  173. phy-handle = <&phy_port1>;
  174. };
  175. port@2 {
  176. reg = <2>;
  177. label = "lan2";
  178. phy-mode = "internal";
  179. phy-handle = <&phy_port2>;
  180. };
  181. port@3 {
  182. reg = <3>;
  183. label = "lan3";
  184. phy-mode = "internal";
  185. phy-handle = <&phy_port3>;
  186. };
  187. port@4 {
  188. reg = <4>;
  189. label = "lan4";
  190. phy-mode = "internal";
  191. phy-handle = <&phy_port4>;
  192. };
  193. port@5 {
  194. reg = <5>;
  195. label = "wan";
  196. phy-mode = "internal";
  197. phy-handle = <&phy_port5>;
  198. };
  199. port@6 {
  200. reg = <6>;
  201. label = "cpu";
  202. ethernet = <&gmac2>;
  203. phy-mode = "sgmii";
  204. qca,sgmii-enable-pll;
  205. fixed-link {
  206. speed = <1000>;
  207. full-duplex;
  208. };
  209. };
  210. };
  211. mdio {
  212. #address-cells = <1>;
  213. #size-cells = <0>;
  214. phy_port1: phy@0 {
  215. reg = <0>;
  216. };
  217. phy_port2: phy@1 {
  218. reg = <1>;
  219. };
  220. phy_port3: phy@2 {
  221. reg = <2>;
  222. };
  223. phy_port4: phy@3 {
  224. reg = <3>;
  225. };
  226. phy_port5: phy@4 {
  227. reg = <4>;
  228. };
  229. };
  230. };
  231. };
  232. &gmac1 {
  233. status = "okay";
  234. phy-mode = "rgmii";
  235. qcom,id = <1>;
  236. pinctrl-0 = <&rgmii2_pins>;
  237. pinctrl-names = "default";
  238. fixed-link {
  239. speed = <1000>;
  240. full-duplex;
  241. };
  242. };
  243. &gmac2 {
  244. status = "okay";
  245. phy-mode = "sgmii";
  246. qcom,id = <2>;
  247. fixed-link {
  248. speed = <1000>;
  249. full-duplex;
  250. };
  251. };
  252. &adm_dma {
  253. status = "okay";
  254. };