qcom-ipq8064-wg2600hp.dts 8.8 KB

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  1. #include "qcom-ipq8064-v2.0-smb208.dtsi"
  2. #include <dt-bindings/input/input.h>
  3. #include <dt-bindings/leds/common.h>
  4. / {
  5. model = "NEC Aterm WG2600HP";
  6. compatible = "nec,wg2600hp", "qcom,ipq8064";
  7. memory@0 {
  8. reg = <0x42000000 0x1e000000>;
  9. device_type = "memory";
  10. };
  11. aliases {
  12. mdio-gpio0 = &mdio0;
  13. led-boot = &power_green;
  14. led-failsafe = &power_red;
  15. led-running = &power_green;
  16. led-upgrade = &power_green;
  17. };
  18. keys {
  19. compatible = "gpio-keys";
  20. pinctrl-0 = <&button_pins>;
  21. pinctrl-names = "default";
  22. wps {
  23. label = "wps";
  24. gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
  25. linux,code = <KEY_WPS_BUTTON>;
  26. debounce-interval = <60>;
  27. wakeup-source;
  28. };
  29. reset {
  30. label = "reset";
  31. gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  32. linux,code = <KEY_RESTART>;
  33. debounce-interval = <60>;
  34. wakeup-source;
  35. };
  36. bridge {
  37. label = "bridge";
  38. gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
  39. linux,code = <BTN_0>;
  40. linux,input-type = <EV_SW>;
  41. debounce-interval = <60>;
  42. wakeup-source;
  43. };
  44. converter {
  45. label = "converter";
  46. gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
  47. linux,code = <BTN_0>;
  48. linux,input-type = <EV_SW>;
  49. debounce-interval = <60>;
  50. wakeup-source;
  51. };
  52. };
  53. leds {
  54. compatible = "gpio-leds";
  55. pinctrl-0 = <&led_pins>;
  56. pinctrl-names = "default";
  57. converter_green {
  58. label = "green:converter";
  59. gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>;
  60. };
  61. power_red: power_red {
  62. function = LED_FUNCTION_POWER;
  63. color = <LED_COLOR_ID_RED>;
  64. gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
  65. };
  66. active_green {
  67. label = "green:active";
  68. gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
  69. };
  70. active_red {
  71. label = "red:active";
  72. gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
  73. };
  74. power_green: power_green {
  75. function = LED_FUNCTION_POWER;
  76. color = <LED_COLOR_ID_GREEN>;
  77. gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;
  78. };
  79. converter_red {
  80. label = "red:converter";
  81. gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
  82. };
  83. wlan2g_green {
  84. label = "green:wlan2g";
  85. gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
  86. };
  87. wlan2g_red {
  88. label = "red:wlan2g";
  89. gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
  90. };
  91. wlan5g_green {
  92. label = "green:wlan5g";
  93. gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
  94. };
  95. wlan5g_red {
  96. label = "red:wlan5g";
  97. gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>;
  98. };
  99. tv_green {
  100. label = "green:tv";
  101. gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
  102. };
  103. tv_red {
  104. label = "red:tv";
  105. gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>;
  106. };
  107. };
  108. };
  109. &CPU_SPC {
  110. status = "disabled";
  111. };
  112. &adm_dma {
  113. status = "okay";
  114. };
  115. &mdio0 {
  116. status = "okay";
  117. pinctrl-0 = <&mdio0_pins>;
  118. pinctrl-names = "default";
  119. switch@10 {
  120. compatible = "qca,qca8337";
  121. #address-cells = <1>;
  122. #size-cells = <0>;
  123. reg = <0x10>;
  124. ports {
  125. #address-cells = <1>;
  126. #size-cells = <0>;
  127. port@0 {
  128. reg = <0>;
  129. label = "cpu";
  130. ethernet = <&gmac1>;
  131. phy-mode = "rgmii";
  132. tx-internal-delay-ps = <1000>;
  133. fixed-link {
  134. speed = <1000>;
  135. full-duplex;
  136. };
  137. };
  138. port@1 {
  139. reg = <1>;
  140. label = "wan";
  141. phy-mode = "internal";
  142. phy-handle = <&phy_port1>;
  143. };
  144. port@2 {
  145. reg = <2>;
  146. label = "lan1";
  147. phy-mode = "internal";
  148. phy-handle = <&phy_port2>;
  149. };
  150. port@3 {
  151. reg = <3>;
  152. label = "lan2";
  153. phy-mode = "internal";
  154. phy-handle = <&phy_port3>;
  155. };
  156. port@4 {
  157. reg = <4>;
  158. label = "lan3";
  159. phy-mode = "internal";
  160. phy-handle = <&phy_port4>;
  161. };
  162. port@5 {
  163. reg = <5>;
  164. label = "lan4";
  165. phy-mode = "internal";
  166. phy-handle = <&phy_port5>;
  167. };
  168. port@6 {
  169. reg = <6>;
  170. label = "cpu";
  171. ethernet = <&gmac2>;
  172. phy-mode = "sgmii";
  173. qca,sgmii-enable-pll;
  174. qca,sgmii-rxclk-falling-edge;
  175. fixed-link {
  176. speed = <1000>;
  177. full-duplex;
  178. };
  179. };
  180. };
  181. mdio {
  182. #address-cells = <1>;
  183. #size-cells = <0>;
  184. phy_port1: phy@0 {
  185. reg = <0>;
  186. };
  187. phy_port2: phy@1 {
  188. reg = <1>;
  189. };
  190. phy_port3: phy@2 {
  191. reg = <2>;
  192. };
  193. phy_port4: phy@3 {
  194. reg = <3>;
  195. };
  196. phy_port5: phy@4 {
  197. reg = <4>;
  198. };
  199. };
  200. };
  201. };
  202. &gmac1 {
  203. status = "okay";
  204. phy-mode = "rgmii";
  205. qcom,id = <1>;
  206. pinctrl-0 = <&rgmii2_pins>;
  207. pinctrl-names = "default";
  208. nvmem-cells = <&macaddr_PRODUCTDATA_6>;
  209. nvmem-cell-names = "mac-address";
  210. fixed-link {
  211. speed = <1000>;
  212. full-duplex;
  213. };
  214. };
  215. &gmac2 {
  216. status = "okay";
  217. phy-mode = "sgmii";
  218. qcom,id = <2>;
  219. nvmem-cells = <&macaddr_PRODUCTDATA_0>;
  220. nvmem-cell-names = "mac-address";
  221. fixed-link {
  222. speed = <1000>;
  223. full-duplex;
  224. };
  225. };
  226. &gsbi5 {
  227. status = "okay";
  228. qcom,mode = <GSBI_PROT_SPI>;
  229. spi@1a280000 {
  230. status = "okay";
  231. pinctrl-0 = <&spi_pins>;
  232. pinctrl-names = "default";
  233. cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
  234. flash@0 {
  235. compatible = "jedec,spi-nor";
  236. spi-max-frequency = <50000000>;
  237. reg = <0>;
  238. partitions {
  239. compatible = "fixed-partitions";
  240. #address-cells = <1>;
  241. #size-cells = <1>;
  242. SBL1@0 {
  243. label = "SBL1";
  244. reg = <0x0 0x20000>;
  245. read-only;
  246. };
  247. MIBIB@20000 {
  248. label = "MIBIB";
  249. reg = <0x20000 0x20000>;
  250. read-only;
  251. };
  252. SBL2@40000 {
  253. label = "SBL2";
  254. reg = <0x40000 0x40000>;
  255. read-only;
  256. };
  257. SBL3@80000 {
  258. label = "SBL3";
  259. reg = <0x80000 0x80000>;
  260. read-only;
  261. };
  262. DDRCONFIG@100000 {
  263. label = "DDRCONFIG";
  264. reg = <0x100000 0x10000>;
  265. read-only;
  266. };
  267. SSD@110000 {
  268. label = "SSD";
  269. reg = <0x110000 0x10000>;
  270. read-only;
  271. };
  272. TZ@120000 {
  273. label = "TZ";
  274. reg = <0x120000 0x80000>;
  275. read-only;
  276. };
  277. RPM@1a0000 {
  278. label = "RPM";
  279. reg = <0x1a0000 0x80000>;
  280. read-only;
  281. };
  282. APPSBL@220000 {
  283. label = "APPSBL";
  284. reg = <0x220000 0x80000>;
  285. read-only;
  286. };
  287. APPSBLENV@2a0000 {
  288. label = "APPSBLENV";
  289. reg = <0x2a0000 0x10000>;
  290. };
  291. PRODUCTDATA: PRODUCTDATA@2b0000 {
  292. label = "PRODUCTDATA";
  293. reg = <0x2b0000 0x30000>;
  294. read-only;
  295. nvmem-layout {
  296. compatible = "fixed-layout";
  297. #address-cells = <1>;
  298. #size-cells = <1>;
  299. macaddr_PRODUCTDATA_0: macaddr@0 {
  300. reg = <0x0 0x6>;
  301. };
  302. macaddr_PRODUCTDATA_6: macaddr@6 {
  303. reg = <0x6 0x6>;
  304. };
  305. macaddr_PRODUCTDATA_c: macaddr@c {
  306. reg = <0xc 0x6>;
  307. };
  308. macaddr_PRODUCTDATA_12: macaddr@12 {
  309. reg = <0x12 0x6>;
  310. };
  311. };
  312. };
  313. ART@2e0000 {
  314. label = "ART";
  315. reg = <0x2e0000 0x40000>;
  316. read-only;
  317. nvmem-layout {
  318. compatible = "fixed-layout";
  319. #address-cells = <1>;
  320. #size-cells = <1>;
  321. precal_ART_1000: precal@1000 {
  322. reg = <0x1000 0x2f20>;
  323. };
  324. precal_ART_5000: precal@5000 {
  325. reg = <0x5000 0x2f20>;
  326. };
  327. };
  328. };
  329. TP@320000 {
  330. label = "TP";
  331. reg = <0x320000 0x40000>;
  332. read-only;
  333. };
  334. TINY@360000 {
  335. label = "TINY";
  336. reg = <0x360000 0x500000>;
  337. read-only;
  338. };
  339. firmware@860000 {
  340. compatible = "denx,uimage";
  341. label = "firmware";
  342. reg = <0x860000 0x17a0000>;
  343. };
  344. };
  345. };
  346. };
  347. };
  348. &hs_phy_0 {
  349. status = "okay";
  350. };
  351. &ss_phy_0 {
  352. status = "okay";
  353. };
  354. &usb3_0 {
  355. status = "okay";
  356. pinctrl-0 = <&usb_pwr_en_pins>;
  357. pinctrl-names = "default";
  358. };
  359. &hs_phy_1 {
  360. status = "okay";
  361. };
  362. &ss_phy_1 {
  363. status = "okay";
  364. };
  365. &usb3_1 {
  366. status = "okay";
  367. };
  368. &pcie0 {
  369. status = "okay";
  370. bridge@0,0 {
  371. reg = <0x00000000 0 0 0 0>;
  372. #address-cells = <3>;
  373. #size-cells = <2>;
  374. ranges;
  375. wifi@1,0 {
  376. compatible = "pci168c,0040";
  377. reg = <0x00010000 0 0 0 0>;
  378. nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;
  379. nvmem-cell-names = "mac-address", "pre-calibration";
  380. };
  381. };
  382. };
  383. &pcie1 {
  384. status = "okay";
  385. max-link-speed = <1>;
  386. bridge@0,0 {
  387. reg = <0x00000000 0 0 0 0>;
  388. #address-cells = <3>;
  389. #size-cells = <2>;
  390. ranges;
  391. wifi@1,0 {
  392. compatible = "pci168c,0040";
  393. reg = <0x00010000 0 0 0 0>;
  394. nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;
  395. nvmem-cell-names = "mac-address", "pre-calibration";
  396. };
  397. };
  398. };
  399. &qcom_pinmux {
  400. button_pins: button_pins {
  401. mux {
  402. pins = "gpio16", "gpio54", "gpio24", "gpio25";
  403. function = "gpio";
  404. drive-strength = <2>;
  405. bias-pull-up;
  406. };
  407. };
  408. led_pins: led_pins {
  409. mux {
  410. pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio14",
  411. "gpio15", "gpio55", "gpio56", "gpio57", "gpio58",
  412. "gpio64", "gpio65";
  413. function = "gpio";
  414. drive-strength = <2>;
  415. bias-pull-down;
  416. };
  417. };
  418. spi_pins: spi_pins {
  419. mux {
  420. pins = "gpio18", "gpio19", "gpio21";
  421. function = "gsbi5";
  422. bias-pull-down;
  423. };
  424. data {
  425. pins = "gpio18", "gpio19";
  426. drive-strength = <10>;
  427. };
  428. cs {
  429. pins = "gpio20";
  430. drive-strength = <10>;
  431. bias-pull-up;
  432. };
  433. clk {
  434. pins = "gpio21";
  435. drive-strength = <12>;
  436. };
  437. };
  438. usb_pwr_en_pins: usb_pwr_en_pins {
  439. mux {
  440. pins = "gpio22";
  441. function = "gpio";
  442. drive-strength = <2>;
  443. bias-pull-down;
  444. output-high;
  445. };
  446. };
  447. };