qcom-ipq8068-ecw5410.dts 5.1 KB

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  1. #include "qcom-ipq8064-v2.0-smb208.dtsi"
  2. #include <dt-bindings/input/input.h>
  3. #include <dt-bindings/leds/common.h>
  4. #include <dt-bindings/soc/qcom,tcsr.h>
  5. / {
  6. model = "Edgecore ECW5410";
  7. compatible = "edgecore,ecw5410", "qcom,ipq8064";
  8. reserved-memory {
  9. nss@40000000 {
  10. reg = <0x40000000 0x1000000>;
  11. no-map;
  12. };
  13. smem: smem@41000000 {
  14. reg = <0x41000000 0x200000>;
  15. no-map;
  16. };
  17. wifi_dump@44000000 {
  18. reg = <0x44000000 0x600000>;
  19. no-map;
  20. };
  21. };
  22. cpus {
  23. idle-states {
  24. CPU_SPC: spc {
  25. status = "disabled";
  26. };
  27. };
  28. };
  29. aliases {
  30. serial1 = &gsbi1_serial;
  31. ethernet0 = &gmac2;
  32. ethernet1 = &gmac3;
  33. led-boot = &led_power_green;
  34. led-failsafe = &led_power_red;
  35. led-running = &led_power_green;
  36. led-upgrade = &led_power_green;
  37. };
  38. chosen {
  39. bootargs-append = " console=ttyMSM0,115200n8 root=/dev/ubiblock0_1";
  40. };
  41. keys {
  42. compatible = "gpio-keys";
  43. pinctrl-0 = <&button_pins>;
  44. pinctrl-names = "default";
  45. reset {
  46. label = "reset";
  47. gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
  48. linux,code = <KEY_RESTART>;
  49. debounce-interval = <60>;
  50. wakeup-source;
  51. };
  52. };
  53. leds {
  54. compatible = "gpio-leds";
  55. pinctrl-0 = <&led_pins>;
  56. pinctrl-names = "default";
  57. led_power_green: power_green {
  58. function = LED_FUNCTION_POWER;
  59. color = <LED_COLOR_ID_GREEN>;
  60. gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
  61. };
  62. wlan2g_green {
  63. label = "green:wlan2g";
  64. gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>;
  65. };
  66. wlan2g_yellow {
  67. label = "yellow:wlan2g";
  68. gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
  69. };
  70. wlan5g_green {
  71. label = "green:wlan5g";
  72. gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
  73. };
  74. led_power_red: power_red {
  75. function = LED_FUNCTION_POWER;
  76. color = <LED_COLOR_ID_RED>;
  77. gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>;
  78. };
  79. wlan5g_yellow {
  80. label = "yellow:wlan5g";
  81. gpios = <&qcom_pinmux 59 GPIO_ACTIVE_LOW>;
  82. };
  83. };
  84. };
  85. &qcom_pinmux {
  86. spi_pins: spi_pins {
  87. mux {
  88. pins = "gpio18", "gpio19";
  89. function = "gsbi5";
  90. drive-strength = <10>;
  91. bias-pull-down;
  92. };
  93. clk {
  94. pins = "gpio21";
  95. function = "gsbi5";
  96. drive-strength = <12>;
  97. bias-pull-down;
  98. };
  99. cs {
  100. pins = "gpio20";
  101. function = "gpio";
  102. drive-strength = <10>;
  103. bias-pull-up;
  104. };
  105. };
  106. led_pins: led_pins {
  107. mux {
  108. pins = "gpio16", "gpio23", "gpio24", "gpio26",
  109. "gpio28", "gpio59";
  110. function = "gpio";
  111. drive-strength = <2>;
  112. bias-pull-up;
  113. };
  114. };
  115. button_pins: button_pins {
  116. mux {
  117. pins = "gpio25";
  118. function = "gpio";
  119. drive-strength = <2>;
  120. bias-pull-up;
  121. };
  122. };
  123. uart1_pins: uart1_pins {
  124. mux {
  125. pins = "gpio51", "gpio52", "gpio53", "gpio54";
  126. function = "gsbi1";
  127. drive-strength = <12>;
  128. bias-none;
  129. };
  130. };
  131. };
  132. &gsbi1 {
  133. qcom,mode = <GSBI_PROT_UART_W_FC>;
  134. status = "okay";
  135. serial@12450000 {
  136. status = "okay";
  137. pinctrl-0 = <&uart1_pins>;
  138. pinctrl-names = "default";
  139. };
  140. };
  141. &gsbi5 {
  142. qcom,mode = <GSBI_PROT_SPI>;
  143. status = "okay";
  144. spi4: spi@1a280000 {
  145. status = "okay";
  146. spi-max-frequency = <50000000>;
  147. pinctrl-0 = <&spi_pins>;
  148. pinctrl-names = "default";
  149. cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
  150. m25p80@0 {
  151. compatible = "jedec,spi-nor";
  152. #address-cells = <1>;
  153. #size-cells = <1>;
  154. spi-max-frequency = <50000000>;
  155. reg = <0>;
  156. partitions {
  157. compatible = "qcom,smem-part";
  158. };
  159. };
  160. };
  161. };
  162. &hs_phy_0 {
  163. status = "okay";
  164. };
  165. &ss_phy_0 {
  166. status = "okay";
  167. };
  168. &usb3_0 {
  169. status = "okay";
  170. };
  171. &hs_phy_1 {
  172. status = "okay";
  173. };
  174. &ss_phy_1 {
  175. status = "okay";
  176. };
  177. &usb3_1 {
  178. status = "okay";
  179. };
  180. &pcie1 {
  181. status = "okay";
  182. /delete-property/ pinctrl-0;
  183. /delete-property/ pinctrl-names;
  184. /delete-property/ perst-gpios;
  185. bridge@0,0 {
  186. reg = <0x00000000 0 0 0 0>;
  187. #address-cells = <3>;
  188. #size-cells = <2>;
  189. ranges;
  190. wifi@1,0 {
  191. compatible = "qcom,ath10k";
  192. status = "okay";
  193. reg = <0x00010000 0 0 0 0>;
  194. qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L";
  195. };
  196. };
  197. };
  198. &pcie2 {
  199. status = "okay";
  200. /delete-property/ pinctrl-0;
  201. /delete-property/ pinctrl-names;
  202. /delete-property/ perst-gpios;
  203. bridge@0,0 {
  204. reg = <0x00000000 0 0 0 0>;
  205. #address-cells = <3>;
  206. #size-cells = <2>;
  207. ranges;
  208. wifi@1,0 {
  209. compatible = "qcom,ath10k";
  210. status = "okay";
  211. reg = <0x00010000 0 0 0 0>;
  212. qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L";
  213. };
  214. };
  215. };
  216. &nand {
  217. status = "okay";
  218. nand@0 {
  219. compatible = "qcom,nandcs";
  220. reg = <0>;
  221. nand-ecc-strength = <4>;
  222. nand-bus-width = <8>;
  223. nand-ecc-step-size = <512>;
  224. partitions {
  225. compatible = "fixed-partitions";
  226. #address-cells = <1>;
  227. #size-cells = <1>;
  228. rootfs1@0 {
  229. label = "rootfs1";
  230. reg = <0x0000000 0x4000000>;
  231. };
  232. rootfs2@4000000 {
  233. label = "rootfs2";
  234. reg = <0x4000000 0x4000000>;
  235. };
  236. };
  237. };
  238. };
  239. &mdio0 {
  240. status = "okay";
  241. pinctrl-0 = <&mdio0_pins>;
  242. pinctrl-names = "default";
  243. phy0: ethernet-phy@0 {
  244. reg = <0>;
  245. };
  246. phy1: ethernet-phy@1 {
  247. reg = <1>;
  248. };
  249. };
  250. &gmac2 {
  251. status = "okay";
  252. qcom,id = <2>;
  253. mdiobus = <&mdio0>;
  254. phy-mode = "sgmii";
  255. phy-handle = <&phy1>;
  256. };
  257. &gmac3 {
  258. status = "okay";
  259. qcom,id = <3>;
  260. mdiobus = <&mdio0>;
  261. phy-mode = "sgmii";
  262. phy-handle = <&phy0>;
  263. };
  264. &adm_dma {
  265. status = "okay";
  266. };