openwrt/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2022 MediaTek Inc.
 * Author: Sam.Shih <[email protected]>
 */

/dts-v1/;
#include "mt7988a-rfb-spim-nand.dtsi"
#include <dt-bindings/pinctrl/mt65xx.h>

/ {
	model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
	compatible = "mediatek,mt7988a-dsa-10g-spim-snand",
		     "mediatek,mt7988a-rfb-snand",
		     "mediatek,mt7988";

	chosen {
		bootargs = "console=ttyS0,115200n1 loglevel=8  \
			    earlycon=uart8250,mmio32,0x11000000 \
			    pci=pcie_bus_perf";
	};

	memory {
		reg = <0 0x40000000 0 0x40000000>;
	};
};

&eth {
	pinctrl-0 = <&mdio0_pins>;
	pinctrl-names = "default";
	status = "okay";

	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-mode = "internal";

		fixed-link {
			speed = <10000>;
			full-duplex;
			pause;
		};
	};

	gmac1: mac@1 {
		compatible = "mediatek,eth-mac";
		reg = <1>;
		phy-mode = "internal";
		phy-connection-type = "internal";
		phy = <&phy15>;
	};

	gmac2: mac@2 {
		compatible = "mediatek,eth-mac";
		reg = <2>;
		phy-mode = "10gbase-kr";
		phy-connection-type = "10gbase-kr";
		phy = <&phy8>;
	};

	mdio0: mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		/* external Aquantia AQR113C */
		phy0: ethernet-phy@0 {
			reg = <0>;
			compatible = "ethernet-phy-ieee802.3-c45";
			reset-gpios = <&pio 72 1>;
			reset-assert-us = <100000>;
			reset-deassert-us = <221000>;
		};

		/* external Aquantia AQR113C */
		phy8: ethernet-phy@8 {
			reg = <8>;
			compatible = "ethernet-phy-ieee802.3-c45";
			reset-gpios = <&pio 71 1>;
			reset-assert-us = <100000>;
			reset-deassert-us = <221000>;
		};

		/* external Maxlinear GPY211C */
		phy5: ethernet-phy@5 {
			reg = <5>;
			compatible = "ethernet-phy-ieee802.3-c45";
			phy-mode = "2500base-x";
		};

		/* external Maxlinear GPY211C */
		phy13: ethernet-phy@13 {
			reg = <13>;
			compatible = "ethernet-phy-ieee802.3-c45";
			phy-mode = "2500base-x";
		};

		/* internal 2.5G PHY */
		phy15: ethernet-phy@15 {
			reg = <15>;
			pinctrl-names = "i2p5gbe-led";
			pinctrl-0 = <&i2p5gbe_led0_pins>;
			compatible = "ethernet-phy-ieee802.3-c45";
			phy-mode = "internal";
		};
	};
};

&switch {
	status = "okay";

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			label = "lan0";
			phy-mode = "internal";
			phy-handle = <&gsw_phy0>;
		};

		port@1 {
			reg = <1>;
			label = "lan1";
			phy-mode = "internal";
			phy-handle = <&gsw_phy1>;
		};

		port@2 {
			reg = <2>;
			label = "lan2";
			phy-mode = "internal";
			phy-handle = <&gsw_phy2>;
		};

		port@3 {
			reg = <3>;
			label = "lan3";
			phy-mode = "internal";
			phy-handle = <&gsw_phy3>;
		};

		port@6 {
			reg = <6>;
			ethernet = <&gmac0>;
			phy-mode = "internal";

			fixed-link {
				speed = <10000>;
				full-duplex;
				pause;
			};
		};
	};

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		gsw_phy0: ethernet-phy@0 {
			compatible = "ethernet-phy-id03a2.9481";
			reg = <0>;
			phy-mode = "internal";
			pinctrl-names = "gbe-led";
			pinctrl-0 = <&gbe0_led0_pins>;
			nvmem-cells = <&phy_calibration_p0>;
			nvmem-cell-names = "phy-cal-data";
		};

		gsw_phy1: ethernet-phy@1 {
			compatible = "ethernet-phy-id03a2.9481";
			reg = <1>;
			phy-mode = "internal";
			pinctrl-names = "gbe-led";
			pinctrl-0 = <&gbe1_led0_pins>;
			nvmem-cells = <&phy_calibration_p1>;
			nvmem-cell-names = "phy-cal-data";
		};

		gsw_phy2: ethernet-phy@2 {
			compatible = "ethernet-phy-id03a2.9481";
			reg = <2>;
			phy-mode = "internal";
			pinctrl-names = "gbe-led";
			pinctrl-0 = <&gbe2_led0_pins>;
			nvmem-cells = <&phy_calibration_p2>;
			nvmem-cell-names = "phy-cal-data";
		};

		gsw_phy3: ethernet-phy@3 {
			compatible = "ethernet-phy-id03a2.9481";
			reg = <3>;
			phy-mode = "internal";
			pinctrl-names = "gbe-led";
			pinctrl-0 = <&gbe3_led0_pins>;
			nvmem-cells = <&phy_calibration_p3>;
			nvmem-cell-names = "phy-cal-data";
		};
	};
};