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120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch 2.5 KB

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  1. From 9e7eb0ea442ecb1c3fe443289e288694f10c5148 Mon Sep 17 00:00:00 2001
  2. From: Miquel Raynal <[email protected]>
  3. Date: Thu, 27 Jan 2022 10:18:01 +0100
  4. Subject: [PATCH 07/15] spi: spi-mem: Add an ecc parameter to the spi_mem_op
  5. structure
  6. Soon the SPI-NAND core will need a way to request a SPI controller to
  7. enable ECC support for a given operation. This is because of the
  8. pipelined integration of certain ECC engines, which are directly managed
  9. by the SPI controller itself.
  10. Introduce a spi_mem_op additional field for this purpose: ecc.
  11. So far this field is left unset and checked to be false by all
  12. the SPI controller drivers in their ->supports_op() hook, as they all
  13. call spi_mem_default_supports_op().
  14. Signed-off-by: Miquel Raynal <[email protected]>
  15. Acked-by: Pratyush Yadav <[email protected]>
  16. Reviewed-by: Boris Brezillon <[email protected]>
  17. Reviewed-by: Tudor Ambarus <[email protected]>
  18. Link: https://lore.kernel.org/linux-mtd/[email protected]
  19. (cherry picked from commit a433c2cbd75ab76f277364f44e76f32c7df306e7)
  20. ---
  21. drivers/spi/spi-mem.c | 5 +++++
  22. include/linux/spi/spi-mem.h | 4 ++++
  23. 2 files changed, 9 insertions(+)
  24. --- a/drivers/spi/spi-mem.c
  25. +++ b/drivers/spi/spi-mem.c
  26. @@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct
  27. return false;
  28. }
  29. + if (op->data.ecc) {
  30. + if (!spi_mem_controller_is_capable(ctlr, ecc))
  31. + return false;
  32. + }
  33. +
  34. return spi_mem_check_buswidth(mem, op);
  35. }
  36. EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
  37. --- a/include/linux/spi/spi-mem.h
  38. +++ b/include/linux/spi/spi-mem.h
  39. @@ -89,6 +89,7 @@ enum spi_mem_data_dir {
  40. * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
  41. * @data.buswidth: number of IO lanes used to send/receive the data
  42. * @data.dtr: whether the data should be sent in DTR mode or not
  43. + * @data.ecc: whether error correction is required or not
  44. * @data.dir: direction of the transfer
  45. * @data.nbytes: number of data bytes to send/receive. Can be zero if the
  46. * operation does not involve transferring data
  47. @@ -119,6 +120,7 @@ struct spi_mem_op {
  48. struct {
  49. u8 buswidth;
  50. u8 dtr : 1;
  51. + u8 ecc : 1;
  52. enum spi_mem_data_dir dir;
  53. unsigned int nbytes;
  54. union {
  55. @@ -288,9 +290,11 @@ struct spi_controller_mem_ops {
  56. /**
  57. * struct spi_controller_mem_caps - SPI memory controller capabilities
  58. * @dtr: Supports DTR operations
  59. + * @ecc: Supports operations with error correction
  60. */
  61. struct spi_controller_mem_caps {
  62. bool dtr;
  63. + bool ecc;
  64. };
  65. #define spi_mem_controller_is_capable(ctlr, cap) \