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bcm6318.dtsi 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /dts-v1/;
  3. #include <dt-bindings/clock/bcm6318-clock.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/interrupt-controller/bcm6318-interrupt-controller.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/reset/bcm6318-reset.h>
  9. #include <dt-bindings/soc/bcm6318-pm.h>
  10. / {
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. compatible = "brcm,bcm6318";
  14. aliases {
  15. pinctrl = &pinctrl;
  16. serial0 = &uart0;
  17. spi1 = &hsspi;
  18. };
  19. chosen {
  20. bootargs = "earlycon";
  21. stdout-path = "serial0:115200n8";
  22. };
  23. clocks {
  24. periph_osc: periph-osc {
  25. compatible = "fixed-clock";
  26. #clock-cells = <0>;
  27. clock-frequency = <50000000>;
  28. clock-output-names = "periph";
  29. };
  30. hsspi_osc: hsspi-osc {
  31. compatible = "fixed-clock";
  32. #clock-cells = <0>;
  33. clock-frequency = <250000000>;
  34. clock-output-names = "hsspi_osc";
  35. };
  36. };
  37. cpus {
  38. #address-cells = <1>;
  39. #size-cells = <0>;
  40. mips-hpt-frequency = <166500000>;
  41. cpu@0 {
  42. compatible = "brcm,bmips3300", "mips,mips4Kc";
  43. device_type = "cpu";
  44. reg = <0>;
  45. };
  46. };
  47. cpu_intc: interrupt-controller {
  48. #address-cells = <0>;
  49. compatible = "mti,cpu-interrupt-controller";
  50. interrupt-controller;
  51. #interrupt-cells = <1>;
  52. };
  53. memory@0 {
  54. device_type = "memory";
  55. reg = <0 0>;
  56. };
  57. ubus {
  58. #address-cells = <1>;
  59. #size-cells = <1>;
  60. compatible = "simple-bus";
  61. ranges;
  62. periph_clk: clock-controller@10000004 {
  63. compatible = "brcm,bcm6318-clocks";
  64. reg = <0x10000004 0x4>;
  65. #clock-cells = <1>;
  66. };
  67. ubus_clk: clock-controller@10000008 {
  68. compatible = "brcm,bcm6318-ubus-clocks";
  69. reg = <0x10000008 0x4>;
  70. #clock-cells = <1>;
  71. };
  72. periph_rst: reset-controller@10000010 {
  73. compatible = "brcm,bcm6345-reset";
  74. reg = <0x10000010 0x4>;
  75. #reset-cells = <1>;
  76. };
  77. ext_intc: interrupt-controller@10000018 {
  78. #address-cells = <1>;
  79. compatible = "brcm,bcm6318-ext-intc";
  80. reg = <0x10000018 0x4>;
  81. interrupt-controller;
  82. #interrupt-cells = <2>;
  83. interrupt-parent = <&periph_intc>;
  84. interrupts = <BCM6318_IRQ_EXT0>,
  85. <BCM6318_IRQ_EXT1>,
  86. <BCM6318_IRQ_EXT2>,
  87. <BCM6318_IRQ_EXT3>;
  88. };
  89. periph_intc: interrupt-controller@10000020 {
  90. #address-cells = <1>;
  91. compatible = "brcm,bcm6345-l1-intc";
  92. reg = <0x10000020 0x20>;
  93. interrupt-controller;
  94. #interrupt-cells = <1>;
  95. interrupt-parent = <&cpu_intc>;
  96. interrupts = <2>, <3>;
  97. };
  98. wdt: watchdog@10000068 {
  99. compatible = "brcm,bcm7038-wdt";
  100. reg = <0x10000068 0xc>;
  101. clocks = <&periph_osc>;
  102. timeout-sec = <30>;
  103. };
  104. pll_cntl: syscon@10000074 {
  105. compatible = "syscon", "simple-mfd";
  106. reg = <0x10000074 0x4>;
  107. native-endian;
  108. syscon-reboot {
  109. compatible = "syscon-reboot";
  110. offset = <0>;
  111. mask = <0x1>;
  112. };
  113. };
  114. gpio_cntl: syscon@10000080 {
  115. #address-cells = <1>;
  116. #size-cells = <1>;
  117. compatible = "brcm,bcm6318-gpio-sysctl",
  118. "syscon", "simple-mfd";
  119. reg = <0x10000080 0x80>;
  120. ranges = <0 0x10000080 0x80>;
  121. native-endian;
  122. gpio: gpio@0 {
  123. compatible = "brcm,bcm6318-gpio";
  124. reg-names = "dirout", "dat";
  125. reg = <0x0 0x8>, <0x8 0x8>;
  126. gpio-controller;
  127. gpio-ranges = <&pinctrl 0 0 50>;
  128. #gpio-cells = <2>;
  129. };
  130. pinctrl: pinctrl@18 {
  131. compatible = "brcm,bcm6318-pinctrl";
  132. reg = <0x18 0x10>, <0x54 0x18>;
  133. pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
  134. function = "ephy0_spd_led";
  135. pins = "gpio0";
  136. };
  137. pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
  138. function = "ephy1_spd_led";
  139. pins = "gpio1";
  140. };
  141. pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
  142. function = "ephy2_spd_led";
  143. pins = "gpio2";
  144. };
  145. pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
  146. function = "ephy3_spd_led";
  147. pins = "gpio3";
  148. };
  149. pinctrl_ephy0_act_led: ephy0_act_led-pins {
  150. function = "ephy0_act_led";
  151. pins = "gpio4";
  152. };
  153. pinctrl_ephy1_act_led: ephy1_act_led-pins {
  154. function = "ephy1_act_led";
  155. pins = "gpio5";
  156. };
  157. pinctrl_ephy2_act_led: ephy2_act_led-pins {
  158. function = "ephy2_act_led";
  159. pins = "gpio6";
  160. };
  161. pinctrl_ephy3_act_led: ephy3_act_led-pins {
  162. function = "ephy3_act_led";
  163. pins = "gpio7";
  164. };
  165. pinctrl_serial_led: serial_led-pins {
  166. pinctrl_serial_led_data: serial_led_data-pins {
  167. function = "serial_led_data";
  168. pins = "gpio6";
  169. };
  170. pinctrl_serial_led_clk: serial_led_clk-pins {
  171. function = "serial_led_clk";
  172. pins = "gpio7";
  173. };
  174. };
  175. pinctrl_inet_act_led: inet_act_led-pins {
  176. function = "inet_act_led";
  177. pins = "gpio8";
  178. };
  179. pinctrl_inet_fail_led: inet_fail_led-pins {
  180. function = "inet_fail_led";
  181. pins = "gpio9";
  182. };
  183. pinctrl_dsl_led: dsl_led-pins {
  184. function = "dsl_led";
  185. pins = "gpio10";
  186. };
  187. pinctrl_post_fail_led: post_fail_led-pins {
  188. function = "post_fail_led";
  189. pins = "gpio11";
  190. };
  191. pinctrl_wlan_wps_led: wlan_wps_led-pins {
  192. function = "wlan_wps_led";
  193. pins = "gpio12";
  194. };
  195. pinctrl_usb_pwron: usb_pwron-pins {
  196. function = "usb_pwron";
  197. pins = "gpio13";
  198. };
  199. pinctrl_usb_device_led: usb_device_led-pins {
  200. function = "usb_device_led";
  201. pins = "gpio13";
  202. };
  203. pinctrl_usb_active: usb_active-pins {
  204. function = "usb_active";
  205. pins = "gpio40";
  206. };
  207. };
  208. };
  209. uart0: serial@10000100 {
  210. compatible = "brcm,bcm6345-uart";
  211. reg = <0x10000100 0x18>;
  212. interrupt-parent = <&periph_intc>;
  213. interrupts = <BCM6318_IRQ_UART0>;
  214. clocks = <&periph_osc>;
  215. clock-names = "periph";
  216. status = "disabled";
  217. };
  218. leds: led-controller@10000200 {
  219. #address-cells = <1>;
  220. #size-cells = <0>;
  221. compatible = "brcm,bcm6328-leds";
  222. reg = <0x10000200 0x24>;
  223. status = "disabled";
  224. };
  225. periph_pwr: power-controller@100008e8 {
  226. compatible = "brcm,bcm6318-power-controller";
  227. reg = <0x100008e8 0x4>;
  228. #power-domain-cells = <1>;
  229. };
  230. hsspi: spi@10003000 {
  231. #address-cells = <1>;
  232. #size-cells = <0>;
  233. compatible = "brcm,bcm6328-hsspi";
  234. reg = <0x10003000 0x600>;
  235. interrupt-parent = <&periph_intc>;
  236. interrupts = <BCM6318_IRQ_HSSPI>;
  237. clocks = <&periph_clk BCM6318_CLK_HSSPI>,
  238. <&hsspi_osc>;
  239. clock-names = "hsspi",
  240. "pll";
  241. resets = <&periph_rst BCM6318_RST_SPI>;
  242. status = "disabled";
  243. };
  244. ehci: usb@10005000 {
  245. compatible = "brcm,bcm6318-ehci", "generic-ehci";
  246. reg = <0x10005000 0x100>;
  247. big-endian;
  248. spurious-oc;
  249. interrupt-parent = <&periph_intc>;
  250. interrupts = <BCM6318_IRQ_EHCI>;
  251. phys = <&usbh 0>;
  252. phy-names = "usb";
  253. status = "disabled";
  254. };
  255. ohci: usb@10005100 {
  256. compatible = "brcm,bcm6318-ohci", "generic-ohci";
  257. reg = <0x10005100 0x100>;
  258. big-endian;
  259. no-big-frame-no;
  260. interrupt-parent = <&periph_intc>;
  261. interrupts = <BCM6318_IRQ_OHCI>;
  262. phys = <&usbh 0>;
  263. phy-names = "usb";
  264. status = "disabled";
  265. };
  266. usbh: usb-phy@10005200 {
  267. compatible = "brcm,bcm6318-usbh-phy";
  268. reg = <0x10005200 0x38>;
  269. #phy-cells = <1>;
  270. clocks = <&periph_clk BCM6318_CLK_USBD>,
  271. <&ubus_clk BCM6318_UCLK_USB>;
  272. clock-names = "usbh",
  273. "usb_ref";
  274. power-domains = <&periph_pwr BCM6318_POWER_DOMAIN_USB>;
  275. resets = <&periph_rst BCM6318_RST_USBH>;
  276. status = "disabled";
  277. };
  278. pcie: pcie@10010000 {
  279. compatible = "brcm,bcm6318-pcie";
  280. reg = <0x10010000 0x10000>;
  281. #address-cells = <3>;
  282. #size-cells = <2>;
  283. device_type = "pci";
  284. bus-range = <0x00 0x01>;
  285. ranges = <0x2000000 0 0x10200000 0x10200000 0 0x100000>;
  286. linux,pci-probe-only = <1>;
  287. interrupt-parent = <&periph_intc>;
  288. interrupts = <BCM6318_IRQ_PCIE_RC>;
  289. clocks = <&periph_clk BCM6318_CLK_PCIE>,
  290. <&periph_clk BCM6318_CLK_PCIE25>,
  291. <&ubus_clk BCM6318_UCLK_PCIE>;
  292. clock-names = "pcie",
  293. "pcie25",
  294. "pcie-ubus";
  295. resets = <&periph_rst BCM6318_RST_PCIE>,
  296. <&periph_rst BCM6318_RST_PCIE_EXT>,
  297. <&periph_rst BCM6318_RST_PCIE_CORE>,
  298. <&periph_rst BCM6318_RST_PCIE_HARD>;
  299. reset-names = "pcie",
  300. "pcie-ext",
  301. "pcie-core",
  302. "pcie-hard";
  303. power-domains = <&periph_pwr BCM6318_POWER_DOMAIN_PCIE>;
  304. status = "disabled";
  305. };
  306. switch0: switch@10080000 {
  307. #address-cells = <1>;
  308. #size-cells = <0>;
  309. compatible = "brcm,bcm6318-switch";
  310. reg = <0x10080000 0x8000>;
  311. big-endian;
  312. ports {
  313. #address-cells = <1>;
  314. #size-cells = <0>;
  315. port@8 {
  316. reg = <8>;
  317. phy-mode = "internal";
  318. ethernet = <&ethernet>;
  319. fixed-link {
  320. speed = <1000>;
  321. full-duplex;
  322. };
  323. };
  324. };
  325. };
  326. mdio: mdio@100800b0 {
  327. #address-cells = <1>;
  328. #size-cells = <0>;
  329. compatible = "brcm,bcm6368-mdio-mux";
  330. reg = <0x100800b0 0x8>;
  331. mdio_int: mdio@0 {
  332. #address-cells = <1>;
  333. #size-cells = <0>;
  334. reg = <0>;
  335. phy1: ethernet-phy@1 {
  336. compatible = "ethernet-phy-ieee802.3-c22";
  337. reg = <1>;
  338. };
  339. phy2: ethernet-phy@2 {
  340. compatible = "ethernet-phy-ieee802.3-c22";
  341. reg = <2>;
  342. };
  343. phy3: ethernet-phy@3 {
  344. compatible = "ethernet-phy-ieee802.3-c22";
  345. reg = <3>;
  346. };
  347. phy4: ethernet-phy@4 {
  348. compatible = "ethernet-phy-ieee802.3-c22";
  349. reg = <4>;
  350. };
  351. };
  352. mdio_ext: mdio@1 {
  353. #address-cells = <1>;
  354. #size-cells = <0>;
  355. reg = <1>;
  356. };
  357. };
  358. ethernet: ethernet@10088000 {
  359. compatible = "brcm,bcm6318-enetsw";
  360. reg = <0x10088000 0x80>,
  361. <0x10088200 0x80>,
  362. <0x10088400 0x80>;
  363. reg-names = "dma",
  364. "dma-channels",
  365. "dma-sram";
  366. interrupt-parent = <&periph_intc>;
  367. interrupts = <BCM6318_IRQ_ENETSW_RX_DMA0>,
  368. <BCM6318_IRQ_ENETSW_TX_DMA0>;
  369. interrupt-names = "rx",
  370. "tx";
  371. clocks = <&periph_clk BCM6318_CLK_ROBOSW250>,
  372. <&periph_clk BCM6318_CLK_ROBOSW025>,
  373. <&ubus_clk BCM6318_UCLK_ROBOSW>;
  374. resets = <&periph_rst BCM6318_RST_ENETSW>,
  375. <&periph_rst BCM6318_RST_EPHY>;
  376. power-domains = <&periph_pwr BCM6318_POWER_DOMAIN_EPHY0>,
  377. <&periph_pwr BCM6318_POWER_DOMAIN_EPHY1>,
  378. <&periph_pwr BCM6318_POWER_DOMAIN_EPHY2>,
  379. <&periph_pwr BCM6318_POWER_DOMAIN_EPHY3>;
  380. dma-rx = <0>;
  381. dma-tx = <1>;
  382. status = "disabled";
  383. };
  384. };
  385. };