bcm6362.dtsi 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /dts-v1/;
  3. #include <dt-bindings/clock/bcm6362-clock.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/interrupt-controller/bcm6362-interrupt-controller.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/reset/bcm6362-reset.h>
  9. #include <dt-bindings/soc/bcm6362-pm.h>
  10. / {
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. compatible = "brcm,bcm6362";
  14. aliases {
  15. nflash = &nflash;
  16. pinctrl = &pinctrl;
  17. serial0 = &uart0;
  18. serial1 = &uart1;
  19. spi0 = &lsspi;
  20. spi1 = &hsspi;
  21. };
  22. chosen {
  23. bootargs = "earlycon";
  24. stdout-path = "serial0:115200n8";
  25. };
  26. clocks {
  27. periph_osc: periph-osc {
  28. compatible = "fixed-clock";
  29. #clock-cells = <0>;
  30. clock-frequency = <50000000>;
  31. clock-output-names = "periph";
  32. };
  33. hsspi_osc: hsspi-osc {
  34. compatible = "fixed-clock";
  35. #clock-cells = <0>;
  36. clock-frequency = <400000000>;
  37. clock-output-names = "hsspi_osc";
  38. };
  39. };
  40. cpus {
  41. #address-cells = <1>;
  42. #size-cells = <0>;
  43. mips-hpt-frequency = <200000000>;
  44. cpu@0 {
  45. compatible = "brcm,bmips4350", "mips,mips4Kc";
  46. device_type = "cpu";
  47. reg = <0>;
  48. };
  49. cpu@1 {
  50. compatible = "brcm,bmips4350", "mips,mips4Kc";
  51. device_type = "cpu";
  52. reg = <1>;
  53. };
  54. };
  55. cpu_intc: interrupt-controller {
  56. #address-cells = <0>;
  57. compatible = "mti,cpu-interrupt-controller";
  58. interrupt-controller;
  59. #interrupt-cells = <1>;
  60. };
  61. memory@0 {
  62. device_type = "memory";
  63. reg = <0 0>;
  64. };
  65. ubus {
  66. #address-cells = <1>;
  67. #size-cells = <1>;
  68. compatible = "simple-bus";
  69. ranges;
  70. periph_clk: clock-controller@10000004 {
  71. compatible = "brcm,bcm6362-clocks";
  72. reg = <0x10000004 0x4>;
  73. #clock-cells = <1>;
  74. };
  75. pll_cntl: syscon@10000008 {
  76. compatible = "syscon", "simple-mfd";
  77. reg = <0x10000008 0x4>;
  78. native-endian;
  79. syscon-reboot {
  80. compatible = "syscon-reboot";
  81. offset = <0x0>;
  82. mask = <0x1>;
  83. };
  84. };
  85. periph_rst: reset-controller@10000010 {
  86. compatible = "brcm,bcm6345-reset";
  87. reg = <0x10000010 0x4>;
  88. #reset-cells = <1>;
  89. };
  90. ext_intc: interrupt-controller@10000018 {
  91. #address-cells = <1>;
  92. compatible = "brcm,bcm6345-ext-intc";
  93. reg = <0x10000018 0x4>;
  94. interrupt-controller;
  95. #interrupt-cells = <2>;
  96. interrupt-parent = <&periph_intc>;
  97. interrupts = <BCM6362_IRQ_EXT0>,
  98. <BCM6362_IRQ_EXT1>,
  99. <BCM6362_IRQ_EXT2>,
  100. <BCM6362_IRQ_EXT3>;
  101. };
  102. periph_intc: interrupt-controller@10000020 {
  103. #address-cells = <1>;
  104. compatible = "brcm,bcm6345-l1-intc";
  105. reg = <0x10000020 0x10>,
  106. <0x10000030 0x10>;
  107. interrupt-controller;
  108. #interrupt-cells = <1>;
  109. interrupt-parent = <&cpu_intc>;
  110. interrupts = <2>, <3>;
  111. };
  112. wdt: watchdog@1000005c {
  113. compatible = "brcm,bcm7038-wdt";
  114. reg = <0x1000005c 0xc>;
  115. clocks = <&periph_osc>;
  116. timeout-sec = <30>;
  117. };
  118. gpio_cntl: syscon@10000080 {
  119. #address-cells = <1>;
  120. #size-cells = <1>;
  121. compatible = "brcm,bcm6362-gpio-sysctl",
  122. "syscon", "simple-mfd";
  123. reg = <0x10000080 0x80>;
  124. ranges = <0 0x10000080 0x80>;
  125. native-endian;
  126. gpio: gpio@0 {
  127. compatible = "brcm,bcm6362-gpio";
  128. reg-names = "dirout", "dat";
  129. reg = <0x0 0x8>, <0x8 0x8>;
  130. gpio-controller;
  131. gpio-ranges = <&pinctrl 0 0 48>;
  132. #gpio-cells = <2>;
  133. };
  134. pinctrl: pinctrl@18 {
  135. compatible = "brcm,bcm6362-pinctrl";
  136. reg = <0x18 0x10>, <0x38 0x4>;
  137. pinctrl_usb_device_led: usb_device_led-pins {
  138. function = "usb_device_led";
  139. pins = "gpio0";
  140. };
  141. pinctrl_sys_irq: sys_irq-pins {
  142. function = "sys_irq";
  143. pins = "gpio1";
  144. };
  145. pinctrl_serial_led: serial_led-pins {
  146. pinctrl_serial_led_clk: serial_led_clk-pins {
  147. function = "serial_led_clk";
  148. pins = "gpio2";
  149. };
  150. pinctrl_serial_led_data: serial_led_data-pins {
  151. function = "serial_led_data";
  152. pins = "gpio3";
  153. };
  154. };
  155. pinctrl_robosw_led_data: robosw_led_data-pins {
  156. function = "robosw_led_data";
  157. pins = "gpio4";
  158. };
  159. pinctrl_robosw_led_clk: robosw_led_clk-pins {
  160. function = "robosw_led_clk";
  161. pins = "gpio5";
  162. };
  163. pinctrl_robosw_led0: robosw_led0-pins {
  164. function = "robosw_led0";
  165. pins = "gpio6";
  166. };
  167. pinctrl_robosw_led1: robosw_led1-pins {
  168. function = "robosw_led1";
  169. pins = "gpio7";
  170. };
  171. pinctrl_inet_led: inet_led-pins {
  172. function = "inet_led";
  173. pins = "gpio8";
  174. };
  175. pinctrl_spi_cs2: spi_cs2-pins {
  176. function = "spi_cs2";
  177. pins = "gpio9";
  178. };
  179. pinctrl_spi_cs3: spi_cs3-pins {
  180. function = "spi_cs3";
  181. pins = "gpio10";
  182. };
  183. pinctrl_ntr_pulse: ntr_pulse-pins {
  184. function = "ntr_pulse";
  185. pins = "gpio11";
  186. };
  187. pinctrl_uart1_scts: uart1_scts-pins {
  188. function = "uart1_scts";
  189. pins = "gpio12";
  190. };
  191. pinctrl_uart1_srts: uart1_srts-pins {
  192. function = "uart1_srts";
  193. pins = "gpio13";
  194. };
  195. pinctrl_uart1: uart1-pins {
  196. pinctrl_uart1_sdin: uart1_sdin-pins {
  197. function = "uart1_sdin";
  198. pins = "gpio14";
  199. };
  200. pinctrl_uart1_sdout: uart1_sdout-pins {
  201. function = "uart1_sdout";
  202. pins = "gpio15";
  203. };
  204. };
  205. pinctrl_adsl_spi: adsl_spi-pins {
  206. pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
  207. function = "adsl_spi_miso";
  208. pins = "gpio16";
  209. };
  210. pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
  211. function = "adsl_spi_mosi";
  212. pins = "gpio17";
  213. };
  214. pinctrl_adsl_spi_clk: adsl_spi_clk-pins {
  215. function = "adsl_spi_clk";
  216. pins = "gpio18";
  217. };
  218. pinctrl_adsl_spi_cs: adsl_spi_cs-pins {
  219. function = "adsl_spi_cs";
  220. pins = "gpio19";
  221. };
  222. };
  223. pinctrl_ephy0_led: ephy0_led-pins {
  224. function = "ephy0_led";
  225. pins = "gpio20";
  226. };
  227. pinctrl_ephy1_led: ephy1_led-pins {
  228. function = "ephy1_led";
  229. pins = "gpio21";
  230. };
  231. pinctrl_ephy2_led: ephy2_led-pins {
  232. function = "ephy2_led";
  233. pins = "gpio22";
  234. };
  235. pinctrl_ephy3_led: ephy3_led-pins {
  236. function = "ephy3_led";
  237. pins = "gpio23";
  238. };
  239. pinctrl_ext_irq0: ext_irq0-pins {
  240. function = "ext_irq0";
  241. pins = "gpio24";
  242. };
  243. pinctrl_ext_irq1: ext_irq1-pins {
  244. function = "ext_irq1";
  245. pins = "gpio25";
  246. };
  247. pinctrl_ext_irq2: ext_irq2-pins {
  248. function = "ext_irq2";
  249. pins = "gpio26";
  250. };
  251. pinctrl_ext_irq3: ext_irq3-pins {
  252. function = "ext_irq3";
  253. pins = "gpio27";
  254. };
  255. pinctrl_nand: nand-pins {
  256. function = "nand";
  257. group = "nand_grp";
  258. };
  259. };
  260. };
  261. uart0: serial@10000100 {
  262. compatible = "brcm,bcm6345-uart";
  263. reg = <0x10000100 0x18>;
  264. interrupt-parent = <&periph_intc>;
  265. interrupts = <BCM6362_IRQ_UART0>;
  266. clocks = <&periph_osc>;
  267. clock-names = "periph";
  268. status = "disabled";
  269. };
  270. uart1: serial@10000120 {
  271. compatible = "brcm,bcm6345-uart";
  272. reg = <0x10000120 0x18>;
  273. interrupt-parent = <&periph_intc>;
  274. interrupts = <BCM6362_IRQ_UART1>;
  275. clocks = <&periph_osc>;
  276. clock-names = "periph";
  277. status = "disabled";
  278. };
  279. nflash: nand@10000200 {
  280. #address-cells = <1>;
  281. #size-cells = <0>;
  282. compatible = "brcm,nand-bcm6368",
  283. "brcm,brcmnand-v2.2",
  284. "brcm,brcmnand";
  285. reg = <0x10000200 0x180>,
  286. <0x10000600 0x200>,
  287. <0x10000070 0x10>;
  288. reg-names = "nand",
  289. "nand-cache",
  290. "nand-int-base";
  291. interrupt-parent = <&periph_intc>;
  292. interrupts = <BCM6362_IRQ_NAND>;
  293. clocks = <&periph_clk BCM6362_CLK_NAND>;
  294. clock-names = "nand";
  295. pinctrl-names = "default";
  296. pinctrl-0 = <&pinctrl_nand>;
  297. status = "disabled";
  298. };
  299. lsspi: spi@10000800 {
  300. #address-cells = <1>;
  301. #size-cells = <0>;
  302. compatible = "brcm,bcm6358-spi";
  303. reg = <0x10000800 0x70c>;
  304. interrupt-parent = <&periph_intc>;
  305. interrupts = <BCM6362_IRQ_LSSPI>;
  306. clocks = <&periph_clk BCM6362_CLK_SPI>;
  307. clock-names = "spi";
  308. resets = <&periph_rst BCM6362_RST_SPI>;
  309. status = "disabled";
  310. };
  311. hsspi: spi@10001000 {
  312. #address-cells = <1>;
  313. #size-cells = <0>;
  314. compatible = "brcm,bcm6328-hsspi";
  315. reg = <0x10001000 0x600>;
  316. interrupt-parent = <&periph_intc>;
  317. interrupts = <BCM6362_IRQ_HSSPI>;
  318. clocks = <&periph_clk BCM6362_CLK_HSSPI>,
  319. <&hsspi_osc>;
  320. clock-names = "hsspi",
  321. "pll";
  322. resets = <&periph_rst BCM6362_RST_SPI>;
  323. status = "disabled";
  324. };
  325. serdes_cntl: syscon@10001804 {
  326. compatible = "syscon";
  327. reg = <0x10001804 0x4>;
  328. native-endian;
  329. };
  330. periph_pwr: power-controller@10001848 {
  331. compatible = "brcm,bcm6362-power-controller";
  332. reg = <0x10001848 0x4>;
  333. #power-domain-cells = <1>;
  334. };
  335. leds: led-controller@10001900 {
  336. #address-cells = <1>;
  337. #size-cells = <0>;
  338. compatible = "brcm,bcm6328-leds";
  339. reg = <0x10001900 0x24>;
  340. status = "disabled";
  341. };
  342. ehci: usb@10002500 {
  343. compatible = "brcm,bcm6362-ehci", "generic-ehci";
  344. reg = <0x10002500 0x100>;
  345. big-endian;
  346. spurious-oc;
  347. interrupt-parent = <&periph_intc>;
  348. interrupts = <BCM6362_IRQ_EHCI>;
  349. phys = <&usbh 0>;
  350. phy-names = "usb";
  351. status = "disabled";
  352. };
  353. ohci: usb@10002600 {
  354. compatible = "brcm,bcm6362-ohci", "generic-ohci";
  355. reg = <0x10002600 0x100>;
  356. big-endian;
  357. no-big-frame-no;
  358. interrupt-parent = <&periph_intc>;
  359. interrupts = <BCM6362_IRQ_OHCI>;
  360. phys = <&usbh 0>;
  361. phy-names = "usb";
  362. status = "disabled";
  363. };
  364. usbh: usb-phy@10002700 {
  365. compatible = "brcm,bcm6362-usbh-phy";
  366. reg = <0x10002700 0x38>;
  367. #phy-cells = <1>;
  368. clocks = <&periph_clk BCM6362_CLK_USBH>;
  369. clock-names = "usbh";
  370. power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_USBH>;
  371. resets = <&periph_rst BCM6362_RST_USBH>;
  372. status = "disabled";
  373. };
  374. random: rng@10002880 {
  375. compatible = "brcm,bcm6368-rng";
  376. reg = <0x10002880 0x14>;
  377. clocks = <&periph_clk BCM6362_CLK_IPSEC>;
  378. clock-names = "ipsec";
  379. resets = <&periph_rst BCM6362_RST_IPSEC>;
  380. power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_IPSEC>;
  381. };
  382. ethernet: ethernet@1000d800 {
  383. compatible = "brcm,bcm6362-enetsw";
  384. reg = <0x1000d800 0x80>,
  385. <0x1000da00 0x80>,
  386. <0x1000dc00 0x80>;
  387. reg-names = "dma",
  388. "dma-channels",
  389. "dma-sram";
  390. interrupt-parent = <&periph_intc>;
  391. interrupts = <BCM6362_IRQ_ENETSW_RX_DMA0>;
  392. interrupt-names = "rx";
  393. clocks = <&periph_clk BCM6362_CLK_SWPKT_USB>,
  394. <&periph_clk BCM6362_CLK_SWPKT_SAR>,
  395. <&periph_clk BCM6362_CLK_ROBOSW>;
  396. resets = <&periph_rst BCM6362_RST_ENETSW>,
  397. <&periph_rst BCM6362_RST_EPHY>;
  398. power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_ROBOSW>,
  399. <&periph_pwr BCM6362_POWER_DOMAIN_GMII_PADS>;
  400. dma-rx = <0>;
  401. dma-tx = <1>;
  402. status = "disabled";
  403. };
  404. switch0: switch@10e00000 {
  405. #address-cells = <1>;
  406. #size-cells = <0>;
  407. compatible = "brcm,bcm6362-switch";
  408. reg = <0x10e00000 0x8000>;
  409. big-endian;
  410. ports {
  411. #address-cells = <1>;
  412. #size-cells = <0>;
  413. port@8 {
  414. reg = <8>;
  415. phy-mode = "internal";
  416. ethernet = <&ethernet>;
  417. fixed-link {
  418. speed = <1000>;
  419. full-duplex;
  420. };
  421. };
  422. };
  423. };
  424. mdio: mdio@10e000b0 {
  425. #address-cells = <1>;
  426. #size-cells = <0>;
  427. compatible = "brcm,bcm6368-mdio-mux";
  428. reg = <0x10e000b0 0x8>;
  429. mdio_int: mdio@0 {
  430. #address-cells = <1>;
  431. #size-cells = <0>;
  432. reg = <0>;
  433. phy1: ethernet-phy@1 {
  434. compatible = "ethernet-phy-ieee802.3-c22";
  435. reg = <1>;
  436. };
  437. phy2: ethernet-phy@2 {
  438. compatible = "ethernet-phy-ieee802.3-c22";
  439. reg = <2>;
  440. };
  441. phy3: ethernet-phy@3 {
  442. compatible = "ethernet-phy-ieee802.3-c22";
  443. reg = <3>;
  444. };
  445. phy4: ethernet-phy@4 {
  446. compatible = "ethernet-phy-ieee802.3-c22";
  447. reg = <4>;
  448. };
  449. };
  450. mdio_ext: mdio@1 {
  451. #address-cells = <1>;
  452. #size-cells = <0>;
  453. reg = <1>;
  454. };
  455. };
  456. pcie: pcie@10e40000 {
  457. compatible = "brcm,bcm6328-pcie";
  458. reg = <0x10e40000 0x10000>;
  459. #address-cells = <3>;
  460. #size-cells = <2>;
  461. device_type = "pci";
  462. bus-range = <0x00 0x01>;
  463. ranges = <0x2000000 0 0x10f00000 0x10f00000 0 0x100000>;
  464. linux,pci-probe-only = <1>;
  465. interrupt-parent = <&periph_intc>;
  466. interrupts = <BCM6362_IRQ_PCIE_RC>;
  467. clocks = <&periph_clk BCM6362_CLK_PCIE>;
  468. clock-names = "pcie";
  469. resets = <&periph_rst BCM6362_RST_PCIE>,
  470. <&periph_rst BCM6362_RST_PCIE_EXT>,
  471. <&periph_rst BCM6362_RST_PCIE_CORE>;
  472. reset-names = "pcie",
  473. "pcie-ext",
  474. "pcie-core";
  475. power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_PCIE>;
  476. brcm,serdes = <&serdes_cntl>;
  477. status = "disabled";
  478. };
  479. };
  480. };