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bcm6368.dtsi 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /dts-v1/;
  3. #include <dt-bindings/clock/bcm6368-clock.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/interrupt-controller/bcm6368-interrupt-controller.h>
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/reset/bcm6368-reset.h>
  9. / {
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. compatible = "brcm,bcm6368";
  13. aliases {
  14. nflash = &nflash;
  15. pflash = &pflash;
  16. pinctrl = &pinctrl;
  17. serial0 = &uart0;
  18. serial1 = &uart1;
  19. spi0 = &lsspi;
  20. };
  21. chosen {
  22. bootargs = "earlycon";
  23. stdout-path = "serial0:115200n8";
  24. };
  25. clocks {
  26. periph_osc: periph-osc {
  27. compatible = "fixed-clock";
  28. #clock-cells = <0>;
  29. clock-frequency = <50000000>;
  30. clock-output-names = "periph";
  31. };
  32. };
  33. cpus {
  34. #address-cells = <1>;
  35. #size-cells = <0>;
  36. mips-hpt-frequency = <200000000>;
  37. cpu@0 {
  38. compatible = "brcm,bmips4350", "mips,mips4Kc";
  39. device_type = "cpu";
  40. reg = <0>;
  41. };
  42. cpu@1 {
  43. compatible = "brcm,bmips4350", "mips,mips4Kc";
  44. device_type = "cpu";
  45. reg = <1>;
  46. };
  47. };
  48. cpu_intc: interrupt-controller {
  49. #address-cells = <0>;
  50. compatible = "mti,cpu-interrupt-controller";
  51. interrupt-controller;
  52. #interrupt-cells = <1>;
  53. };
  54. memory@0 {
  55. device_type = "memory";
  56. reg = <0 0>;
  57. };
  58. ubus {
  59. #address-cells = <1>;
  60. #size-cells = <1>;
  61. compatible = "simple-bus";
  62. ranges;
  63. periph_clk: clock-controller@10000004 {
  64. compatible = "brcm,bcm6368-clocks";
  65. reg = <0x10000004 0x4>;
  66. #clock-cells = <1>;
  67. };
  68. pll_cntl: syscon@10000008 {
  69. compatible = "syscon", "simple-mfd";
  70. reg = <0x10000008 0x4>;
  71. native-endian;
  72. syscon-reboot {
  73. compatible = "syscon-reboot";
  74. offset = <0x0>;
  75. mask = <0x1>;
  76. };
  77. };
  78. periph_rst: reset-controller@10000010 {
  79. compatible = "brcm,bcm6345-reset";
  80. reg = <0x10000010 0x4>;
  81. #reset-cells = <1>;
  82. };
  83. ext_intc0: interrupt-controller@10000018 {
  84. #address-cells = <1>;
  85. compatible = "brcm,bcm6345-ext-intc";
  86. reg = <0x10000018 0x4>;
  87. interrupt-controller;
  88. #interrupt-cells = <2>;
  89. interrupt-parent = <&periph_intc>;
  90. interrupts = <BCM6368_IRQ_EXT0>,
  91. <BCM6368_IRQ_EXT1>,
  92. <BCM6368_IRQ_EXT2>,
  93. <BCM6368_IRQ_EXT3>;
  94. };
  95. ext_intc1: interrupt-controller@1000001c {
  96. #address-cells = <1>;
  97. compatible = "brcm,bcm6345-ext-intc";
  98. reg = <0x1000001c 0x4>;
  99. interrupt-controller;
  100. #interrupt-cells = <2>;
  101. interrupt-parent = <&periph_intc>;
  102. interrupts = <BCM6368_IRQ_EXT4>,
  103. <BCM6368_IRQ_EXT5>;
  104. };
  105. periph_intc: interrupt-controller@10000020 {
  106. #address-cells = <1>;
  107. compatible = "brcm,bcm6345-l1-intc";
  108. reg = <0x10000020 0x10>,
  109. <0x10000030 0x10>;
  110. interrupt-controller;
  111. #interrupt-cells = <1>;
  112. interrupt-parent = <&cpu_intc>;
  113. interrupts = <2>, <3>;
  114. };
  115. wdt: watchdog@1000005c {
  116. compatible = "brcm,bcm7038-wdt";
  117. reg = <0x1000005c 0xc>;
  118. clocks = <&periph_osc>;
  119. timeout-sec = <30>;
  120. };
  121. gpio_cntl: syscon@10000080 {
  122. #address-cells = <1>;
  123. #size-cells = <1>;
  124. compatible = "brcm,bcm6368-gpio-sysctl",
  125. "syscon", "simple-mfd";
  126. reg = <0x10000080 0x80>;
  127. ranges = <0 0x10000080 0x80>;
  128. native-endian;
  129. gpio: gpio@0 {
  130. compatible = "brcm,bcm6368-gpio";
  131. reg-names = "dirout", "dat";
  132. reg = <0x0 0x8>, <0x8 0x8>;
  133. gpio-controller;
  134. gpio-ranges = <&pinctrl 0 0 38>;
  135. #gpio-cells = <2>;
  136. };
  137. pinctrl: pinctrl@18 {
  138. compatible = "brcm,bcm6368-pinctrl";
  139. reg = <0x18 0x4>, <0x38 0x4>;
  140. pinctrl_analog_afe_0: analog_afe_0-pins {
  141. function = "analog_afe_0";
  142. pins = "gpio0";
  143. };
  144. pinctrl_analog_afe_1: analog_afe_1-pins {
  145. function = "analog_afe_1";
  146. pins = "gpio1";
  147. };
  148. pinctrl_sys_irq: sys_irq-pins {
  149. function = "sys_irq";
  150. pins = "gpio2";
  151. };
  152. pinctrl_serial_led: serial_led-pins {
  153. pinctrl_serial_led_data: serial_led_data-pins {
  154. function = "serial_led_data";
  155. pins = "gpio3";
  156. };
  157. pinctrl_serial_led_clk: serial_led_clk-pins {
  158. function = "serial_led_clk";
  159. pins = "gpio4";
  160. };
  161. };
  162. pinctrl_inet_led: inet_led-pins {
  163. function = "inet_led";
  164. pins = "gpio5";
  165. };
  166. pinctrl_ephy0_led: ephy0_led-pins {
  167. function = "ephy0_led";
  168. pins = "gpio6";
  169. };
  170. pinctrl_ephy1_led: ephy1_led-pins {
  171. function = "ephy1_led";
  172. pins = "gpio7";
  173. };
  174. pinctrl_ephy2_led: ephy2_led-pins {
  175. function = "ephy2_led";
  176. pins = "gpio8";
  177. };
  178. pinctrl_ephy3_led: ephy3_led-pins {
  179. function = "ephy3_led";
  180. pins = "gpio9";
  181. };
  182. pinctrl_robosw_led_data: robosw_led_data-pins {
  183. function = "robosw_led_data";
  184. pins = "gpio10";
  185. };
  186. pinctrl_robosw_led_clk: robosw_led_clk-pins {
  187. function = "robosw_led_clk";
  188. pins = "gpio11";
  189. };
  190. pinctrl_robosw_led0: robosw_led0-pins {
  191. function = "robosw_led0";
  192. pins = "gpio12";
  193. };
  194. pinctrl_robosw_led1: robosw_led1-pins {
  195. function = "robosw_led1";
  196. pins = "gpio13";
  197. };
  198. pinctrl_usb_device_led: usb_device_led-pins {
  199. function = "usb_device_led";
  200. pins = "gpio14";
  201. };
  202. pinctrl_pci: pci-pins {
  203. pinctrl_pci_req1: pci_req1-pins {
  204. function = "pci_req1";
  205. pins = "gpio16";
  206. };
  207. pinctrl_pci_gnt1: pci_gnt1-pins {
  208. function = "pci_gnt1";
  209. pins = "gpio17";
  210. };
  211. pinctrl_pci_intb: pci_intb-pins {
  212. function = "pci_intb";
  213. pins = "gpio18";
  214. };
  215. pinctrl_pci_req0: pci_req0-pins {
  216. function = "pci_req0";
  217. pins = "gpio19";
  218. };
  219. pinctrl_pci_gnt0: pci_gnt0-pins {
  220. function = "pci_gnt0";
  221. pins = "gpio20";
  222. };
  223. };
  224. pinctrl_pcmcia: pcmcia-pins {
  225. pinctrl_pcmcia_cd1: pcmcia_cd1-pins {
  226. function = "pcmcia_cd1";
  227. pins = "gpio22";
  228. };
  229. pinctrl_pcmcia_cd2: pcmcia_cd2-pins {
  230. function = "pcmcia_cd2";
  231. pins = "gpio23";
  232. };
  233. pinctrl_pcmcia_vs1: pcmcia_vs1-pins {
  234. function = "pcmcia_vs1";
  235. pins = "gpio24";
  236. };
  237. pinctrl_pcmcia_vs2: pcmcia_vs2-pins {
  238. function = "pcmcia_vs2";
  239. pins = "gpio25";
  240. };
  241. };
  242. pinctrl_ebi_cs2: ebi_cs2-pins {
  243. function = "ebi_cs2";
  244. pins = "gpio26";
  245. };
  246. pinctrl_ebi_cs3: ebi_cs3-pins {
  247. function = "ebi_cs3";
  248. pins = "gpio27";
  249. };
  250. pinctrl_spi_cs2: spi_cs2-pins {
  251. function = "spi_cs2";
  252. pins = "gpio28";
  253. };
  254. pinctrl_spi_cs3: spi_cs3-pins {
  255. function = "spi_cs3";
  256. pins = "gpio29";
  257. };
  258. pinctrl_spi_cs4: spi_cs4-pins {
  259. function = "spi_cs4";
  260. pins = "gpio30";
  261. };
  262. pinctrl_spi_cs5: spi_cs5-pins {
  263. function = "spi_cs5";
  264. pins = "gpio31";
  265. };
  266. pinctrl_uart1: uart1-pins {
  267. function = "uart1";
  268. group = "uart1_grp";
  269. };
  270. };
  271. };
  272. leds: led-controller@100000d0 {
  273. #address-cells = <1>;
  274. #size-cells = <0>;
  275. compatible = "brcm,bcm6358-leds";
  276. reg = <0x100000d0 0x8>;
  277. status = "disabled";
  278. };
  279. uart0: serial@10000100 {
  280. compatible = "brcm,bcm6345-uart";
  281. reg = <0x10000100 0x18>;
  282. interrupt-parent = <&periph_intc>;
  283. interrupts = <BCM6368_IRQ_UART0>;
  284. clocks = <&periph_osc>;
  285. clock-names = "periph";
  286. status = "disabled";
  287. };
  288. uart1: serial@10000120 {
  289. compatible = "brcm,bcm6345-uart";
  290. reg = <0x10000120 0x18>;
  291. interrupt-parent = <&periph_intc>;
  292. interrupts = <BCM6368_IRQ_UART1>;
  293. clocks = <&periph_osc>;
  294. clock-names = "periph";
  295. status = "disabled";
  296. };
  297. nflash: nand@10000200 {
  298. #address-cells = <1>;
  299. #size-cells = <0>;
  300. compatible = "brcm,nand-bcm6368",
  301. "brcm,brcmnand-v2.1",
  302. "brcm,brcmnand";
  303. reg = <0x10000200 0x180>,
  304. <0x10000600 0x200>,
  305. <0x10000070 0x10>;
  306. reg-names = "nand",
  307. "nand-cache",
  308. "nand-int-base";
  309. interrupt-parent = <&periph_intc>;
  310. interrupts = <BCM6368_IRQ_NAND>;
  311. clocks = <&periph_clk BCM6368_CLK_NAND>;
  312. clock-names = "nand";
  313. status = "disabled";
  314. };
  315. lsspi: spi@10000800 {
  316. #address-cells = <1>;
  317. #size-cells = <0>;
  318. compatible = "brcm,bcm6358-spi";
  319. reg = <0x10000800 0x70c>;
  320. interrupt-parent = <&periph_intc>;
  321. interrupts = <BCM6368_IRQ_SPI>;
  322. clocks = <&periph_clk BCM6368_CLK_SPI>;
  323. clock-names = "spi";
  324. resets = <&periph_rst BCM6368_RST_SPI>;
  325. status = "disabled";
  326. };
  327. pci: pci@10001000 {
  328. compatible = "brcm,bcm6348-pci";
  329. reg = <0x10001000 0x200>;
  330. #address-cells = <3>;
  331. #size-cells = <2>;
  332. device_type = "pci";
  333. bus-range = <0x00 0x01>;
  334. ranges = <0x2000000 0 0x30000000 0x30000000 0 0x8000000>,
  335. <0x1000000 0 0x08000000 0x08000000 0 0x0010000>;
  336. linux,pci-probe-only = <1>;
  337. interrupt-parent = <&periph_intc>;
  338. interrupts = <BCM6368_IRQ_MPI>;
  339. resets = <&periph_rst BCM6368_RST_MPI>;
  340. reset-names = "pci";
  341. pinctrl-names = "default";
  342. pinctrl-0 = <&pinctrl_pci>;
  343. brcm,remap;
  344. status = "disabled";
  345. };
  346. ehci: usb@10001500 {
  347. compatible = "brcm,bcm6368-ehci", "generic-ehci";
  348. reg = <0x10001500 0x100>;
  349. big-endian;
  350. spurious-oc;
  351. interrupt-parent = <&periph_intc>;
  352. interrupts = <BCM6368_IRQ_EHCI>;
  353. phys = <&usbh 0>;
  354. phy-names = "usb";
  355. status = "disabled";
  356. };
  357. ohci: usb@10001600 {
  358. compatible = "brcm,bcm6368-ohci", "generic-ohci";
  359. reg = <0x10001600 0x100>;
  360. big-endian;
  361. no-big-frame-no;
  362. interrupt-parent = <&periph_intc>;
  363. interrupts = <BCM6368_IRQ_OHCI>;
  364. phys = <&usbh 0>;
  365. phy-names = "usb";
  366. status = "disabled";
  367. };
  368. usbh: usb-phy@10001700 {
  369. compatible = "brcm,bcm6368-usbh-phy";
  370. reg = <0x10001700 0x38>;
  371. #phy-cells = <1>;
  372. clocks = <&periph_clk BCM6368_CLK_USBH>;
  373. clock-names = "usbh";
  374. resets = <&periph_rst BCM6368_RST_USBH>;
  375. status = "disabled";
  376. };
  377. random: rng@10004180 {
  378. compatible = "brcm,bcm6368-rng";
  379. reg = <0x10004180 0x14>;
  380. clocks = <&periph_clk BCM6368_CLK_IPSEC>;
  381. clock-names = "ipsec";
  382. resets = <&periph_rst BCM6368_RST_IPSEC>;
  383. };
  384. ethernet: ethernet@10006800 {
  385. compatible = "brcm,bcm6368-enetsw";
  386. reg = <0x10006800 0x80>,
  387. <0x10006a00 0x80>,
  388. <0x10006c00 0x80>;
  389. reg-names = "dma",
  390. "dma-channels",
  391. "dma-sram";
  392. interrupt-parent = <&periph_intc>;
  393. interrupts = <BCM6368_IRQ_ENETSW_RX_DMA0>,
  394. <BCM6368_IRQ_ENETSW_TX_DMA0>;
  395. interrupt-names = "rx",
  396. "tx";
  397. clocks = <&periph_clk BCM6368_CLK_SWPKT_USB>,
  398. <&periph_clk BCM6368_CLK_SWPKT_SAR>,
  399. <&periph_clk BCM6368_CLK_ROBOSW>;
  400. resets = <&periph_rst BCM6368_RST_SWITCH>,
  401. <&periph_rst BCM6368_RST_EPHY>;
  402. dma-rx = <0>;
  403. dma-tx = <1>;
  404. status = "disabled";
  405. };
  406. switch0: switch@10f00000 {
  407. #address-cells = <1>;
  408. #size-cells = <0>;
  409. compatible = "brcm,bcm6368-switch";
  410. reg = <0x10f00000 0x8000>;
  411. big-endian;
  412. ports {
  413. #address-cells = <1>;
  414. #size-cells = <0>;
  415. port@8 {
  416. reg = <8>;
  417. phy-mode = "internal";
  418. ethernet = <&ethernet>;
  419. fixed-link {
  420. speed = <1000>;
  421. full-duplex;
  422. };
  423. };
  424. };
  425. };
  426. mdio: mdio@10f000b0 {
  427. #address-cells = <1>;
  428. #size-cells = <0>;
  429. compatible = "brcm,bcm6368-mdio-mux";
  430. reg = <0x10f000b0 0x8>;
  431. mdio_int: mdio@0 {
  432. #address-cells = <1>;
  433. #size-cells = <0>;
  434. reg = <0>;
  435. phy1: ethernet-phy@1 {
  436. compatible = "ethernet-phy-ieee802.3-c22";
  437. reg = <1>;
  438. };
  439. phy2: ethernet-phy@2 {
  440. compatible = "ethernet-phy-ieee802.3-c22";
  441. reg = <2>;
  442. };
  443. phy3: ethernet-phy@3 {
  444. compatible = "ethernet-phy-ieee802.3-c22";
  445. reg = <3>;
  446. };
  447. phy4: ethernet-phy@4 {
  448. compatible = "ethernet-phy-ieee802.3-c22";
  449. reg = <4>;
  450. };
  451. };
  452. mdio_ext: mdio@1 {
  453. #address-cells = <1>;
  454. #size-cells = <0>;
  455. reg = <1>;
  456. };
  457. };
  458. };
  459. pflash: nor@18000000 {
  460. #address-cells = <1>;
  461. #size-cells = <1>;
  462. compatible = "cfi-flash";
  463. reg = <0x18000000 0x2000000>;
  464. bank-width = <2>;
  465. status = "disabled";
  466. };
  467. };