qcom-ipq8064-onhub.dtsi 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2014 The ChromiumOS Authors
  4. */
  5. #include "qcom-ipq8064-smb208.dtsi"
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/input/input.h>
  8. #include <dt-bindings/soc/qcom,tcsr.h>
  9. / {
  10. aliases {
  11. ethernet0 = &gmac0;
  12. ethernet1 = &gmac2;
  13. mdio-gpio0 = &mdio;
  14. serial0 = &gsbi4_serial;
  15. };
  16. chosen {
  17. stdout-path = "serial0:115200n8";
  18. };
  19. reserved-memory {
  20. #address-cells = <1>;
  21. #size-cells = <1>;
  22. ranges;
  23. rsvd@41200000 {
  24. reg = <0x41200000 0x300000>;
  25. no-map;
  26. };
  27. };
  28. keys {
  29. compatible = "gpio-keys";
  30. pinctrl-0 = <&button_pins>;
  31. pinctrl-names = "default";
  32. reset {
  33. label = "reset";
  34. gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
  35. linux,code = <KEY_RESTART>;
  36. debounce-interval = <60>;
  37. wakeup-source;
  38. };
  39. dev {
  40. label = "dev";
  41. gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
  42. linux,code = <KEY_CONFIG>;
  43. debounce-interval = <60>;
  44. wakeup-source;
  45. };
  46. };
  47. mdio: mdio {
  48. compatible = "virtual,mdio-gpio";
  49. #address-cells = <1>;
  50. #size-cells = <0>;
  51. gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
  52. <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
  53. pinctrl-0 = <&mdio_pins>;
  54. pinctrl-names = "default";
  55. phy0: ethernet-phy@0 {
  56. reg = <0>;
  57. qca,ar8327-initvals = <
  58. 0x00004 0x7600000 /* PAD0_MODE */
  59. 0x00008 0x1000000 /* PAD5_MODE */
  60. 0x0000c 0x80 /* PAD6_MODE */
  61. 0x000e4 0xaa545 /* MAC_POWER_SEL */
  62. 0x000e0 0xc74164de /* SGMII_CTRL */
  63. 0x0007c 0x4e /* PORT0_STATUS */
  64. 0x00094 0x4e /* PORT6_STATUS */
  65. >;
  66. };
  67. phy1: ethernet-phy@1 {
  68. reg = <1>;
  69. };
  70. };
  71. soc {
  72. rng@1a500000 {
  73. status = "disabled";
  74. };
  75. sound {
  76. compatible = "google,storm-audio";
  77. qcom,model = "ipq806x-storm";
  78. cpu = <&lpass>;
  79. codec = <&max98357a>;
  80. };
  81. lpass: lpass@28100000 {
  82. status = "okay";
  83. pinctrl-names = "default", "idle";
  84. pinctrl-0 = <&mi2s_default>;
  85. pinctrl-1 = <&mi2s_idle>;
  86. };
  87. max98357a: max98357a {
  88. compatible = "maxim,max98357a";
  89. #sound-dai-cells = <1>;
  90. pinctrl-names = "default";
  91. pinctrl-0 = <&sdmode_pins>;
  92. sdmode-gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
  93. };
  94. };
  95. };
  96. &qcom_pinmux {
  97. rgmii0_pins: rgmii0_pins {
  98. mux {
  99. pins = "gpio2", "gpio66";
  100. drive-strength = <8>;
  101. bias-disable;
  102. };
  103. };
  104. mi2s_pins {
  105. mi2s_default: mi2s_default {
  106. dout {
  107. pins = "gpio32";
  108. function = "mi2s";
  109. drive-strength = <16>;
  110. bias-disable;
  111. };
  112. sync {
  113. pins = "gpio27";
  114. function = "mi2s";
  115. drive-strength = <16>;
  116. bias-disable;
  117. };
  118. clk {
  119. pins = "gpio28";
  120. function = "mi2s";
  121. drive-strength = <16>;
  122. bias-disable;
  123. };
  124. };
  125. mi2s_idle: mi2s_idle {
  126. dout {
  127. pins = "gpio32";
  128. function = "mi2s";
  129. drive-strength = <2>;
  130. bias-pull-down;
  131. };
  132. sync {
  133. pins = "gpio27";
  134. function = "mi2s";
  135. drive-strength = <2>;
  136. bias-pull-down;
  137. };
  138. clk {
  139. pins = "gpio28";
  140. function = "mi2s";
  141. drive-strength = <2>;
  142. bias-pull-down;
  143. };
  144. };
  145. };
  146. mdio_pins: mdio_pins {
  147. mux {
  148. pins = "gpio0", "gpio1";
  149. function = "gpio";
  150. drive-strength = <8>;
  151. bias-disable;
  152. };
  153. rst {
  154. pins = "gpio26";
  155. output-low;
  156. };
  157. };
  158. sdmode_pins: sdmode_pinmux {
  159. pins = "gpio25";
  160. function = "gpio";
  161. drive-strength = <16>;
  162. bias-disable;
  163. };
  164. sdcc1_pins: sdcc1_pinmux {
  165. mux {
  166. pins = "gpio38", "gpio39", "gpio40",
  167. "gpio41", "gpio42", "gpio43",
  168. "gpio44", "gpio45", "gpio46",
  169. "gpio47";
  170. function = "sdc1";
  171. };
  172. cmd {
  173. pins = "gpio45";
  174. drive-strength = <10>;
  175. bias-pull-up;
  176. };
  177. data {
  178. pins = "gpio38", "gpio39", "gpio40",
  179. "gpio41", "gpio43", "gpio44",
  180. "gpio46", "gpio47";
  181. drive-strength = <10>;
  182. bias-pull-up;
  183. };
  184. clk {
  185. pins = "gpio42";
  186. drive-strength = <16>;
  187. bias-pull-down;
  188. };
  189. };
  190. i2c1_pins: i2c1_pinmux {
  191. pins = "gpio53", "gpio54";
  192. function = "gsbi1";
  193. bias-disable;
  194. };
  195. rpm_i2c_pinmux: rpm_i2c_pinmux {
  196. mux {
  197. pins = "gpio12", "gpio13";
  198. function = "gsbi4";
  199. drive-strength = <12>;
  200. bias-disable;
  201. };
  202. };
  203. spi_pins: spi_pins {
  204. mux {
  205. pins = "gpio18", "gpio19", "gpio21";
  206. function = "gsbi5";
  207. bias-pull-down;
  208. /delete-property/ bias-none;
  209. /delete-property/ drive-strength;
  210. };
  211. data {
  212. pins = "gpio18", "gpio19";
  213. drive-strength = <10>;
  214. };
  215. cs {
  216. pins = "gpio20";
  217. drive-strength = <10>;
  218. bias-pull-up;
  219. };
  220. clk {
  221. pins = "gpio21";
  222. drive-strength = <12>;
  223. };
  224. };
  225. fw_pinmux {
  226. wp {
  227. pins = "gpio17";
  228. output-low;
  229. };
  230. };
  231. button_pins: button_pins {
  232. recovery {
  233. pins = "gpio16";
  234. function = "gpio";
  235. bias-none;
  236. };
  237. developer {
  238. pins = "gpio15";
  239. function = "gpio";
  240. bias-none;
  241. };
  242. };
  243. spi6_pins: spi6_pins {
  244. mux {
  245. pins = "gpio55", "gpio56", "gpio58";
  246. function = "gsbi6";
  247. bias-pull-down;
  248. };
  249. data {
  250. pins = "gpio55", "gpio56";
  251. drive-strength = <10>;
  252. };
  253. cs {
  254. pins = "gpio57";
  255. drive-strength = <10>;
  256. bias-pull-up;
  257. output-high;
  258. };
  259. clk {
  260. pins = "gpio58";
  261. drive-strength = <12>;
  262. };
  263. };
  264. };
  265. &gmac0 {
  266. status = "okay";
  267. phy-mode = "rgmii";
  268. qcom,id = <0>;
  269. phy-handle = <&phy1>;
  270. pinctrl-0 = <&rgmii0_pins>;
  271. pinctrl-names = "default";
  272. fixed-link {
  273. speed = <1000>;
  274. full-duplex;
  275. };
  276. };
  277. &gmac2 {
  278. status = "okay";
  279. phy-mode = "sgmii";
  280. qcom,id = <2>;
  281. phy-handle = <&phy0>;
  282. fixed-link {
  283. speed = <1000>;
  284. full-duplex;
  285. };
  286. };
  287. &gsbi1 {
  288. status = "okay";
  289. qcom,mode = <GSBI_PROT_I2C_UART>;
  290. };
  291. &gsbi1_i2c {
  292. status = "okay";
  293. clock-frequency = <100000>;
  294. pinctrl-0 = <&i2c1_pins>;
  295. pinctrl-names = "default";
  296. tpm@20 {
  297. compatible = "infineon,slb9645tt";
  298. reg = <0x20>;
  299. powered-while-suspended;
  300. };
  301. };
  302. &gsbi4 {
  303. status = "okay";
  304. qcom,mode = <GSBI_PROT_I2C_UART>;
  305. };
  306. &gsbi4_serial {
  307. status = "okay";
  308. };
  309. &gsbi5 {
  310. status = "okay";
  311. qcom,mode = <GSBI_PROT_SPI>;
  312. spi4: spi@1a280000 {
  313. status = "okay";
  314. spi-max-frequency = <50000000>;
  315. pinctrl-0 = <&spi_pins>;
  316. pinctrl-names = "default";
  317. cs-gpios = <&qcom_pinmux 20 0>;
  318. flash: flash@0 {
  319. compatible = "jedec,spi-nor";
  320. spi-max-frequency = <50000000>;
  321. reg = <0>;
  322. };
  323. };
  324. };
  325. &gsbi6 {
  326. status = "okay";
  327. qcom,mode = <GSBI_PROT_SPI>;
  328. };
  329. &gsbi6_spi {
  330. status = "okay";
  331. spi-max-frequency = <25000000>;
  332. pinctrl-0 = <&spi6_pins>;
  333. pinctrl-names = "default";
  334. cs-gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
  335. dmas = <&adm_dma 8 0xb>,
  336. <&adm_dma 7 0x14>;
  337. dma-names = "rx", "tx";
  338. /*
  339. * This "spidev" was included in the manufacturer device tree. I suspect
  340. * it's the (unused) Zigbee radio -- SiliconLabs EM3581 Zigbee? There's
  341. * no driver or binding for this at the moment.
  342. */
  343. spidev@0 {
  344. compatible = "spidev";
  345. reg = <0>;
  346. spi-max-frequency = <25000000>;
  347. };
  348. };
  349. &pcie0 {
  350. status = "okay";
  351. pcie@0 {
  352. reg = <0 0 0 0 0>;
  353. #interrupt-cells = <1>;
  354. #size-cells = <2>;
  355. #address-cells = <3>;
  356. device_type = "pci";
  357. ath10k@0,0 {
  358. reg = <0 0 0 0 0>;
  359. device_type = "pci";
  360. qcom,ath10k-sa-gpio = <2 3 4 0>;
  361. qcom,ath10k-sa-gpio-func = <5 5 5 0>;
  362. };
  363. };
  364. };
  365. &pcie1 {
  366. status = "okay";
  367. pcie@0 {
  368. reg = <0 0 0 0 0>;
  369. #interrupt-cells = <1>;
  370. #size-cells = <2>;
  371. #address-cells = <3>;
  372. device_type = "pci";
  373. ath10k@0,0 {
  374. reg = <0 0 0 0 0>;
  375. device_type = "pci";
  376. qcom,ath10k-sa-gpio = <2 3 4 0>;
  377. qcom,ath10k-sa-gpio-func = <5 5 5 0>;
  378. };
  379. };
  380. };
  381. &pcie2 {
  382. status = "okay";
  383. pcie@0 {
  384. reg = <0 0 0 0 0>;
  385. #interrupt-cells = <1>;
  386. #size-cells = <2>;
  387. #address-cells = <3>;
  388. device_type = "pci";
  389. ath10k@0,0 {
  390. reg = <0 0 0 0 0>;
  391. device_type = "pci";
  392. };
  393. };
  394. };
  395. &rpm {
  396. pinctrl-0 = <&rpm_i2c_pinmux>;
  397. pinctrl-names = "default";
  398. };
  399. &sdcc1 {
  400. status = "okay";
  401. pinctrl-0 = <&sdcc1_pins>;
  402. pinctrl-names = "default";
  403. /delete-property/ mmc-ddr-1_8v;
  404. };
  405. &tcsr {
  406. compatible = "qcom,tcsr-ipq8064", "qcom,tcsr", "syscon";
  407. qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
  408. };
  409. &hs_phy_0 {
  410. status = "okay";
  411. };
  412. &ss_phy_0 {
  413. status = "okay";
  414. };
  415. &usb3_0 {
  416. status = "okay";
  417. };
  418. &hs_phy_1 {
  419. status = "okay";
  420. };
  421. &ss_phy_1 {
  422. status = "okay";
  423. };
  424. &usb3_1 {
  425. status = "okay";
  426. };