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- From 512ea2edfe15ffa2cd839b3a31d768145f2edc20 Mon Sep 17 00:00:00 2001
- From: Ansuel Smith <[email protected]>
- Date: Sat, 26 Feb 2022 14:52:27 +0100
- Subject: [PATCH 07/14] clk: qcom: gcc-ipq806x: add additional freq nss cores
- Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be
- clocked to 800MHz. Add these missing freq to the gcc driver.
- Set the freq_tbl for the ubi32_cores to the correct values based on the
- machine compatible.
- Signed-off-by: Ansuel Smith <[email protected]>
- Reviewed-by: Stephen Boyd <[email protected]>
- Tested-by: Jonathan McDowell <[email protected]>
- Signed-off-by: Bjorn Andersson <[email protected]>
- Link: https://lore.kernel.org/r/[email protected]
- ---
- drivers/clk/qcom/gcc-ipq806x.c | 24 +++++++++++++++++++++---
- 1 file changed, 21 insertions(+), 3 deletions(-)
- --- a/drivers/clk/qcom/gcc-ipq806x.c
- +++ b/drivers/clk/qcom/gcc-ipq806x.c
- @@ -232,7 +232,9 @@ static struct clk_regmap pll14_vote = {
-
- static struct pll_freq_tbl pll18_freq_tbl[] = {
- NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
- + NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
- NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
- + NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
- };
-
- static struct clk_pll pll18 = {
- @@ -2698,7 +2700,7 @@ static struct clk_branch nss_tcm_clk = {
- },
- };
-
- -static const struct freq_tbl clk_tbl_nss[] = {
- +static const struct freq_tbl clk_tbl_nss_ipq8064[] = {
- { 110000000, P_PLL18, 1, 1, 5 },
- { 275000000, P_PLL18, 2, 0, 0 },
- { 550000000, P_PLL18, 1, 0, 0 },
- @@ -2706,6 +2708,14 @@ static const struct freq_tbl clk_tbl_nss
- { }
- };
-
- +static const struct freq_tbl clk_tbl_nss_ipq8065[] = {
- + { 110000000, P_PLL18, 1, 1, 5 },
- + { 275000000, P_PLL18, 2, 0, 0 },
- + { 600000000, P_PLL18, 1, 0, 0 },
- + { 800000000, P_PLL18, 1, 0, 0 },
- + { }
- +};
- +
- static struct clk_dyn_rcg ubi32_core1_src_clk = {
- .ns_reg[0] = 0x3d2c,
- .ns_reg[1] = 0x3d30,
- @@ -2745,7 +2755,7 @@ static struct clk_dyn_rcg ubi32_core1_sr
- .pre_div_width = 2,
- },
- .mux_sel_bit = 0,
- - .freq_tbl = clk_tbl_nss,
- + /* nss freq table is selected based on the SoC compatible */
- .clkr = {
- .enable_reg = 0x3d20,
- .enable_mask = BIT(1),
- @@ -2798,7 +2808,7 @@ static struct clk_dyn_rcg ubi32_core2_sr
- .pre_div_width = 2,
- },
- .mux_sel_bit = 0,
- - .freq_tbl = clk_tbl_nss,
- + /* nss freq table is selected based on the SoC compatible */
- .clkr = {
- .enable_reg = 0x3d40,
- .enable_mask = BIT(1),
- @@ -3131,6 +3141,14 @@ static int gcc_ipq806x_probe(struct plat
- if (ret)
- return ret;
-
- + if (of_machine_is_compatible("qcom,ipq8065")) {
- + ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
- + ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
- + } else {
- + ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
- + ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
- + }
- +
- ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
- if (ret)
- return ret;
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