106-v6.1-01-ARM-dts-qcom-ipq8064-add-v2-dtsi-variant.patch 2.8 KB

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  1. From 9f7097a8b1948533a6db1b53b5c0480cc75bbd16 Mon Sep 17 00:00:00 2001
  2. From: Christian Marangi <[email protected]>
  3. Date: Mon, 18 Jul 2022 18:05:16 +0200
  4. Subject: [PATCH 1/3] ARM: dts: qcom: ipq8064: add v2 dtsi variant
  5. Add ipq8064-v2.0 dtsi variant that differ from original ipq8064 SoC for
  6. some additional pcie, sata and usb configuration values, additional
  7. reserved memory and serial output.
  8. Signed-off-by: Christian Marangi <[email protected]>
  9. ---
  10. .../boot/dts/qcom-ipq8064-v2.0-smb208.dtsi | 37 ++++++++++
  11. arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 69 +++++++++++++++++++
  12. 2 files changed, 106 insertions(+)
  13. create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
  14. create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
  15. --- /dev/null
  16. +++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
  17. @@ -0,0 +1,37 @@
  18. +// SPDX-License-Identifier: GPL-2.0
  19. +
  20. +#include "qcom-ipq8064-v2.0.dtsi"
  21. +
  22. +&rpm {
  23. + smb208_regulators: regulators {
  24. + compatible = "qcom,rpm-smb208-regulators";
  25. +
  26. + smb208_s1a: s1a {
  27. + regulator-min-microvolt = <1050000>;
  28. + regulator-max-microvolt = <1150000>;
  29. +
  30. + qcom,switch-mode-frequency = <1200000>;
  31. + };
  32. +
  33. + smb208_s1b: s1b {
  34. + regulator-min-microvolt = <1050000>;
  35. + regulator-max-microvolt = <1150000>;
  36. +
  37. + qcom,switch-mode-frequency = <1200000>;
  38. + };
  39. +
  40. + smb208_s2a: s2a {
  41. + regulator-min-microvolt = < 800000>;
  42. + regulator-max-microvolt = <1250000>;
  43. +
  44. + qcom,switch-mode-frequency = <1200000>;
  45. + };
  46. +
  47. + smb208_s2b: s2b {
  48. + regulator-min-microvolt = < 800000>;
  49. + regulator-max-microvolt = <1250000>;
  50. +
  51. + qcom,switch-mode-frequency = <1200000>;
  52. + };
  53. + };
  54. +};
  55. --- /dev/null
  56. +++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
  57. @@ -0,0 +1,69 @@
  58. +// SPDX-License-Identifier: GPL-2.0
  59. +
  60. +#include "qcom-ipq8064.dtsi"
  61. +
  62. +/ {
  63. + model = "Qualcomm Technologies, Inc. IPQ8064-v2.0";
  64. +
  65. + aliases {
  66. + serial0 = &gsbi4_serial;
  67. + };
  68. +
  69. + chosen {
  70. + stdout-path = "serial0:115200n8";
  71. + };
  72. +
  73. + reserved-memory {
  74. + #address-cells = <1>;
  75. + #size-cells = <1>;
  76. + ranges;
  77. +
  78. + rsvd@41200000 {
  79. + reg = <0x41200000 0x300000>;
  80. + no-map;
  81. + };
  82. + };
  83. +};
  84. +
  85. +&gsbi4 {
  86. + qcom,mode = <GSBI_PROT_I2C_UART>;
  87. + status = "okay";
  88. +
  89. + serial@16340000 {
  90. + status = "okay";
  91. + };
  92. + /*
  93. + * The i2c device on gsbi4 should not be enabled.
  94. + * On ipq806x designs gsbi4 i2c is meant for exclusive
  95. + * RPM usage. Turning this on in kernel manifests as
  96. + * i2c failure for the RPM.
  97. + */
  98. +};
  99. +
  100. +&pcie0 {
  101. + compatible = "qcom,pcie-ipq8064-v2";
  102. +};
  103. +
  104. +&pcie1 {
  105. + compatible = "qcom,pcie-ipq8064-v2";
  106. +};
  107. +
  108. +&pcie2 {
  109. + compatible = "qcom,pcie-ipq8064-v2";
  110. +};
  111. +
  112. +&sata {
  113. + ports-implemented = <0x1>;
  114. +};
  115. +
  116. +&ss_phy_0 {
  117. + qcom,rx-eq = <2>;
  118. + qcom,tx-deamp_3_5db = <32>;
  119. + qcom,mpll = <5>;
  120. +};
  121. +
  122. +&ss_phy_1 {
  123. + qcom,rx-eq = <2>;
  124. + qcom,tx-deamp_3_5db = <32>;
  125. + qcom,mpll = <5>;
  126. +};