mt7986a-acelink-ew-7886cax.dts 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only OR MIT
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/leds/common.h>
  6. #include "mt7986a.dtsi"
  7. / {
  8. compatible = "acelink,ew-7886cax", "mediatek,mt7986a";
  9. model = "Acelink EW-7886CAX";
  10. aliases {
  11. serial0 = &uart0;
  12. led-boot = &led_status_blue;
  13. led-running = &led_status_green;
  14. led-upgrade = &led_status_red;
  15. led-failsafe = &led_status_red;
  16. };
  17. chosen {
  18. stdout-path = "serial0:115200n8";
  19. };
  20. memory@40000000 {
  21. reg = <0 0x40000000 0 0x20000000>;
  22. device_type = "memory";
  23. };
  24. keys {
  25. compatible = "gpio-keys";
  26. key-restart {
  27. label = "Reset";
  28. gpios = <&pio 7 GPIO_ACTIVE_LOW>;
  29. linux,code = <KEY_RESTART>;
  30. };
  31. };
  32. leds {
  33. compatible = "gpio-leds";
  34. led_status_red: led-0 {
  35. function = LED_FUNCTION_STATUS;
  36. color = <LED_COLOR_ID_RED>;
  37. gpios = <&pio 18 GPIO_ACTIVE_HIGH>;
  38. };
  39. led_status_green: led-1 {
  40. function = LED_FUNCTION_STATUS;
  41. color = <LED_COLOR_ID_GREEN>;
  42. gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
  43. };
  44. led_status_blue: led-2 {
  45. function = LED_FUNCTION_STATUS;
  46. color = <LED_COLOR_ID_BLUE>;
  47. gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
  48. };
  49. };
  50. };
  51. &crypto {
  52. status = "okay";
  53. };
  54. &eth {
  55. status = "okay";
  56. mac@1 {
  57. compatible = "mediatek,eth-mac";
  58. reg = <1>;
  59. phy-mode = "2500base-x";
  60. phy-handle = <&phy6>;
  61. nvmem-cells = <&macaddr>;
  62. nvmem-cell-names = "mac-address";
  63. };
  64. mdio-bus {
  65. reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
  66. reset-delay-us = <50000>;
  67. reset-post-delay-us = <20000>;
  68. #address-cells = <1>;
  69. #size-cells = <0>;
  70. /* Maxlinear GPY211C */
  71. phy6: phy@6 {
  72. compatible = "ethernet-phy-ieee802.3-c45";
  73. reg = <6>;
  74. };
  75. };
  76. };
  77. &pcie_phy {
  78. status = "okay";
  79. };
  80. &pio {
  81. spi_flash_pins: spi-flash-pins-33-to-38 {
  82. mux {
  83. function = "spi";
  84. groups = "spi0", "spi0_wp_hold";
  85. };
  86. conf-pu {
  87. pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
  88. drive-strength = <8>;
  89. mediatek,pull-up-adv = <0>; /* bias-disable */
  90. };
  91. conf-pd {
  92. pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
  93. drive-strength = <8>;
  94. mediatek,pull-down-adv = <0>; /* bias-disable */
  95. };
  96. };
  97. wf_2g_5g_pins: wf_2g_5g-pins {
  98. mux {
  99. function = "wifi";
  100. groups = "wf_2g", "wf_5g";
  101. };
  102. conf {
  103. pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  104. "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  105. "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  106. "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
  107. "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
  108. "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
  109. "WF1_TOP_CLK", "WF1_TOP_DATA";
  110. drive-strength = <4>;
  111. };
  112. };
  113. wf_dbdc_pins: wf-dbdc-pins {
  114. mux {
  115. function = "wifi";
  116. groups = "wf_dbdc";
  117. };
  118. conf {
  119. pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  120. "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  121. "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  122. "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
  123. "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
  124. "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
  125. "WF1_TOP_CLK", "WF1_TOP_DATA";
  126. drive-strength = <4>;
  127. };
  128. };
  129. };
  130. &spi0 {
  131. pinctrl-names = "default";
  132. pinctrl-0 = <&spi_flash_pins>;
  133. status = "okay";
  134. flash@0 {
  135. compatible = "spi-nand";
  136. reg = <0>;
  137. #address-cells = <1>;
  138. #size-cells = <1>;
  139. spi-max-frequency = <52000000>;
  140. spi-rx-bus-width = <4>;
  141. spi-tx-bus-width = <4>;
  142. mediatek,nmbm;
  143. mediatek,bmt-max-ratio = <1>;
  144. mediatek,bmt-max-reserved-blocks = <64>;
  145. partitions {
  146. compatible = "fixed-partitions";
  147. #address-cells = <1>;
  148. #size-cells = <1>;
  149. partition@0 {
  150. reg = <0x0 0x100000>;
  151. label = "bootloader";
  152. read-only;
  153. };
  154. partition@100000 {
  155. reg = <0x100000 0x80000>;
  156. label = "u-boot-env";
  157. };
  158. partition@180000 {
  159. compatible = "nvmem-cells";
  160. reg = <0x180000 0x200000>;
  161. label = "factory";
  162. read-only;
  163. nvmem-layout {
  164. compatible = "fixed-layout";
  165. #address-cells = <1>;
  166. #size-cells = <1>;
  167. eeprom: eeprom@0 {
  168. reg = <0x0 0x1000>;
  169. };
  170. macaddr: macaddr@4 {
  171. reg = <0x4 0x6>;
  172. };
  173. };
  174. };
  175. partition@380000 {
  176. reg = <0x380000 0x200000>;
  177. label = "fip";
  178. };
  179. partition@580000 {
  180. reg = <0x580000 0x4000000>;
  181. label = "ubi";
  182. };
  183. };
  184. };
  185. };
  186. &trng {
  187. status = "okay";
  188. };
  189. &uart0 {
  190. status = "okay";
  191. };
  192. &watchdog {
  193. status = "okay";
  194. };
  195. &wifi {
  196. pinctrl-names = "default", "dbdc";
  197. pinctrl-0 = <&wf_2g_5g_pins>;
  198. pinctrl-1 = <&wf_dbdc_pins>;
  199. nvmem-cells = <&eeprom>;
  200. nvmem-cell-names = "eeprom";
  201. status = "okay";
  202. };