ArcherC20v1.dts 3.2 KB

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  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. / {
  6. compatible = "tplink,c20-v1", "ralink,mt7620a-soc";
  7. model = "TP-Link Archer C20 v1";
  8. aliases {
  9. led-boot = &led_power;
  10. led-failsafe = &led_power;
  11. led-running = &led_power;
  12. led-upgrade = &led_power;
  13. };
  14. chosen {
  15. bootargs = "console=ttyS0,115200";
  16. };
  17. leds {
  18. compatible = "gpio-leds";
  19. lan {
  20. label = "c20-v1:blue:lan";
  21. gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
  22. };
  23. led_power: power {
  24. label = "c20-v1:blue:power";
  25. gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
  26. default-state = "keep";
  27. };
  28. usb {
  29. label = "c20-v1:blue:usb";
  30. gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
  31. trigger-sources = <&ohci_port1>, <&ehci_port1>;
  32. linux,default-trigger = "usbport";
  33. };
  34. wan {
  35. label = "c20-v1:blue:wan";
  36. gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
  37. };
  38. wan_orange {
  39. label = "c20-v1:orange:wan";
  40. gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
  41. };
  42. wlan5g {
  43. label = "c20-v1:blue:wlan5g";
  44. gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
  45. };
  46. wlan2g {
  47. label = "c20-v1:blue:wlan2g";
  48. gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
  49. };
  50. wps {
  51. label = "c20-v1:blue:wps";
  52. gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  53. };
  54. };
  55. keys {
  56. compatible = "gpio-keys-polled";
  57. poll-interval = <20>;
  58. reset {
  59. label = "reset";
  60. gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
  61. linux,code = <KEY_RESTART>;
  62. };
  63. rfkill {
  64. label = "rfkill";
  65. gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
  66. linux,code = <KEY_RFKILL>;
  67. };
  68. };
  69. };
  70. &gpio1 {
  71. status = "okay";
  72. };
  73. &gpio2 {
  74. status = "okay";
  75. };
  76. &gpio3 {
  77. status = "okay";
  78. };
  79. &spi0 {
  80. status = "okay";
  81. m25p80@0 {
  82. compatible = "jedec,spi-nor";
  83. reg = <0>;
  84. spi-max-frequency = <10000000>;
  85. partitions {
  86. compatible = "fixed-partitions";
  87. #address-cells = <1>;
  88. #size-cells = <1>;
  89. partition@0 {
  90. label = "u-boot";
  91. reg = <0x0 0x20000>;
  92. read-only;
  93. };
  94. partition@20000 {
  95. compatible = "tplink,firmware";
  96. label = "firmware";
  97. reg = <0x20000 0x7a0000>;
  98. };
  99. partition@7c0000 {
  100. label = "config";
  101. reg = <0x7c0000 0x10000>;
  102. read-only;
  103. };
  104. rom: partition@7d0000 {
  105. label = "rom";
  106. reg = <0x7d0000 0x10000>;
  107. read-only;
  108. };
  109. partition@7e0000 {
  110. label = "romfile";
  111. reg = <0x7e0000 0x10000>;
  112. read-only;
  113. };
  114. radio: partition@7f0000 {
  115. label = "radio";
  116. reg = <0x7f0000 0x10000>;
  117. read-only;
  118. };
  119. };
  120. };
  121. };
  122. &pinctrl {
  123. state_default: pinctrl0 {
  124. gpio {
  125. ralink,group = "i2c", "uartf", "wled", "ephy", "spi refclk", "wdt";
  126. ralink,function = "gpio";
  127. };
  128. };
  129. };
  130. &ethernet {
  131. pinctrl-names = "default";
  132. mtd-mac-address = <&rom 0xf100>;
  133. mediatek,portmap = "wllll";
  134. };
  135. &ehci {
  136. status = "okay";
  137. };
  138. &ohci {
  139. status = "okay";
  140. };
  141. &gsw {
  142. mediatek,port4 = "ephy";
  143. };
  144. &wmac {
  145. ralink,mtd-eeprom = <&radio 0>;
  146. mtd-mac-address = <&rom 0xf100>;
  147. mtd-mac-address-increment = <(-2)>;
  148. pinctrl-names = "default";
  149. pinctrl-0 = <&pa_pins>;
  150. };
  151. &pcie {
  152. status = "okay";
  153. };
  154. &pcie0 {
  155. mt76@0,0 {
  156. reg = <0x0000 0 0 0 0>;
  157. mediatek,mtd-eeprom = <&radio 0x8000>;
  158. ieee80211-freq-limit = <5000000 6000000>;
  159. mtd-mac-address = <&rom 0xf100>;
  160. mtd-mac-address-increment = <(-1)>;
  161. };
  162. };