0025-NET-MIPS-lantiq-adds-xrx200-legacy.patch 159 KB

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  1. From fb0c9601f4414c39ff68e26b88681bef0bb04954 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <[email protected]>
  3. Date: Mon, 22 Oct 2012 12:22:23 +0200
  4. Subject: NET: MIPS: lantiq: adds xrx200 ethernet and switch driver
  5. ---
  6. drivers/net/ethernet/Kconfig | 8 +-
  7. drivers/net/ethernet/Makefile | 1 +
  8. drivers/net/ethernet/lantiq_pce.h | 163 +++
  9. drivers/net/ethernet/lantiq_xrx200_legacy.c | 1798 +++++++++++++++++++++++++++++++
  10. drivers/net/ethernet/lantiq_xrx200_legacy.h | 1328 +++++++++++++++++++++++
  11. 5 files changed, 3297 insertions(+), 1 deletion(-)
  12. create mode 100644 drivers/net/ethernet/lantiq_pce.h
  13. create mode 100644 drivers/net/ethernet/lantiq_xrx200_legacy.c
  14. create mode 100644 drivers/net/ethernet/lantiq_xrx200_legacy.h
  15. --- a/drivers/net/ethernet/Kconfig
  16. +++ b/drivers/net/ethernet/Kconfig
  17. @@ -107,7 +107,13 @@ config LANTIQ_ETOP
  18. tristate "Lantiq SoC ETOP driver"
  19. depends on SOC_TYPE_XWAY
  20. help
  21. - Support for the MII0 inside the Lantiq SoC
  22. + Support for the MII0 inside the Lantiq ADSL SoC
  23. +
  24. +config LANTIQ_XRX200_LEGACY
  25. + tristate "Lantiq SoC XRX200 driver"
  26. + depends on SOC_TYPE_XWAY
  27. + help
  28. + Support for the MII0 inside the Lantiq VDSL SoC
  29. config LANTIQ_XRX200
  30. tristate "Lantiq / Intel xRX200 PMAC network driver"
  31. --- a/drivers/net/ethernet/Makefile
  32. +++ b/drivers/net/ethernet/Makefile
  33. @@ -50,6 +50,7 @@ obj-$(CONFIG_JME) += jme.o
  34. obj-$(CONFIG_KORINA) += korina.o
  35. obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
  36. obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o
  37. +obj-$(CONFIG_LANTIQ_XRX200_LEGACY) += lantiq_xrx200_legacy.o
  38. obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/
  39. obj-$(CONFIG_NET_VENDOR_MEDIATEK) += mediatek/
  40. obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
  41. --- /dev/null
  42. +++ b/drivers/net/ethernet/lantiq_pce.h
  43. @@ -0,0 +1,163 @@
  44. +/*
  45. + * This program is free software; you can redistribute it and/or modify it
  46. + * under the terms of the GNU General Public License version 2 as published
  47. + * by the Free Software Foundation.
  48. + *
  49. + * This program is distributed in the hope that it will be useful,
  50. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  51. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  52. + * GNU General Public License for more details.
  53. + *
  54. + * You should have received a copy of the GNU General Public License
  55. + * along with this program; if not, write to the Free Software
  56. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  57. + *
  58. + * Copyright (C) 2010 Lantiq Deutschland GmbH
  59. + * Copyright (C) 2012 John Crispin <[email protected]>
  60. + *
  61. + * PCE microcode extracted from UGW5.2 switch api
  62. + */
  63. +
  64. +/* Switch API Micro Code V0.3 */
  65. +enum {
  66. + OUT_MAC0 = 0,
  67. + OUT_MAC1,
  68. + OUT_MAC2,
  69. + OUT_MAC3,
  70. + OUT_MAC4,
  71. + OUT_MAC5,
  72. + OUT_ETHTYP,
  73. + OUT_VTAG0,
  74. + OUT_VTAG1,
  75. + OUT_ITAG0,
  76. + OUT_ITAG1, /*10 */
  77. + OUT_ITAG2,
  78. + OUT_ITAG3,
  79. + OUT_IP0,
  80. + OUT_IP1,
  81. + OUT_IP2,
  82. + OUT_IP3,
  83. + OUT_SIP0,
  84. + OUT_SIP1,
  85. + OUT_SIP2,
  86. + OUT_SIP3, /*20*/
  87. + OUT_SIP4,
  88. + OUT_SIP5,
  89. + OUT_SIP6,
  90. + OUT_SIP7,
  91. + OUT_DIP0,
  92. + OUT_DIP1,
  93. + OUT_DIP2,
  94. + OUT_DIP3,
  95. + OUT_DIP4,
  96. + OUT_DIP5, /*30*/
  97. + OUT_DIP6,
  98. + OUT_DIP7,
  99. + OUT_SESID,
  100. + OUT_PROT,
  101. + OUT_APP0,
  102. + OUT_APP1,
  103. + OUT_IGMP0,
  104. + OUT_IGMP1,
  105. + OUT_IPOFF, /*39*/
  106. + OUT_NONE = 63
  107. +};
  108. +
  109. +/* parser's microcode length type */
  110. +#define INSTR 0
  111. +#define IPV6 1
  112. +#define LENACCU 2
  113. +
  114. +/* parser's microcode flag type */
  115. +enum {
  116. + FLAG_ITAG = 0,
  117. + FLAG_VLAN,
  118. + FLAG_SNAP,
  119. + FLAG_PPPOE,
  120. + FLAG_IPV6,
  121. + FLAG_IPV6FL,
  122. + FLAG_IPV4,
  123. + FLAG_IGMP,
  124. + FLAG_TU,
  125. + FLAG_HOP,
  126. + FLAG_NN1, /*10 */
  127. + FLAG_NN2,
  128. + FLAG_END,
  129. + FLAG_NO, /*13*/
  130. +};
  131. +
  132. +/* Micro code version V2_11 (extension for parsing IPv6 in PPPoE) */
  133. +#define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \
  134. + { {val, msk, (ns<<10 | out<<4 | len>>1), (len&1)<<15 | type<<13 | flags<<9 | ipv4_len<<8 }}
  135. +struct pce_microcode {
  136. + unsigned short val[4];
  137. +/* unsigned short val_2;
  138. + unsigned short val_1;
  139. + unsigned short val_0;*/
  140. +} pce_microcode[] = {
  141. + /* value mask ns fields L type flags ipv4_len */
  142. + MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0),
  143. + MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
  144. + MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
  145. + MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
  146. + MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
  147. + MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
  148. + MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
  149. + MC_ENTRY(0x8863, 0xFFFF, 16, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
  150. + MC_ENTRY(0x0000, 0xF800, 10, OUT_NONE, 0, INSTR, FLAG_NO, 0),
  151. + MC_ENTRY(0x0000, 0x0000, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
  152. + MC_ENTRY(0x0600, 0x0600, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
  153. + MC_ENTRY(0x0000, 0x0000, 12, OUT_NONE, 1, INSTR, FLAG_NO, 0),
  154. + MC_ENTRY(0xAAAA, 0xFFFF, 14, OUT_NONE, 1, INSTR, FLAG_NO, 0),
  155. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
  156. + MC_ENTRY(0x0300, 0xFF00, 39, OUT_NONE, 0, INSTR, FLAG_SNAP, 0),
  157. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
  158. + MC_ENTRY(0x0000, 0x0000, 39, OUT_DIP7, 3, INSTR, FLAG_NO, 0),
  159. + MC_ENTRY(0x0000, 0x0000, 18, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0),
  160. + MC_ENTRY(0x0021, 0xFFFF, 21, OUT_NONE, 1, INSTR, FLAG_NO, 0),
  161. + MC_ENTRY(0x0057, 0xFFFF, 22, OUT_NONE, 1, INSTR, FLAG_NO, 0),
  162. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
  163. + MC_ENTRY(0x4000, 0xF000, 24, OUT_IP0, 4, INSTR, FLAG_IPV4, 1),
  164. + MC_ENTRY(0x6000, 0xF000, 27, OUT_IP0, 3, INSTR, FLAG_IPV6, 0),
  165. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
  166. + MC_ENTRY(0x0000, 0x0000, 25, OUT_IP3, 2, INSTR, FLAG_NO, 0),
  167. + MC_ENTRY(0x0000, 0x0000, 26, OUT_SIP0, 4, INSTR, FLAG_NO, 0),
  168. + MC_ENTRY(0x0000, 0x0000, 38, OUT_NONE, 0, LENACCU, FLAG_NO, 0),
  169. + MC_ENTRY(0x1100, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
  170. + MC_ENTRY(0x0600, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
  171. + MC_ENTRY(0x0000, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_HOP, 0),
  172. + MC_ENTRY(0x2B00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN1, 0),
  173. + MC_ENTRY(0x3C00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN2, 0),
  174. + MC_ENTRY(0x0000, 0x0000, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
  175. + MC_ENTRY(0x0000, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_HOP, 0),
  176. + MC_ENTRY(0x2B00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN1, 0),
  177. + MC_ENTRY(0x3C00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN2, 0),
  178. + MC_ENTRY(0x0000, 0x0000, 38, OUT_PROT, 1, IPV6, FLAG_NO, 0),
  179. + MC_ENTRY(0x0000, 0x0000, 38, OUT_SIP0, 16, INSTR, FLAG_NO, 0),
  180. + MC_ENTRY(0x0000, 0x0000, 39, OUT_APP0, 4, INSTR, FLAG_IGMP, 0),
  181. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  182. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  183. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  184. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  185. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  186. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  187. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  188. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  189. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  190. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  191. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  192. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  193. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  194. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  195. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  196. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  197. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  198. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  199. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  200. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  201. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  202. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  203. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  204. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  205. + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
  206. +};
  207. --- /dev/null
  208. +++ b/drivers/net/ethernet/lantiq_xrx200_legacy.c
  209. @@ -0,0 +1,1930 @@
  210. +/*
  211. + * This program is free software; you can redistribute it and/or modify it
  212. + * under the terms of the GNU General Public License version 2 as published
  213. + * by the Free Software Foundation.
  214. + *
  215. + * This program is distributed in the hope that it will be useful,
  216. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  217. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  218. + * GNU General Public License for more details.
  219. + *
  220. + * You should have received a copy of the GNU General Public License
  221. + * along with this program; if not, write to the Free Software
  222. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  223. + *
  224. + * Copyright (C) 2010 Lantiq Deutschland
  225. + * Copyright (C) 2012 John Crispin <[email protected]>
  226. + */
  227. +
  228. +#include <linux/switch.h>
  229. +#include <linux/etherdevice.h>
  230. +#include <linux/module.h>
  231. +#include <linux/platform_device.h>
  232. +#include <linux/interrupt.h>
  233. +#include <linux/clk.h>
  234. +#include <linux/if_vlan.h>
  235. +#include <asm/delay.h>
  236. +
  237. +#include <linux/of_net.h>
  238. +#include <linux/of_mdio.h>
  239. +#include <linux/of_gpio.h>
  240. +#include <linux/of_platform.h>
  241. +
  242. +#include <xway_dma.h>
  243. +#include <lantiq_soc.h>
  244. +
  245. +#include "lantiq_pce.h"
  246. +#include "lantiq_xrx200_legacy.h"
  247. +
  248. +#define SW_POLLING
  249. +#define SW_ROUTING
  250. +
  251. +#ifdef SW_ROUTING
  252. +#define XRX200_MAX_DEV 2
  253. +#else
  254. +#define XRX200_MAX_DEV 1
  255. +#endif
  256. +
  257. +#define XRX200_MAX_VLAN 64
  258. +#define XRX200_PCE_ACTVLAN_IDX 0x01
  259. +#define XRX200_PCE_VLANMAP_IDX 0x02
  260. +
  261. +#define XRX200_MAX_PORT 7
  262. +#define XRX200_MAX_DMA 8
  263. +
  264. +#define XRX200_HEADROOM 4
  265. +
  266. +#define XRX200_TX_TIMEOUT (10 * HZ)
  267. +
  268. +/* port type */
  269. +#define XRX200_PORT_TYPE_PHY 1
  270. +#define XRX200_PORT_TYPE_MAC 2
  271. +
  272. +/* DMA */
  273. +#define XRX200_DMA_DATA_LEN 0x600
  274. +#define XRX200_DMA_IRQ INT_NUM_IM2_IRL0
  275. +#define XRX200_DMA_RX 0
  276. +#define XRX200_DMA_TX 1
  277. +#define XRX200_DMA_TX_2 3
  278. +#define XRX200_DMA_IS_TX(x) (x%2)
  279. +#define XRX200_DMA_IS_RX(x) (!XRX200_DMA_IS_TX(x))
  280. +
  281. +/* fetch / store dma */
  282. +#define FDMA_PCTRL0 0x2A00
  283. +#define FDMA_PCTRLx(x) (FDMA_PCTRL0 + (x * 0x18))
  284. +#define SDMA_PCTRL0 0x2F00
  285. +#define SDMA_PCTRLx(x) (SDMA_PCTRL0 + (x * 0x18))
  286. +
  287. +/* buffer management */
  288. +#define BM_PCFG0 0x200
  289. +#define BM_PCFGx(x) (BM_PCFG0 + (x * 8))
  290. +
  291. +/* MDIO */
  292. +#define MDIO_GLOB 0x0000
  293. +#define MDIO_CTRL 0x0020
  294. +#define MDIO_READ 0x0024
  295. +#define MDIO_WRITE 0x0028
  296. +#define MDIO_PHY0 0x0054
  297. +#define MDIO_PHY(x) (0x0054 - (x * sizeof(unsigned)))
  298. +#define MDIO_CLK_CFG0 0x002C
  299. +#define MDIO_CLK_CFG1 0x0030
  300. +
  301. +#define MDIO_GLOB_ENABLE 0x8000
  302. +#define MDIO_BUSY BIT(12)
  303. +#define MDIO_RD BIT(11)
  304. +#define MDIO_WR BIT(10)
  305. +#define MDIO_MASK 0x1f
  306. +#define MDIO_ADDRSHIFT 5
  307. +#define MDIO1_25MHZ 9
  308. +
  309. +#define MDIO_PHY_LINK_DOWN 0x4000
  310. +#define MDIO_PHY_LINK_UP 0x2000
  311. +
  312. +#define MDIO_PHY_SPEED_M10 0x0000
  313. +#define MDIO_PHY_SPEED_M100 0x0800
  314. +#define MDIO_PHY_SPEED_G1 0x1000
  315. +
  316. +#define MDIO_PHY_FDUP_EN 0x0200
  317. +#define MDIO_PHY_FDUP_DIS 0x0600
  318. +
  319. +#define MDIO_PHY_LINK_MASK 0x6000
  320. +#define MDIO_PHY_SPEED_MASK 0x1800
  321. +#define MDIO_PHY_FDUP_MASK 0x0600
  322. +#define MDIO_PHY_ADDR_MASK 0x001f
  323. +#define MDIO_UPDATE_MASK MDIO_PHY_ADDR_MASK | MDIO_PHY_LINK_MASK | \
  324. + MDIO_PHY_SPEED_MASK | MDIO_PHY_FDUP_MASK
  325. +
  326. +/* MII */
  327. +#define MII_CFG(p) (p * 8)
  328. +
  329. +#define MII_CFG_EN BIT(14)
  330. +
  331. +#define MII_CFG_MODE_MIIP 0x0
  332. +#define MII_CFG_MODE_MIIM 0x1
  333. +#define MII_CFG_MODE_RMIIP 0x2
  334. +#define MII_CFG_MODE_RMIIM 0x3
  335. +#define MII_CFG_MODE_RGMII 0x4
  336. +#define MII_CFG_MODE_MASK 0xf
  337. +
  338. +#define MII_CFG_RATE_M2P5 0x00
  339. +#define MII_CFG_RATE_M25 0x10
  340. +#define MII_CFG_RATE_M125 0x20
  341. +#define MII_CFG_RATE_M50 0x30
  342. +#define MII_CFG_RATE_AUTO 0x40
  343. +#define MII_CFG_RATE_MASK 0x70
  344. +
  345. +/* cpu port mac */
  346. +#define PMAC_HD_CTL 0x0000
  347. +#define PMAC_RX_IPG 0x0024
  348. +#define PMAC_EWAN 0x002c
  349. +
  350. +#define PMAC_IPG_MASK 0xf
  351. +#define PMAC_HD_CTL_AS 0x0008
  352. +#define PMAC_HD_CTL_AC 0x0004
  353. +#define PMAC_HD_CTL_RC 0x0010
  354. +#define PMAC_HD_CTL_RXSH 0x0040
  355. +#define PMAC_HD_CTL_AST 0x0080
  356. +#define PMAC_HD_CTL_RST 0x0100
  357. +
  358. +/* PCE */
  359. +#define PCE_TBL_KEY(x) (0x1100 + ((7 - x) * 4))
  360. +#define PCE_TBL_MASK 0x1120
  361. +#define PCE_TBL_VAL(x) (0x1124 + ((4 - x) * 4))
  362. +#define PCE_TBL_ADDR 0x1138
  363. +#define PCE_TBL_CTRL 0x113c
  364. +#define PCE_PMAP1 0x114c
  365. +#define PCE_PMAP2 0x1150
  366. +#define PCE_PMAP3 0x1154
  367. +#define PCE_GCTRL_REG(x) (0x1158 + (x * 4))
  368. +#define PCE_PCTRL_REG(p, x) (0x1200 + (((p * 0xa) + x) * 4))
  369. +
  370. +#define PCE_TBL_BUSY BIT(15)
  371. +#define PCE_TBL_CFG_ADDR_MASK 0x1f
  372. +#define PCE_TBL_CFG_ADWR 0x20
  373. +#define PCE_TBL_CFG_ADWR_MASK 0x60
  374. +#define PCE_INGRESS BIT(11)
  375. +
  376. +/* MAC */
  377. +#define MAC_FLEN_REG (0x2314)
  378. +#define MAC_CTRL_REG(p, x) (0x240c + (((p * 0xc) + x) * 4))
  379. +
  380. +/* buffer management */
  381. +#define BM_PCFG(p) (0x200 + (p * 8))
  382. +
  383. +/* special tag in TX path header */
  384. +#define SPID_SHIFT 24
  385. +#define DPID_SHIFT 16
  386. +#define DPID_ENABLE 1
  387. +#define SPID_CPU_PORT 2
  388. +#define PORT_MAP_SEL BIT(15)
  389. +#define PORT_MAP_EN BIT(14)
  390. +#define PORT_MAP_SHIFT 1
  391. +#define PORT_MAP_MASK 0x3f
  392. +
  393. +#define SPPID_MASK 0x7
  394. +#define SPPID_SHIFT 4
  395. +
  396. +/* MII regs not yet in linux */
  397. +#define MDIO_DEVAD_NONE (-1)
  398. +#define ADVERTIZE_MPD (1 << 10)
  399. +
  400. +struct xrx200_port {
  401. + u8 num;
  402. + u8 phy_addr;
  403. + u16 flags;
  404. + phy_interface_t phy_if;
  405. +
  406. + int link;
  407. + int gpio;
  408. + enum of_gpio_flags gpio_flags;
  409. +
  410. + struct phy_device *phydev;
  411. + struct device_node *phy_node;
  412. +};
  413. +
  414. +struct xrx200_chan {
  415. + int idx;
  416. + int refcount;
  417. + int tx_free;
  418. +
  419. + struct net_device dummy_dev;
  420. + struct net_device *devs[XRX200_MAX_DEV];
  421. +
  422. + struct tasklet_struct tasklet;
  423. + struct napi_struct napi;
  424. + struct ltq_dma_channel dma;
  425. + struct sk_buff *skb[LTQ_DESC_NUM];
  426. +
  427. + spinlock_t lock;
  428. +};
  429. +
  430. +struct xrx200_hw {
  431. + struct clk *clk;
  432. + struct mii_bus *mii_bus;
  433. + u8 phy_addr[XRX200_MAX_PORT];
  434. +
  435. + struct xrx200_chan chan[XRX200_MAX_DMA];
  436. + u16 vlan_vid[XRX200_MAX_VLAN];
  437. + u16 vlan_port_map[XRX200_MAX_VLAN];
  438. +
  439. + struct net_device *devs[XRX200_MAX_DEV];
  440. + int num_devs;
  441. +
  442. + int port_map[XRX200_MAX_PORT];
  443. + unsigned short wan_map;
  444. +
  445. + struct switch_dev swdev;
  446. +};
  447. +
  448. +struct xrx200_priv {
  449. + struct net_device_stats stats;
  450. + int id;
  451. +
  452. + struct xrx200_port port[XRX200_MAX_PORT];
  453. + int num_port;
  454. + bool wan;
  455. + bool sw;
  456. + unsigned short port_map;
  457. + unsigned char mac[6];
  458. +
  459. + struct xrx200_hw *hw;
  460. +};
  461. +
  462. +static __iomem void *xrx200_switch_membase;
  463. +static __iomem void *xrx200_mii_membase;
  464. +static __iomem void *xrx200_mdio_membase;
  465. +static __iomem void *xrx200_pmac_membase;
  466. +
  467. +#define ltq_switch_r32(x) ltq_r32(xrx200_switch_membase + (x))
  468. +#define ltq_switch_w32(x, y) ltq_w32(x, xrx200_switch_membase + (y))
  469. +#define ltq_switch_w32_mask(x, y, z) \
  470. + ltq_w32_mask(x, y, xrx200_switch_membase + (z))
  471. +
  472. +#define ltq_mdio_r32(x) ltq_r32(xrx200_mdio_membase + (x))
  473. +#define ltq_mdio_w32(x, y) ltq_w32(x, xrx200_mdio_membase + (y))
  474. +#define ltq_mdio_w32_mask(x, y, z) \
  475. + ltq_w32_mask(x, y, xrx200_mdio_membase + (z))
  476. +
  477. +#define ltq_mii_r32(x) ltq_r32(xrx200_mii_membase + (x))
  478. +#define ltq_mii_w32(x, y) ltq_w32(x, xrx200_mii_membase + (y))
  479. +#define ltq_mii_w32_mask(x, y, z) \
  480. + ltq_w32_mask(x, y, xrx200_mii_membase + (z))
  481. +
  482. +#define ltq_pmac_r32(x) ltq_r32(xrx200_pmac_membase + (x))
  483. +#define ltq_pmac_w32(x, y) ltq_w32(x, xrx200_pmac_membase + (y))
  484. +#define ltq_pmac_w32_mask(x, y, z) \
  485. + ltq_w32_mask(x, y, xrx200_pmac_membase + (z))
  486. +
  487. +#define XRX200_GLOBAL_REGATTR(reg) \
  488. + .id = reg, \
  489. + .type = SWITCH_TYPE_INT, \
  490. + .set = xrx200_set_global_attr, \
  491. + .get = xrx200_get_global_attr
  492. +
  493. +#define XRX200_PORT_REGATTR(reg) \
  494. + .id = reg, \
  495. + .type = SWITCH_TYPE_INT, \
  496. + .set = xrx200_set_port_attr, \
  497. + .get = xrx200_get_port_attr
  498. +
  499. +static int xrx200sw_read_x(int reg, int x)
  500. +{
  501. + int value, mask, addr;
  502. +
  503. + addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x);
  504. + value = ltq_switch_r32(addr);
  505. + mask = (1 << xrx200sw_reg[reg].size) - 1;
  506. + value = (value >> xrx200sw_reg[reg].shift);
  507. +
  508. + return (value & mask);
  509. +}
  510. +
  511. +static int xrx200sw_read(int reg)
  512. +{
  513. + return xrx200sw_read_x(reg, 0);
  514. +}
  515. +
  516. +static void xrx200sw_write_x(int value, int reg, int x)
  517. +{
  518. + int mask, addr;
  519. +
  520. + addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x);
  521. + mask = (1 << xrx200sw_reg[reg].size) - 1;
  522. + mask = (mask << xrx200sw_reg[reg].shift);
  523. + value = (value << xrx200sw_reg[reg].shift) & mask;
  524. +
  525. + ltq_switch_w32_mask(mask, value, addr);
  526. +}
  527. +
  528. +static void xrx200sw_write(int value, int reg)
  529. +{
  530. + xrx200sw_write_x(value, reg, 0);
  531. +}
  532. +
  533. +struct xrx200_pce_table_entry {
  534. + int index; // PCE_TBL_ADDR.ADDR = pData->table_index
  535. + int table; // PCE_TBL_CTRL.ADDR = pData->table
  536. + unsigned short key[8];
  537. + unsigned short val[5];
  538. + unsigned short mask;
  539. + unsigned short type;
  540. + unsigned short valid;
  541. + unsigned short gmap;
  542. +};
  543. +
  544. +static int xrx200_pce_table_entry_read(struct xrx200_pce_table_entry *tbl)
  545. +{
  546. + // wait until hardware is ready
  547. + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {};
  548. +
  549. + // prepare the table access:
  550. + // PCE_TBL_ADDR.ADDR = pData->table_index
  551. + xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR);
  552. + // PCE_TBL_CTRL.ADDR = pData->table
  553. + xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR);
  554. +
  555. + //(address-based read)
  556. + xrx200sw_write(0, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD
  557. +
  558. + xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access
  559. +
  560. + // wait until hardware is ready
  561. + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {};
  562. +
  563. + // read the keys
  564. + tbl->key[7] = xrx200sw_read(XRX200_PCE_TBL_KEY_7);
  565. + tbl->key[6] = xrx200sw_read(XRX200_PCE_TBL_KEY_6);
  566. + tbl->key[5] = xrx200sw_read(XRX200_PCE_TBL_KEY_5);
  567. + tbl->key[4] = xrx200sw_read(XRX200_PCE_TBL_KEY_4);
  568. + tbl->key[3] = xrx200sw_read(XRX200_PCE_TBL_KEY_3);
  569. + tbl->key[2] = xrx200sw_read(XRX200_PCE_TBL_KEY_2);
  570. + tbl->key[1] = xrx200sw_read(XRX200_PCE_TBL_KEY_1);
  571. + tbl->key[0] = xrx200sw_read(XRX200_PCE_TBL_KEY_0);
  572. +
  573. + // read the values
  574. + tbl->val[4] = xrx200sw_read(XRX200_PCE_TBL_VAL_4);
  575. + tbl->val[3] = xrx200sw_read(XRX200_PCE_TBL_VAL_3);
  576. + tbl->val[2] = xrx200sw_read(XRX200_PCE_TBL_VAL_2);
  577. + tbl->val[1] = xrx200sw_read(XRX200_PCE_TBL_VAL_1);
  578. + tbl->val[0] = xrx200sw_read(XRX200_PCE_TBL_VAL_0);
  579. +
  580. + // read the mask
  581. + tbl->mask = xrx200sw_read(XRX200_PCE_TBL_MASK_0);
  582. + // read the type
  583. + tbl->type = xrx200sw_read(XRX200_PCE_TBL_CTRL_TYPE);
  584. + // read the valid flag
  585. + tbl->valid = xrx200sw_read(XRX200_PCE_TBL_CTRL_VLD);
  586. + // read the group map
  587. + tbl->gmap = xrx200sw_read(XRX200_PCE_TBL_CTRL_GMAP);
  588. +
  589. + return 0;
  590. +}
  591. +
  592. +static int xrx200_pce_table_entry_write(struct xrx200_pce_table_entry *tbl)
  593. +{
  594. + // wait until hardware is ready
  595. + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {};
  596. +
  597. + // prepare the table access:
  598. + // PCE_TBL_ADDR.ADDR = pData->table_index
  599. + xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR);
  600. + // PCE_TBL_CTRL.ADDR = pData->table
  601. + xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR);
  602. +
  603. + //(address-based write)
  604. + xrx200sw_write(1, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD
  605. +
  606. + // read the keys
  607. + xrx200sw_write(tbl->key[7], XRX200_PCE_TBL_KEY_7);
  608. + xrx200sw_write(tbl->key[6], XRX200_PCE_TBL_KEY_6);
  609. + xrx200sw_write(tbl->key[5], XRX200_PCE_TBL_KEY_5);
  610. + xrx200sw_write(tbl->key[4], XRX200_PCE_TBL_KEY_4);
  611. + xrx200sw_write(tbl->key[3], XRX200_PCE_TBL_KEY_3);
  612. + xrx200sw_write(tbl->key[2], XRX200_PCE_TBL_KEY_2);
  613. + xrx200sw_write(tbl->key[1], XRX200_PCE_TBL_KEY_1);
  614. + xrx200sw_write(tbl->key[0], XRX200_PCE_TBL_KEY_0);
  615. +
  616. + // read the values
  617. + xrx200sw_write(tbl->val[4], XRX200_PCE_TBL_VAL_4);
  618. + xrx200sw_write(tbl->val[3], XRX200_PCE_TBL_VAL_3);
  619. + xrx200sw_write(tbl->val[2], XRX200_PCE_TBL_VAL_2);
  620. + xrx200sw_write(tbl->val[1], XRX200_PCE_TBL_VAL_1);
  621. + xrx200sw_write(tbl->val[0], XRX200_PCE_TBL_VAL_0);
  622. +
  623. + // read the mask
  624. + xrx200sw_write(tbl->mask, XRX200_PCE_TBL_MASK_0);
  625. + // read the type
  626. + xrx200sw_write(tbl->type, XRX200_PCE_TBL_CTRL_TYPE);
  627. + // read the valid flag
  628. + xrx200sw_write(tbl->valid, XRX200_PCE_TBL_CTRL_VLD);
  629. + // read the group map
  630. + xrx200sw_write(tbl->gmap, XRX200_PCE_TBL_CTRL_GMAP);
  631. +
  632. + xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access
  633. +
  634. + // wait until hardware is ready
  635. + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {};
  636. +
  637. + return 0;
  638. +}
  639. +
  640. +static void xrx200sw_fixup_pvids(void)
  641. +{
  642. + int index, p, portmap, untagged;
  643. + struct xrx200_pce_table_entry tem;
  644. + struct xrx200_pce_table_entry tev;
  645. +
  646. + portmap = 0;
  647. + for (p = 0; p < XRX200_MAX_PORT; p++)
  648. + portmap |= BIT(p);
  649. +
  650. + tem.table = XRX200_PCE_VLANMAP_IDX;
  651. + tev.table = XRX200_PCE_ACTVLAN_IDX;
  652. +
  653. + for (index = XRX200_MAX_VLAN; index-- > 0;)
  654. + {
  655. + tev.index = index;
  656. + xrx200_pce_table_entry_read(&tev);
  657. +
  658. + if (tev.valid == 0)
  659. + continue;
  660. +
  661. + tem.index = index;
  662. + xrx200_pce_table_entry_read(&tem);
  663. +
  664. + if (tem.val[0] == 0)
  665. + continue;
  666. +
  667. + untagged = portmap & (tem.val[1] ^ tem.val[2]);
  668. +
  669. + for (p = 0; p < XRX200_MAX_PORT; p++)
  670. + if (untagged & BIT(p))
  671. + {
  672. + portmap &= ~BIT(p);
  673. + xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p);
  674. + }
  675. +
  676. + for (p = 0; p < XRX200_MAX_PORT; p++)
  677. + if (portmap & BIT(p))
  678. + xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p);
  679. + }
  680. +}
  681. +
  682. +// swconfig interface
  683. +static void xrx200_hw_init(struct xrx200_hw *hw);
  684. +
  685. +// global
  686. +static int xrx200sw_reset_switch(struct switch_dev *dev)
  687. +{
  688. + struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev);
  689. +
  690. + xrx200_hw_init(hw);
  691. +
  692. + return 0;
  693. +}
  694. +
  695. +static int xrx200_set_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
  696. +{
  697. + int p;
  698. +
  699. + if ((attr->max > 0) && (val->value.i > attr->max))
  700. + return -EINVAL;
  701. +
  702. + for (p = 0; p < XRX200_MAX_PORT; p++) {
  703. + xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VEMR, p);
  704. + xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VIMR, p);
  705. + }
  706. +
  707. + xrx200sw_write(val->value.i, XRX200_PCE_GCTRL_0_VLAN);
  708. + return 0;
  709. +}
  710. +
  711. +static int xrx200_get_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
  712. +{
  713. + val->value.i = xrx200sw_read(attr->id);
  714. + return 0;
  715. +}
  716. +
  717. +static int xrx200_set_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
  718. +{
  719. + if ((attr->max > 0) && (val->value.i > attr->max))
  720. + return -EINVAL;
  721. +
  722. + xrx200sw_write(val->value.i, attr->id);
  723. + return 0;
  724. +}
  725. +
  726. +static int xrx200_get_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
  727. +{
  728. + val->value.i = xrx200sw_read(attr->id);
  729. + return 0;
  730. +}
  731. +
  732. +// vlan
  733. +static int xrx200sw_set_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr,
  734. + struct switch_val *val)
  735. +{
  736. + struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev);
  737. + int i;
  738. + struct xrx200_pce_table_entry tev;
  739. + struct xrx200_pce_table_entry tem;
  740. +
  741. + tev.table = XRX200_PCE_ACTVLAN_IDX;
  742. +
  743. + for (i = 0; i < XRX200_MAX_VLAN; i++)
  744. + {
  745. + tev.index = i;
  746. + xrx200_pce_table_entry_read(&tev);
  747. + if (tev.key[0] == val->value.i && i != val->port_vlan)
  748. + return -EINVAL;
  749. + }
  750. +
  751. + hw->vlan_vid[val->port_vlan] = val->value.i;
  752. +
  753. + tev.index = val->port_vlan;
  754. + xrx200_pce_table_entry_read(&tev);
  755. + tev.key[0] = val->value.i;
  756. + tev.valid = val->value.i > 0;
  757. + xrx200_pce_table_entry_write(&tev);
  758. +
  759. + tem.table = XRX200_PCE_VLANMAP_IDX;
  760. + tem.index = val->port_vlan;
  761. + xrx200_pce_table_entry_read(&tem);
  762. + tem.val[0] = val->value.i;
  763. + xrx200_pce_table_entry_write(&tem);
  764. +
  765. + xrx200sw_fixup_pvids();
  766. + return 0;
  767. +}
  768. +
  769. +static int xrx200sw_get_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr,
  770. + struct switch_val *val)
  771. +{
  772. + struct xrx200_pce_table_entry te;
  773. +
  774. + te.table = XRX200_PCE_ACTVLAN_IDX;
  775. + te.index = val->port_vlan;
  776. + xrx200_pce_table_entry_read(&te);
  777. + val->value.i = te.key[0];
  778. +
  779. + return 0;
  780. +}
  781. +
  782. +static int xrx200sw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
  783. +{
  784. + struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev);
  785. + int i, portmap, tagmap, untagged;
  786. + struct xrx200_pce_table_entry tem;
  787. +
  788. + portmap = 0;
  789. + tagmap = 0;
  790. + for (i = 0; i < val->len; i++)
  791. + {
  792. + struct switch_port *p = &val->value.ports[i];
  793. +
  794. + portmap |= (1 << p->id);
  795. + if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
  796. + tagmap |= (1 << p->id);
  797. + }
  798. +
  799. + tem.table = XRX200_PCE_VLANMAP_IDX;
  800. +
  801. + untagged = portmap ^ tagmap;
  802. + for (i = 0; i < XRX200_MAX_VLAN; i++)
  803. + {
  804. + tem.index = i;
  805. + xrx200_pce_table_entry_read(&tem);
  806. +
  807. + if (tem.val[0] == 0)
  808. + continue;
  809. +
  810. + if ((untagged & (tem.val[1] ^ tem.val[2])) && (val->port_vlan != i))
  811. + return -EINVAL;
  812. + }
  813. +
  814. + tem.index = val->port_vlan;
  815. + xrx200_pce_table_entry_read(&tem);
  816. +
  817. + // auto-enable this vlan if not enabled already
  818. + if (tem.val[0] == 0)
  819. + {
  820. + struct switch_val v;
  821. + v.port_vlan = val->port_vlan;
  822. + v.value.i = val->port_vlan;
  823. + if(xrx200sw_set_vlan_vid(dev, NULL, &v))
  824. + return -EINVAL;
  825. +
  826. + //read updated tem
  827. + tem.index = val->port_vlan;
  828. + xrx200_pce_table_entry_read(&tem);
  829. + }
  830. +
  831. + tem.val[1] = portmap;
  832. + tem.val[2] = tagmap;
  833. + xrx200_pce_table_entry_write(&tem);
  834. +
  835. + ltq_switch_w32_mask(0, portmap, PCE_PMAP2);
  836. + ltq_switch_w32_mask(0, portmap, PCE_PMAP3);
  837. + hw->vlan_port_map[val->port_vlan] = portmap;
  838. +
  839. + xrx200sw_fixup_pvids();
  840. +
  841. + return 0;
  842. +}
  843. +
  844. +static int xrx200sw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
  845. +{
  846. + int i;
  847. + unsigned short ports, tags;
  848. + struct xrx200_pce_table_entry tem;
  849. +
  850. + tem.table = XRX200_PCE_VLANMAP_IDX;
  851. + tem.index = val->port_vlan;
  852. + xrx200_pce_table_entry_read(&tem);
  853. +
  854. + ports = tem.val[1];
  855. + tags = tem.val[2];
  856. +
  857. + for (i = 0; i < XRX200_MAX_PORT; i++) {
  858. + struct switch_port *p;
  859. +
  860. + if (!(ports & (1 << i)))
  861. + continue;
  862. +
  863. + p = &val->value.ports[val->len++];
  864. + p->id = i;
  865. + if (tags & (1 << i))
  866. + p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
  867. + else
  868. + p->flags = 0;
  869. + }
  870. +
  871. + return 0;
  872. +}
  873. +
  874. +static int xrx200sw_set_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr,
  875. + struct switch_val *val)
  876. +{
  877. + struct xrx200_pce_table_entry tev;
  878. +
  879. + tev.table = XRX200_PCE_ACTVLAN_IDX;
  880. + tev.index = val->port_vlan;
  881. + xrx200_pce_table_entry_read(&tev);
  882. +
  883. + if (tev.key[0] == 0)
  884. + return -EINVAL;
  885. +
  886. + tev.valid = val->value.i;
  887. + xrx200_pce_table_entry_write(&tev);
  888. +
  889. + xrx200sw_fixup_pvids();
  890. + return 0;
  891. +}
  892. +
  893. +static int xrx200sw_get_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr,
  894. + struct switch_val *val)
  895. +{
  896. + struct xrx200_pce_table_entry tev;
  897. +
  898. + tev.table = XRX200_PCE_ACTVLAN_IDX;
  899. + tev.index = val->port_vlan;
  900. + xrx200_pce_table_entry_read(&tev);
  901. + val->value.i = tev.valid;
  902. +
  903. + return 0;
  904. +}
  905. +
  906. +// port
  907. +static int xrx200sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
  908. +{
  909. + struct xrx200_pce_table_entry tev;
  910. +
  911. + if (port >= XRX200_MAX_PORT)
  912. + return -EINVAL;
  913. +
  914. + tev.table = XRX200_PCE_ACTVLAN_IDX;
  915. + tev.index = xrx200sw_read_x(XRX200_PCE_DEFPVID_PVID, port);
  916. + xrx200_pce_table_entry_read(&tev);
  917. +
  918. + *val = tev.key[0];
  919. + return 0;
  920. +}
  921. +
  922. +static int xrx200sw_get_port_link(struct switch_dev *dev,
  923. + int port,
  924. + struct switch_port_link *link)
  925. +{
  926. + if (port >= XRX200_MAX_PORT)
  927. + return -EINVAL;
  928. +
  929. + link->link = xrx200sw_read_x(XRX200_MAC_PSTAT_LSTAT, port);
  930. + if (!link->link)
  931. + return 0;
  932. +
  933. + link->duplex = xrx200sw_read_x(XRX200_MAC_PSTAT_FDUP, port);
  934. +
  935. + link->rx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0010);
  936. + link->tx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0020);
  937. + link->aneg = !(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port));
  938. +
  939. + link->speed = SWITCH_PORT_SPEED_10;
  940. + if (xrx200sw_read_x(XRX200_MAC_PSTAT_MBIT, port))
  941. + link->speed = SWITCH_PORT_SPEED_100;
  942. + if (xrx200sw_read_x(XRX200_MAC_PSTAT_GBIT, port))
  943. + link->speed = SWITCH_PORT_SPEED_1000;
  944. +
  945. + return 0;
  946. +}
  947. +
  948. +static int xrx200sw_set_port_link(struct switch_dev *dev, int port,
  949. + struct switch_port_link *link)
  950. +{
  951. + if (port >= XRX200_MAX_PORT)
  952. + return -EINVAL;
  953. +
  954. + return switch_generic_set_link(dev, port, link);
  955. +}
  956. +
  957. +static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val);
  958. +static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg);
  959. +
  960. +static int xrx200sw_phy_read16(struct switch_dev *dev, int addr, u8 reg, u16 *value)
  961. +{
  962. + struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev);
  963. +
  964. + *value = xrx200_mdio_rd(hw->mii_bus, hw->phy_addr[addr], reg);
  965. +
  966. + return 0;
  967. +}
  968. +
  969. +static int xrx200sw_phy_write16(struct switch_dev *dev, int addr, u8 reg, u16 value)
  970. +{
  971. + struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev);
  972. +
  973. + return xrx200_mdio_wr(hw->mii_bus, hw->phy_addr[addr], reg, value);
  974. +}
  975. +
  976. +static int xrx200_set_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
  977. +{
  978. + if (val->port_vlan >= XRX200_MAX_PORT)
  979. + return -EINVAL;
  980. +
  981. + if ((attr->max > 0) && (val->value.i > attr->max))
  982. + return -EINVAL;
  983. +
  984. + xrx200sw_write_x(val->value.i, attr->id, val->port_vlan);
  985. + return 0;
  986. +}
  987. +
  988. +static int xrx200_get_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
  989. +{
  990. + if (val->port_vlan >= XRX200_MAX_PORT)
  991. + return -EINVAL;
  992. +
  993. + val->value.i = xrx200sw_read_x(attr->id, val->port_vlan);
  994. + return 0;
  995. +}
  996. +
  997. +// attributes
  998. +static struct switch_attr xrx200sw_globals[] = {
  999. + {
  1000. + .type = SWITCH_TYPE_INT,
  1001. + .set = xrx200_set_vlan_mode_enable,
  1002. + .get = xrx200_get_vlan_mode_enable,
  1003. + .name = "enable_vlan",
  1004. + .description = "Enable VLAN mode",
  1005. + .max = 1},
  1006. +};
  1007. +
  1008. +static struct switch_attr xrx200sw_port[] = {
  1009. + {
  1010. + XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_UVR),
  1011. + .name = "uvr",
  1012. + .description = "Unknown VLAN Rule",
  1013. + .max = 1,
  1014. + },
  1015. + {
  1016. + XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VSR),
  1017. + .name = "vsr",
  1018. + .description = "VLAN Security Rule",
  1019. + .max = 1,
  1020. + },
  1021. + {
  1022. + XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VINR),
  1023. + .name = "vinr",
  1024. + .description = "VLAN Ingress Tag Rule",
  1025. + .max = 2,
  1026. + },
  1027. + {
  1028. + XRX200_PORT_REGATTR(XRX200_PCE_PCTRL_0_TVM),
  1029. + .name = "tvm",
  1030. + .description = "Transparent VLAN Mode",
  1031. + .max = 1,
  1032. + },
  1033. +};
  1034. +
  1035. +static struct switch_attr xrx200sw_vlan[] = {
  1036. + {
  1037. + .type = SWITCH_TYPE_INT,
  1038. + .name = "vid",
  1039. + .description = "VLAN ID (0-4094)",
  1040. + .set = xrx200sw_set_vlan_vid,
  1041. + .get = xrx200sw_get_vlan_vid,
  1042. + .max = 4094,
  1043. + },
  1044. + {
  1045. + .type = SWITCH_TYPE_INT,
  1046. + .name = "enable",
  1047. + .description = "Enable VLAN",
  1048. + .set = xrx200sw_set_vlan_enable,
  1049. + .get = xrx200sw_get_vlan_enable,
  1050. + .max = 1,
  1051. + },
  1052. +};
  1053. +
  1054. +static const struct switch_dev_ops xrx200sw_ops = {
  1055. + .attr_global = {
  1056. + .attr = xrx200sw_globals,
  1057. + .n_attr = ARRAY_SIZE(xrx200sw_globals),
  1058. + },
  1059. + .attr_port = {
  1060. + .attr = xrx200sw_port,
  1061. + .n_attr = ARRAY_SIZE(xrx200sw_port),
  1062. + },
  1063. + .attr_vlan = {
  1064. + .attr = xrx200sw_vlan,
  1065. + .n_attr = ARRAY_SIZE(xrx200sw_vlan),
  1066. + },
  1067. + .get_vlan_ports = xrx200sw_get_vlan_ports,
  1068. + .set_vlan_ports = xrx200sw_set_vlan_ports,
  1069. + .get_port_pvid = xrx200sw_get_port_pvid,
  1070. + .reset_switch = xrx200sw_reset_switch,
  1071. + .get_port_link = xrx200sw_get_port_link,
  1072. + .set_port_link = xrx200sw_set_port_link,
  1073. +// .get_port_stats = xrx200sw_get_port_stats, //TODO
  1074. + .phy_read16 = xrx200sw_phy_read16,
  1075. + .phy_write16 = xrx200sw_phy_write16,
  1076. +};
  1077. +
  1078. +static int xrx200sw_init(struct xrx200_hw *hw)
  1079. +{
  1080. + int netdev_num;
  1081. +
  1082. + for (netdev_num = 0; netdev_num < hw->num_devs; netdev_num++)
  1083. + {
  1084. + struct switch_dev *swdev;
  1085. + struct net_device *dev = hw->devs[netdev_num];
  1086. + struct xrx200_priv *priv = netdev_priv(dev);
  1087. + if (!priv->sw)
  1088. + continue;
  1089. +
  1090. + swdev = &hw->swdev;
  1091. +
  1092. + swdev->name = "Lantiq XRX200 Switch";
  1093. + swdev->vlans = XRX200_MAX_VLAN;
  1094. + swdev->ports = XRX200_MAX_PORT;
  1095. + swdev->cpu_port = 6;
  1096. + swdev->ops = &xrx200sw_ops;
  1097. +
  1098. + register_switch(swdev, dev);
  1099. + return 0; // enough switches
  1100. + }
  1101. + return 0;
  1102. +}
  1103. +
  1104. +static int xrx200_open(struct net_device *dev)
  1105. +{
  1106. + struct xrx200_priv *priv = netdev_priv(dev);
  1107. + int i;
  1108. +
  1109. + for (i = 0; i < XRX200_MAX_DMA; i++) {
  1110. + if (!priv->hw->chan[i].dma.irq)
  1111. + continue;
  1112. + spin_lock_bh(&priv->hw->chan[i].lock);
  1113. + if (!priv->hw->chan[i].refcount) {
  1114. + if (XRX200_DMA_IS_RX(i))
  1115. + napi_enable(&priv->hw->chan[i].napi);
  1116. + ltq_dma_open(&priv->hw->chan[i].dma);
  1117. + ltq_dma_enable_irq(&priv->hw->chan[i].dma);
  1118. + }
  1119. + priv->hw->chan[i].refcount++;
  1120. + spin_unlock_bh(&priv->hw->chan[i].lock);
  1121. + }
  1122. + for (i = 0; i < priv->num_port; i++)
  1123. + if (priv->port[i].phydev)
  1124. + phy_start(priv->port[i].phydev);
  1125. + netif_wake_queue(dev);
  1126. +
  1127. + return 0;
  1128. +}
  1129. +
  1130. +static int xrx200_close(struct net_device *dev)
  1131. +{
  1132. + struct xrx200_priv *priv = netdev_priv(dev);
  1133. + int i;
  1134. +
  1135. + netif_stop_queue(dev);
  1136. +
  1137. + for (i = 0; i < priv->num_port; i++)
  1138. + if (priv->port[i].phydev)
  1139. + phy_stop(priv->port[i].phydev);
  1140. +
  1141. + for (i = 0; i < XRX200_MAX_DMA; i++) {
  1142. + if (!priv->hw->chan[i].dma.irq)
  1143. + continue;
  1144. +
  1145. + priv->hw->chan[i].refcount--;
  1146. + if (!priv->hw->chan[i].refcount) {
  1147. + if (XRX200_DMA_IS_RX(i))
  1148. + napi_disable(&priv->hw->chan[i].napi);
  1149. + spin_lock_bh(&priv->hw->chan[i].lock);
  1150. + ltq_dma_close(&priv->hw->chan[XRX200_DMA_RX].dma);
  1151. + spin_unlock_bh(&priv->hw->chan[i].lock);
  1152. + }
  1153. + }
  1154. +
  1155. + return 0;
  1156. +}
  1157. +
  1158. +static int xrx200_alloc_skb(struct xrx200_chan *ch)
  1159. +{
  1160. +#define DMA_PAD (NET_IP_ALIGN + NET_SKB_PAD)
  1161. + ch->skb[ch->dma.desc] = dev_alloc_skb(XRX200_DMA_DATA_LEN + DMA_PAD);
  1162. + if (!ch->skb[ch->dma.desc])
  1163. + goto skip;
  1164. +
  1165. + skb_reserve(ch->skb[ch->dma.desc], NET_SKB_PAD);
  1166. + ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(ch->dma.dev,
  1167. + ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN,
  1168. + DMA_FROM_DEVICE);
  1169. + ch->dma.desc_base[ch->dma.desc].addr =
  1170. + CPHYSADDR(ch->skb[ch->dma.desc]->data);
  1171. + skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
  1172. +
  1173. +skip:
  1174. + ch->dma.desc_base[ch->dma.desc].ctl =
  1175. + LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
  1176. + XRX200_DMA_DATA_LEN;
  1177. +
  1178. + return 0;
  1179. +}
  1180. +
  1181. +static void xrx200_hw_receive(struct xrx200_chan *ch, int id)
  1182. +{
  1183. + struct net_device *dev = ch->devs[id];
  1184. + struct xrx200_priv *priv = netdev_priv(dev);
  1185. + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
  1186. + struct sk_buff *skb = ch->skb[ch->dma.desc];
  1187. + int len = (desc->ctl & LTQ_DMA_SIZE_MASK);
  1188. + int ret;
  1189. +
  1190. + ret = xrx200_alloc_skb(ch);
  1191. +
  1192. + ch->dma.desc++;
  1193. + ch->dma.desc %= LTQ_DESC_NUM;
  1194. +
  1195. + if (ret) {
  1196. + netdev_err(dev,
  1197. + "failed to allocate new rx buffer\n");
  1198. + return;
  1199. + }
  1200. +
  1201. + skb_put(skb, len);
  1202. +#ifdef SW_ROUTING
  1203. + skb_pull(skb, 8);
  1204. +#endif
  1205. + skb->dev = dev;
  1206. + skb->protocol = eth_type_trans(skb, dev);
  1207. + netif_receive_skb(skb);
  1208. + priv->stats.rx_packets++;
  1209. + priv->stats.rx_bytes+=len;
  1210. +}
  1211. +
  1212. +static int xrx200_poll_rx(struct napi_struct *napi, int budget)
  1213. +{
  1214. + struct xrx200_chan *ch = container_of(napi,
  1215. + struct xrx200_chan, napi);
  1216. + struct xrx200_priv *priv = netdev_priv(ch->devs[0]);
  1217. + int rx = 0;
  1218. + int complete = 0;
  1219. +
  1220. + while ((rx < budget) && !complete) {
  1221. + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
  1222. + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
  1223. +#ifdef SW_ROUTING
  1224. + struct sk_buff *skb = ch->skb[ch->dma.desc];
  1225. + u8 *special_tag = (u8*)skb->data;
  1226. + int port = (special_tag[7] >> SPPID_SHIFT) & SPPID_MASK;
  1227. + xrx200_hw_receive(ch, priv->hw->port_map[port]);
  1228. +#else
  1229. + xrx200_hw_receive(ch, 0);
  1230. +#endif
  1231. + rx++;
  1232. + } else {
  1233. + complete = 1;
  1234. + }
  1235. + }
  1236. +
  1237. + if (complete || !rx) {
  1238. + napi_complete(&ch->napi);
  1239. + ltq_dma_enable_irq(&ch->dma);
  1240. + }
  1241. +
  1242. + return rx;
  1243. +}
  1244. +
  1245. +static void xrx200_tx_housekeeping(unsigned long ptr)
  1246. +{
  1247. + struct xrx200_chan *ch = (struct xrx200_chan *) ptr;
  1248. + int pkts = 0;
  1249. + int i;
  1250. +
  1251. + spin_lock_bh(&ch->lock);
  1252. + ltq_dma_ack_irq(&ch->dma);
  1253. + while ((ch->dma.desc_base[ch->tx_free].ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
  1254. + struct sk_buff *skb = ch->skb[ch->tx_free];
  1255. +
  1256. + pkts++;
  1257. + ch->skb[ch->tx_free] = NULL;
  1258. + dev_kfree_skb(skb);
  1259. + memset(&ch->dma.desc_base[ch->tx_free], 0,
  1260. + sizeof(struct ltq_dma_desc));
  1261. + ch->tx_free++;
  1262. + ch->tx_free %= LTQ_DESC_NUM;
  1263. + }
  1264. + ltq_dma_enable_irq(&ch->dma);
  1265. + spin_unlock_bh(&ch->lock);
  1266. +
  1267. + if (!pkts)
  1268. + return;
  1269. +
  1270. + for (i = 0; i < XRX200_MAX_DEV && ch->devs[i]; i++)
  1271. + netif_wake_queue(ch->devs[i]);
  1272. +}
  1273. +
  1274. +static struct net_device_stats *xrx200_get_stats (struct net_device *dev)
  1275. +{
  1276. + struct xrx200_priv *priv = netdev_priv(dev);
  1277. +
  1278. + return &priv->stats;
  1279. +}
  1280. +
  1281. +static void xrx200_tx_timeout(struct net_device *dev, unsigned int txqueue)
  1282. +{
  1283. + struct xrx200_priv *priv = netdev_priv(dev);
  1284. +
  1285. + printk(KERN_ERR "%s: transmit timed out, disable the dma channel irq\n", dev->name);
  1286. +
  1287. + priv->stats.tx_errors++;
  1288. + netif_wake_queue(dev);
  1289. +}
  1290. +
  1291. +static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1292. +{
  1293. + struct xrx200_priv *priv = netdev_priv(dev);
  1294. + struct xrx200_chan *ch;
  1295. + struct ltq_dma_desc *desc;
  1296. + u32 byte_offset;
  1297. + int ret = NETDEV_TX_OK;
  1298. + int len;
  1299. +#ifdef SW_ROUTING
  1300. + u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | DPID_ENABLE;
  1301. +#endif
  1302. + if(priv->id)
  1303. + ch = &priv->hw->chan[XRX200_DMA_TX_2];
  1304. + else
  1305. + ch = &priv->hw->chan[XRX200_DMA_TX];
  1306. +
  1307. + desc = &ch->dma.desc_base[ch->dma.desc];
  1308. +
  1309. + skb->dev = dev;
  1310. + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
  1311. +
  1312. +#ifdef SW_ROUTING
  1313. + if (is_multicast_ether_addr(eth_hdr(skb)->h_dest)) {
  1314. + u16 port_map = priv->port_map;
  1315. +
  1316. + if (priv->sw && skb->protocol == htons(ETH_P_8021Q)) {
  1317. + u16 vid;
  1318. + int i;
  1319. +
  1320. + port_map = 0;
  1321. + if (!__vlan_get_tag(skb, &vid)) {
  1322. + for (i = 0; i < XRX200_MAX_VLAN; i++) {
  1323. + if (priv->hw->vlan_vid[i] != vid)
  1324. + continue;
  1325. + port_map = priv->hw->vlan_port_map[i];
  1326. + break;
  1327. + }
  1328. + }
  1329. + }
  1330. +
  1331. + special_tag |= (port_map << PORT_MAP_SHIFT) |
  1332. + PORT_MAP_SEL | PORT_MAP_EN;
  1333. + }
  1334. + if(priv->wan)
  1335. + special_tag |= (1 << DPID_SHIFT);
  1336. + if(skb_headroom(skb) < 4) {
  1337. + struct sk_buff *tmp = skb_realloc_headroom(skb, 4);
  1338. + dev_kfree_skb_any(skb);
  1339. + skb = tmp;
  1340. + }
  1341. + skb_push(skb, 4);
  1342. + memcpy(skb->data, &special_tag, sizeof(u32));
  1343. + len += 4;
  1344. +#endif
  1345. +
  1346. + /* dma needs to start on a 16 byte aligned address */
  1347. + byte_offset = CPHYSADDR(skb->data) % 16;
  1348. +
  1349. + spin_lock_bh(&ch->lock);
  1350. + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
  1351. + netdev_err(dev, "tx ring full\n");
  1352. + netif_stop_queue(dev);
  1353. + ret = NETDEV_TX_BUSY;
  1354. + goto out;
  1355. + }
  1356. +
  1357. + ch->skb[ch->dma.desc] = skb;
  1358. +
  1359. + netif_trans_update(dev);
  1360. +
  1361. + desc->addr = ((unsigned int) dma_map_single(ch->dma.dev, skb->data, len,
  1362. + DMA_TO_DEVICE)) - byte_offset;
  1363. + wmb();
  1364. + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
  1365. + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
  1366. + ch->dma.desc++;
  1367. + ch->dma.desc %= LTQ_DESC_NUM;
  1368. + if (ch->dma.desc == ch->tx_free)
  1369. + netif_stop_queue(dev);
  1370. +
  1371. +
  1372. + priv->stats.tx_packets++;
  1373. + priv->stats.tx_bytes+=len;
  1374. +
  1375. +out:
  1376. + spin_unlock_bh(&ch->lock);
  1377. +
  1378. + return ret;
  1379. +}
  1380. +
  1381. +static irqreturn_t xrx200_dma_irq(int irq, void *priv)
  1382. +{
  1383. + struct xrx200_hw *hw = priv;
  1384. + int chnr = irq - XRX200_DMA_IRQ;
  1385. + struct xrx200_chan *ch = &hw->chan[chnr];
  1386. +
  1387. + ltq_dma_disable_irq(&ch->dma);
  1388. + ltq_dma_ack_irq(&ch->dma);
  1389. +
  1390. + if (chnr % 2)
  1391. + tasklet_schedule(&ch->tasklet);
  1392. + else
  1393. + napi_schedule(&ch->napi);
  1394. +
  1395. + return IRQ_HANDLED;
  1396. +}
  1397. +
  1398. +static int xrx200_dma_init(struct device *dev, struct xrx200_hw *hw)
  1399. +{
  1400. + int i, err = 0;
  1401. +
  1402. + ltq_dma_init_port(DMA_PORT_ETOP);
  1403. +
  1404. + for (i = 0; i < 8 && !err; i++) {
  1405. + int irq = XRX200_DMA_IRQ + i;
  1406. + struct xrx200_chan *ch = &hw->chan[i];
  1407. +
  1408. + spin_lock_init(&ch->lock);
  1409. +
  1410. + ch->idx = ch->dma.nr = i;
  1411. + ch->dma.dev = dev;
  1412. +
  1413. + if (i == XRX200_DMA_TX) {
  1414. + ltq_dma_alloc_tx(&ch->dma);
  1415. + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx", hw);
  1416. + } else if (i == XRX200_DMA_TX_2) {
  1417. + ltq_dma_alloc_tx(&ch->dma);
  1418. + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx_2", hw);
  1419. + } else if (i == XRX200_DMA_RX) {
  1420. + ltq_dma_alloc_rx(&ch->dma);
  1421. + for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
  1422. + ch->dma.desc++)
  1423. + if (xrx200_alloc_skb(ch))
  1424. + err = -ENOMEM;
  1425. + ch->dma.desc = 0;
  1426. + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_rx", hw);
  1427. + } else
  1428. + continue;
  1429. +
  1430. + if (!err)
  1431. + ch->dma.irq = irq;
  1432. + else
  1433. + pr_err("net-xrx200: failed to request irq %d\n", irq);
  1434. + }
  1435. +
  1436. + return err;
  1437. +}
  1438. +
  1439. +#ifdef SW_POLLING
  1440. +static void xrx200_gmac_update(struct xrx200_port *port)
  1441. +{
  1442. + u16 phyaddr = port->phydev->mdio.addr & MDIO_PHY_ADDR_MASK;
  1443. + u16 miimode = ltq_mii_r32(MII_CFG(port->num)) & MII_CFG_MODE_MASK;
  1444. + u16 miirate = 0;
  1445. +
  1446. + switch (port->phydev->speed) {
  1447. + case SPEED_1000:
  1448. + phyaddr |= MDIO_PHY_SPEED_G1;
  1449. + miirate = MII_CFG_RATE_M125;
  1450. + break;
  1451. +
  1452. + case SPEED_100:
  1453. + phyaddr |= MDIO_PHY_SPEED_M100;
  1454. + switch (miimode) {
  1455. + case MII_CFG_MODE_RMIIM:
  1456. + case MII_CFG_MODE_RMIIP:
  1457. + miirate = MII_CFG_RATE_M50;
  1458. + break;
  1459. + default:
  1460. + miirate = MII_CFG_RATE_M25;
  1461. + break;
  1462. + }
  1463. + break;
  1464. +
  1465. + default:
  1466. + phyaddr |= MDIO_PHY_SPEED_M10;
  1467. + miirate = MII_CFG_RATE_M2P5;
  1468. + break;
  1469. + }
  1470. +
  1471. + if (port->phydev->link)
  1472. + phyaddr |= MDIO_PHY_LINK_UP;
  1473. + else
  1474. + phyaddr |= MDIO_PHY_LINK_DOWN;
  1475. +
  1476. + if (port->phydev->duplex == DUPLEX_FULL)
  1477. + phyaddr |= MDIO_PHY_FDUP_EN;
  1478. + else
  1479. + phyaddr |= MDIO_PHY_FDUP_DIS;
  1480. +
  1481. + ltq_mdio_w32_mask(MDIO_UPDATE_MASK, phyaddr, MDIO_PHY(port->num));
  1482. + ltq_mii_w32_mask(MII_CFG_RATE_MASK, miirate, MII_CFG(port->num));
  1483. + udelay(1);
  1484. +}
  1485. +#else
  1486. +static void xrx200_gmac_update(struct xrx200_port *port)
  1487. +{
  1488. +
  1489. +}
  1490. +#endif
  1491. +
  1492. +static void xrx200_mdio_link(struct net_device *dev)
  1493. +{
  1494. + struct xrx200_priv *priv = netdev_priv(dev);
  1495. + int i;
  1496. +
  1497. + for (i = 0; i < priv->num_port; i++) {
  1498. + if (!priv->port[i].phydev)
  1499. + continue;
  1500. +
  1501. + if (priv->port[i].link != priv->port[i].phydev->link) {
  1502. + xrx200_gmac_update(&priv->port[i]);
  1503. + priv->port[i].link = priv->port[i].phydev->link;
  1504. + netdev_info(dev, "port %d %s link\n",
  1505. + priv->port[i].num,
  1506. + (priv->port[i].link)?("got"):("lost"));
  1507. + }
  1508. + }
  1509. +}
  1510. +
  1511. +static inline int xrx200_mdio_poll(struct mii_bus *bus)
  1512. +{
  1513. + unsigned cnt = 10000;
  1514. +
  1515. + while (likely(cnt--)) {
  1516. + unsigned ctrl = ltq_mdio_r32(MDIO_CTRL);
  1517. + if ((ctrl & MDIO_BUSY) == 0)
  1518. + return 0;
  1519. + }
  1520. +
  1521. + return 1;
  1522. +}
  1523. +
  1524. +static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
  1525. +{
  1526. + if (xrx200_mdio_poll(bus))
  1527. + return 1;
  1528. +
  1529. + ltq_mdio_w32(val, MDIO_WRITE);
  1530. + ltq_mdio_w32(MDIO_BUSY | MDIO_WR |
  1531. + ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) |
  1532. + (reg & MDIO_MASK),
  1533. + MDIO_CTRL);
  1534. +
  1535. + return 0;
  1536. +}
  1537. +
  1538. +static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg)
  1539. +{
  1540. + if (xrx200_mdio_poll(bus))
  1541. + return -1;
  1542. +
  1543. + ltq_mdio_w32(MDIO_BUSY | MDIO_RD |
  1544. + ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) |
  1545. + (reg & MDIO_MASK),
  1546. + MDIO_CTRL);
  1547. +
  1548. + if (xrx200_mdio_poll(bus))
  1549. + return -1;
  1550. +
  1551. + return ltq_mdio_r32(MDIO_READ);
  1552. +}
  1553. +
  1554. +static int xrx200_phy_has_link(struct net_device *dev)
  1555. +{
  1556. + struct xrx200_priv *priv = netdev_priv(dev);
  1557. + int i;
  1558. +
  1559. + for (i = 0; i < priv->num_port; i++) {
  1560. + if (!priv->port[i].phydev)
  1561. + continue;
  1562. +
  1563. + if (priv->port[i].phydev->link)
  1564. + return 1;
  1565. + }
  1566. +
  1567. + return 0;
  1568. +}
  1569. +
  1570. +static void xrx200_phy_link_change(struct phy_device *phydev, bool up)
  1571. +{
  1572. + struct net_device *netdev = phydev->attached_dev;
  1573. +
  1574. + if (up)
  1575. + netif_carrier_on(netdev);
  1576. + else if (!xrx200_phy_has_link(netdev))
  1577. + netif_carrier_off(netdev);
  1578. +
  1579. + phydev->adjust_link(netdev);
  1580. +}
  1581. +
  1582. +static int xrx200_mdio_probe(struct net_device *dev, struct xrx200_port *port)
  1583. +{
  1584. + struct xrx200_priv *priv = netdev_priv(dev);
  1585. + struct phy_device *phydev = NULL;
  1586. + unsigned val;
  1587. +
  1588. + phydev = mdiobus_get_phy(priv->hw->mii_bus, port->phy_addr);
  1589. +
  1590. + if (!phydev) {
  1591. + netdev_err(dev, "no PHY found\n");
  1592. + return -ENODEV;
  1593. + }
  1594. +
  1595. + phydev = phy_connect(dev, phydev_name(phydev), &xrx200_mdio_link,
  1596. + port->phy_if);
  1597. +
  1598. + if (IS_ERR(phydev)) {
  1599. + netdev_err(dev, "Could not attach to PHY\n");
  1600. + return PTR_ERR(phydev);
  1601. + }
  1602. +
  1603. + linkmode_zero(phydev->supported);
  1604. + linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
  1605. + linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported);
  1606. + linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, phydev->supported);
  1607. + linkmode_set_bit_array(phy_10_100_features_array,
  1608. + ARRAY_SIZE(phy_10_100_features_array),
  1609. + phydev->supported);
  1610. + linkmode_set_bit_array(phy_gbit_features_array,
  1611. + ARRAY_SIZE(phy_gbit_features_array),
  1612. + phydev->supported);
  1613. + linkmode_copy(phydev->advertising, phydev->supported);
  1614. +
  1615. + port->phydev = phydev;
  1616. + phydev->phy_link_change = xrx200_phy_link_change;
  1617. +
  1618. + phy_attached_info(phydev);
  1619. +
  1620. +#ifdef SW_POLLING
  1621. + phy_read_status(phydev);
  1622. +
  1623. + val = xrx200_mdio_rd(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000);
  1624. + val |= ADVERTIZE_MPD;
  1625. + xrx200_mdio_wr(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val);
  1626. + xrx200_mdio_wr(priv->hw->mii_bus, 0, 0, 0x1040);
  1627. +
  1628. + phy_start_aneg(phydev);
  1629. +#endif
  1630. + return 0;
  1631. +}
  1632. +
  1633. +static void xrx200_port_config(struct xrx200_priv *priv,
  1634. + const struct xrx200_port *port)
  1635. +{
  1636. + u16 miimode = 0;
  1637. +
  1638. + switch (port->num) {
  1639. + case 0: /* xMII0 */
  1640. + case 1: /* xMII1 */
  1641. + switch (port->phy_if) {
  1642. + case PHY_INTERFACE_MODE_MII:
  1643. + if (port->flags & XRX200_PORT_TYPE_PHY)
  1644. + /* MII MAC mode, connected to external PHY */
  1645. + miimode = MII_CFG_MODE_MIIM;
  1646. + else
  1647. + /* MII PHY mode, connected to external MAC */
  1648. + miimode = MII_CFG_MODE_MIIP;
  1649. + break;
  1650. + case PHY_INTERFACE_MODE_RMII:
  1651. + if (port->flags & XRX200_PORT_TYPE_PHY)
  1652. + /* RMII MAC mode, connected to external PHY */
  1653. + miimode = MII_CFG_MODE_RMIIM;
  1654. + else
  1655. + /* RMII PHY mode, connected to external MAC */
  1656. + miimode = MII_CFG_MODE_RMIIP;
  1657. + break;
  1658. + case PHY_INTERFACE_MODE_RGMII:
  1659. + /* RGMII MAC mode, connected to external PHY */
  1660. + miimode = MII_CFG_MODE_RGMII;
  1661. + break;
  1662. + default:
  1663. + break;
  1664. + }
  1665. + break;
  1666. + case 2: /* internal GPHY0 */
  1667. + case 3: /* internal GPHY0 */
  1668. + case 4: /* internal GPHY1 */
  1669. + switch (port->phy_if) {
  1670. + case PHY_INTERFACE_MODE_MII:
  1671. + case PHY_INTERFACE_MODE_GMII:
  1672. + /* MII MAC mode, connected to internal GPHY */
  1673. + miimode = MII_CFG_MODE_MIIM;
  1674. + break;
  1675. + default:
  1676. + break;
  1677. + }
  1678. + break;
  1679. + case 5: /* internal GPHY1 or xMII2 */
  1680. + switch (port->phy_if) {
  1681. + case PHY_INTERFACE_MODE_MII:
  1682. + /* MII MAC mode, connected to internal GPHY */
  1683. + miimode = MII_CFG_MODE_MIIM;
  1684. + break;
  1685. + case PHY_INTERFACE_MODE_RGMII:
  1686. + /* RGMII MAC mode, connected to external PHY */
  1687. + miimode = MII_CFG_MODE_RGMII;
  1688. + break;
  1689. + default:
  1690. + break;
  1691. + }
  1692. + break;
  1693. + default:
  1694. + break;
  1695. + }
  1696. +
  1697. + ltq_mii_w32_mask(MII_CFG_MODE_MASK, miimode | MII_CFG_EN,
  1698. + MII_CFG(port->num));
  1699. +}
  1700. +
  1701. +static int xrx200_init(struct net_device *dev)
  1702. +{
  1703. + struct xrx200_priv *priv = netdev_priv(dev);
  1704. + struct sockaddr mac;
  1705. + int err, i;
  1706. +
  1707. +#ifndef SW_POLLING
  1708. + unsigned int reg = 0;
  1709. +
  1710. + /* enable auto polling */
  1711. + for (i = 0; i < priv->num_port; i++)
  1712. + reg |= BIT(priv->port[i].num);
  1713. + ltq_mdio_w32(reg, MDIO_CLK_CFG0);
  1714. + ltq_mdio_w32(MDIO1_25MHZ, MDIO_CLK_CFG1);
  1715. +#endif
  1716. +
  1717. + /* setup each port */
  1718. + for (i = 0; i < priv->num_port; i++)
  1719. + xrx200_port_config(priv, &priv->port[i]);
  1720. +
  1721. + memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
  1722. + if (!is_valid_ether_addr(mac.sa_data)) {
  1723. + pr_warn("net-xrx200: invalid MAC, using random\n");
  1724. + eth_random_addr(mac.sa_data);
  1725. + dev->addr_assign_type |= NET_ADDR_RANDOM;
  1726. + }
  1727. +
  1728. + err = eth_mac_addr(dev, &mac);
  1729. + if (err)
  1730. + goto err_netdev;
  1731. +
  1732. + for (i = 0; i < priv->num_port; i++)
  1733. + if (xrx200_mdio_probe(dev, &priv->port[i]))
  1734. + pr_warn("xrx200-mdio: probing phy of port %d failed\n",
  1735. + priv->port[i].num);
  1736. +
  1737. + return 0;
  1738. +
  1739. +err_netdev:
  1740. + unregister_netdev(dev);
  1741. + free_netdev(dev);
  1742. + return err;
  1743. +}
  1744. +
  1745. +static void xrx200_pci_microcode(void)
  1746. +{
  1747. + int i;
  1748. +
  1749. + ltq_switch_w32_mask(PCE_TBL_CFG_ADDR_MASK | PCE_TBL_CFG_ADWR_MASK,
  1750. + PCE_TBL_CFG_ADWR, PCE_TBL_CTRL);
  1751. + ltq_switch_w32(0, PCE_TBL_MASK);
  1752. +
  1753. + for (i = 0; i < ARRAY_SIZE(pce_microcode); i++) {
  1754. + ltq_switch_w32(i, PCE_TBL_ADDR);
  1755. + ltq_switch_w32(pce_microcode[i].val[3], PCE_TBL_VAL(0));
  1756. + ltq_switch_w32(pce_microcode[i].val[2], PCE_TBL_VAL(1));
  1757. + ltq_switch_w32(pce_microcode[i].val[1], PCE_TBL_VAL(2));
  1758. + ltq_switch_w32(pce_microcode[i].val[0], PCE_TBL_VAL(3));
  1759. +
  1760. + // start the table access:
  1761. + ltq_switch_w32_mask(0, PCE_TBL_BUSY, PCE_TBL_CTRL);
  1762. + while (ltq_switch_r32(PCE_TBL_CTRL) & PCE_TBL_BUSY);
  1763. + }
  1764. +
  1765. + /* tell the switch that the microcode is loaded */
  1766. + ltq_switch_w32_mask(0, BIT(3), PCE_GCTRL_REG(0));
  1767. +}
  1768. +
  1769. +static void xrx200_hw_init(struct xrx200_hw *hw)
  1770. +{
  1771. + int i;
  1772. +
  1773. + /* enable clock gate */
  1774. + clk_enable(hw->clk);
  1775. +
  1776. + ltq_switch_w32(1, 0);
  1777. + mdelay(100);
  1778. + ltq_switch_w32(0, 0);
  1779. + /*
  1780. + * TODO: we should really disbale all phys/miis here and explicitly
  1781. + * enable them in the device secific init function
  1782. + */
  1783. +
  1784. + /* disable port fetch/store dma */
  1785. + for (i = 0; i < 7; i++ ) {
  1786. + ltq_switch_w32(0, FDMA_PCTRLx(i));
  1787. + ltq_switch_w32(0, SDMA_PCTRLx(i));
  1788. + }
  1789. +
  1790. + /* enable Switch */
  1791. + ltq_mdio_w32_mask(0, MDIO_GLOB_ENABLE, MDIO_GLOB);
  1792. +
  1793. + /* load the pce microcode */
  1794. + xrx200_pci_microcode();
  1795. +
  1796. + /* Default unknown Broadcat/Multicast/Unicast port maps */
  1797. + ltq_switch_w32(0x40, PCE_PMAP1);
  1798. + ltq_switch_w32(0x40, PCE_PMAP2);
  1799. + ltq_switch_w32(0x40, PCE_PMAP3);
  1800. +
  1801. + /* RMON Counter Enable for all physical ports */
  1802. + for (i = 0; i < 7; i++)
  1803. + ltq_switch_w32(0x1, BM_PCFG(i));
  1804. +
  1805. + /* disable auto polling */
  1806. + ltq_mdio_w32(0x0, MDIO_CLK_CFG0);
  1807. +
  1808. + /* enable port statistic counters */
  1809. + for (i = 0; i < 7; i++)
  1810. + ltq_switch_w32(0x1, BM_PCFGx(i));
  1811. +
  1812. + /* set IPG to 12 */
  1813. + ltq_pmac_w32_mask(PMAC_IPG_MASK, 0xb, PMAC_RX_IPG);
  1814. +
  1815. +#ifdef SW_ROUTING
  1816. + /* enable status header, enable CRC */
  1817. + ltq_pmac_w32_mask(0,
  1818. + PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC | PMAC_HD_CTL_RC,
  1819. + PMAC_HD_CTL);
  1820. +#else
  1821. + /* disable status header, enable CRC */
  1822. + ltq_pmac_w32_mask(PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS,
  1823. + PMAC_HD_CTL_AC | PMAC_HD_CTL_RC,
  1824. + PMAC_HD_CTL);
  1825. +#endif
  1826. +
  1827. + /* enable port fetch/store dma & VLAN Modification */
  1828. + for (i = 0; i < 7; i++ ) {
  1829. + ltq_switch_w32_mask(0, 0x19, FDMA_PCTRLx(i));
  1830. + ltq_switch_w32_mask(0, 0x01, SDMA_PCTRLx(i));
  1831. + ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(i, 0));
  1832. + }
  1833. +
  1834. + /* enable special tag insertion on cpu port */
  1835. + ltq_switch_w32_mask(0, 0x02, FDMA_PCTRLx(6));
  1836. + ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(6, 0));
  1837. + ltq_switch_w32_mask(0, BIT(3), MAC_CTRL_REG(6, 2));
  1838. + ltq_switch_w32(1518 + 8 + 4 * 2, MAC_FLEN_REG);
  1839. + xrx200sw_write_x(1, XRX200_BM_QUEUE_GCTRL_GL_MOD, 0);
  1840. +
  1841. + for (i = 0; i < XRX200_MAX_VLAN; i++)
  1842. + hw->vlan_vid[i] = i;
  1843. +}
  1844. +
  1845. +static void xrx200_hw_cleanup(struct xrx200_hw *hw)
  1846. +{
  1847. + int i;
  1848. +
  1849. + /* disable the switch */
  1850. + ltq_mdio_w32_mask(MDIO_GLOB_ENABLE, 0, MDIO_GLOB);
  1851. +
  1852. + /* free the channels and IRQs */
  1853. + for (i = 0; i < 2; i++) {
  1854. + ltq_dma_free(&hw->chan[i].dma);
  1855. + if (hw->chan[i].dma.irq)
  1856. + free_irq(hw->chan[i].dma.irq, hw);
  1857. + }
  1858. +
  1859. + /* free the allocated RX ring */
  1860. + for (i = 0; i < LTQ_DESC_NUM; i++)
  1861. + dev_kfree_skb_any(hw->chan[XRX200_DMA_RX].skb[i]);
  1862. +
  1863. + /* clear the mdio bus */
  1864. + mdiobus_unregister(hw->mii_bus);
  1865. + mdiobus_free(hw->mii_bus);
  1866. +
  1867. + /* release the clock */
  1868. + clk_disable(hw->clk);
  1869. + clk_put(hw->clk);
  1870. +}
  1871. +
  1872. +static int xrx200_of_mdio(struct xrx200_hw *hw, struct device_node *np)
  1873. +{
  1874. + hw->mii_bus = mdiobus_alloc();
  1875. + if (!hw->mii_bus)
  1876. + return -ENOMEM;
  1877. +
  1878. + hw->mii_bus->read = xrx200_mdio_rd;
  1879. + hw->mii_bus->write = xrx200_mdio_wr;
  1880. + hw->mii_bus->name = "lantiq,xrx200-mdio";
  1881. + snprintf(hw->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
  1882. +
  1883. + if (of_mdiobus_register(hw->mii_bus, np)) {
  1884. + mdiobus_free(hw->mii_bus);
  1885. + return -ENXIO;
  1886. + }
  1887. +
  1888. + return 0;
  1889. +}
  1890. +
  1891. +static void xrx200_of_port(struct xrx200_priv *priv, struct device_node *port)
  1892. +{
  1893. + const __be32 *addr, *id = of_get_property(port, "reg", NULL);
  1894. + struct xrx200_port *p = &priv->port[priv->num_port];
  1895. + int ret;
  1896. +
  1897. + if (!id)
  1898. + return;
  1899. +
  1900. + memset(p, 0, sizeof(struct xrx200_port));
  1901. + p->phy_node = of_parse_phandle(port, "phy-handle", 0);
  1902. + addr = of_get_property(p->phy_node, "reg", NULL);
  1903. + if (!addr)
  1904. + return;
  1905. +
  1906. + p->num = *id;
  1907. + p->phy_addr = *addr;
  1908. +
  1909. + ret = of_get_phy_mode(port, &p->phy_if);
  1910. + if (ret)
  1911. + pr_err("Can't find phy-mode for port\n");
  1912. +
  1913. + if (p->phy_addr > 0x10)
  1914. + p->flags = XRX200_PORT_TYPE_MAC;
  1915. + else
  1916. + p->flags = XRX200_PORT_TYPE_PHY;
  1917. + priv->num_port++;
  1918. +
  1919. + p->gpio = of_get_gpio_flags(port, 0, &p->gpio_flags);
  1920. + if (gpio_is_valid(p->gpio))
  1921. + if (!gpio_request(p->gpio, "phy-reset")) {
  1922. + gpio_direction_output(p->gpio,
  1923. + (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (1) : (0));
  1924. + udelay(100);
  1925. + gpio_set_value(p->gpio, (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1));
  1926. + }
  1927. + /* is this port a wan port ? */
  1928. + if (priv->wan)
  1929. + priv->hw->wan_map |= BIT(p->num);
  1930. +
  1931. + priv->port_map |= BIT(p->num);
  1932. +
  1933. + /* store the port id in the hw struct so we can map ports -> devices */
  1934. + priv->hw->port_map[p->num] = priv->hw->num_devs;
  1935. +
  1936. + /* store the phy addr in the hw struct so we can map ports -> phys */
  1937. + priv->hw->phy_addr[p->num] = p->phy_addr;
  1938. +}
  1939. +
  1940. +static const struct net_device_ops xrx200_netdev_ops = {
  1941. + .ndo_init = xrx200_init,
  1942. + .ndo_open = xrx200_open,
  1943. + .ndo_stop = xrx200_close,
  1944. + .ndo_start_xmit = xrx200_start_xmit,
  1945. + .ndo_set_mac_address = eth_mac_addr,
  1946. + .ndo_validate_addr = eth_validate_addr,
  1947. + .ndo_get_stats = xrx200_get_stats,
  1948. + .ndo_tx_timeout = xrx200_tx_timeout,
  1949. +};
  1950. +
  1951. +static void xrx200_of_iface(struct xrx200_hw *hw, struct device_node *iface, struct device *dev)
  1952. +{
  1953. + struct xrx200_priv *priv;
  1954. + struct device_node *port;
  1955. + const __be32 *wan;
  1956. + const u8 *mac;
  1957. +
  1958. + /* alloc the network device */
  1959. + hw->devs[hw->num_devs] = alloc_etherdev(sizeof(struct xrx200_priv));
  1960. + if (!hw->devs[hw->num_devs])
  1961. + return;
  1962. +
  1963. + /* setup the network device */
  1964. + strcpy(hw->devs[hw->num_devs]->name, "eth%d");
  1965. + hw->devs[hw->num_devs]->netdev_ops = &xrx200_netdev_ops;
  1966. + hw->devs[hw->num_devs]->watchdog_timeo = XRX200_TX_TIMEOUT;
  1967. + hw->devs[hw->num_devs]->needed_headroom = XRX200_HEADROOM;
  1968. + SET_NETDEV_DEV(hw->devs[hw->num_devs], dev);
  1969. +
  1970. + /* setup our private data */
  1971. + priv = netdev_priv(hw->devs[hw->num_devs]);
  1972. + priv->hw = hw;
  1973. + priv->id = hw->num_devs;
  1974. +
  1975. + mac = of_get_mac_address(iface);
  1976. + if (!IS_ERR(mac))
  1977. + memcpy(priv->mac, mac, ETH_ALEN);
  1978. +
  1979. + /* is this the wan interface ? */
  1980. + wan = of_get_property(iface, "lantiq,wan", NULL);
  1981. + if (wan && (*wan == 1))
  1982. + priv->wan = 1;
  1983. +
  1984. + /* should the switch be enabled on this interface ? */
  1985. + if (of_find_property(iface, "lantiq,switch", NULL))
  1986. + priv->sw = 1;
  1987. +
  1988. + /* load the ports that are part of the interface */
  1989. + for_each_child_of_node(iface, port)
  1990. + if (of_device_is_compatible(port, "lantiq,xrx200-pdi-port"))
  1991. + xrx200_of_port(priv, port);
  1992. +
  1993. + /* register the actual device */
  1994. + if (!register_netdev(hw->devs[hw->num_devs]))
  1995. + hw->num_devs++;
  1996. +}
  1997. +
  1998. +static struct xrx200_hw xrx200_hw;
  1999. +
  2000. +static int xrx200_probe(struct platform_device *pdev)
  2001. +{
  2002. + struct resource *res[4];
  2003. + struct device_node *mdio_np, *iface_np, *phy_np;
  2004. + struct of_phandle_iterator it;
  2005. + int err;
  2006. + int i;
  2007. +
  2008. + /* load the memory ranges */
  2009. + for (i = 0; i < 4; i++) {
  2010. + res[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
  2011. + if (!res[i]) {
  2012. + dev_err(&pdev->dev, "failed to get resources\n");
  2013. + return -ENOENT;
  2014. + }
  2015. + }
  2016. + xrx200_switch_membase = devm_ioremap_resource(&pdev->dev, res[0]);
  2017. + xrx200_mdio_membase = devm_ioremap_resource(&pdev->dev, res[1]);
  2018. + xrx200_mii_membase = devm_ioremap_resource(&pdev->dev, res[2]);
  2019. + xrx200_pmac_membase = devm_ioremap_resource(&pdev->dev, res[3]);
  2020. + if (!xrx200_switch_membase || !xrx200_mdio_membase ||
  2021. + !xrx200_mii_membase || !xrx200_pmac_membase) {
  2022. + dev_err(&pdev->dev, "failed to request and remap io ranges \n");
  2023. + return -ENOMEM;
  2024. + }
  2025. +
  2026. + of_for_each_phandle(&it, err, pdev->dev.of_node, "lantiq,phys", NULL, 0) {
  2027. + phy_np = it.node;
  2028. + if (phy_np) {
  2029. + struct platform_device *phy = of_find_device_by_node(phy_np);
  2030. +
  2031. + of_node_put(phy_np);
  2032. + if (!platform_get_drvdata(phy))
  2033. + return -EPROBE_DEFER;
  2034. + }
  2035. + }
  2036. +
  2037. + /* get the clock */
  2038. + xrx200_hw.clk = clk_get(&pdev->dev, NULL);
  2039. + if (IS_ERR(xrx200_hw.clk)) {
  2040. + dev_err(&pdev->dev, "failed to get clock\n");
  2041. + return PTR_ERR(xrx200_hw.clk);
  2042. + }
  2043. +
  2044. + /* bring up the dma engine and IP core */
  2045. + xrx200_dma_init(&pdev->dev, &xrx200_hw);
  2046. + xrx200_hw_init(&xrx200_hw);
  2047. + tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw.chan[XRX200_DMA_TX]);
  2048. + tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX_2].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw.chan[XRX200_DMA_TX_2]);
  2049. +
  2050. + /* bring up the mdio bus */
  2051. + mdio_np = of_find_compatible_node(pdev->dev.of_node, NULL,
  2052. + "lantiq,xrx200-mdio");
  2053. + if (mdio_np)
  2054. + if (xrx200_of_mdio(&xrx200_hw, mdio_np))
  2055. + dev_err(&pdev->dev, "mdio probe failed\n");
  2056. +
  2057. + /* load the interfaces */
  2058. + for_each_child_of_node(pdev->dev.of_node, iface_np)
  2059. + if (of_device_is_compatible(iface_np, "lantiq,xrx200-pdi")) {
  2060. + if (xrx200_hw.num_devs < XRX200_MAX_DEV)
  2061. + xrx200_of_iface(&xrx200_hw, iface_np, &pdev->dev);
  2062. + else
  2063. + dev_err(&pdev->dev,
  2064. + "only %d interfaces allowed\n",
  2065. + XRX200_MAX_DEV);
  2066. + }
  2067. +
  2068. + if (!xrx200_hw.num_devs) {
  2069. + xrx200_hw_cleanup(&xrx200_hw);
  2070. + dev_err(&pdev->dev, "failed to load interfaces\n");
  2071. + return -ENOENT;
  2072. + }
  2073. +
  2074. + xrx200sw_init(&xrx200_hw);
  2075. +
  2076. + /* set wan port mask */
  2077. + ltq_pmac_w32(xrx200_hw.wan_map, PMAC_EWAN);
  2078. +
  2079. + for (i = 0; i < xrx200_hw.num_devs; i++) {
  2080. + xrx200_hw.chan[XRX200_DMA_RX].devs[i] = xrx200_hw.devs[i];
  2081. + xrx200_hw.chan[XRX200_DMA_TX].devs[i] = xrx200_hw.devs[i];
  2082. + xrx200_hw.chan[XRX200_DMA_TX_2].devs[i] = xrx200_hw.devs[i];
  2083. + }
  2084. +
  2085. + /* setup NAPI */
  2086. + init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev);
  2087. + netif_napi_add(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev,
  2088. + &xrx200_hw.chan[XRX200_DMA_RX].napi, xrx200_poll_rx, 32);
  2089. +
  2090. + platform_set_drvdata(pdev, &xrx200_hw);
  2091. +
  2092. + return 0;
  2093. +}
  2094. +
  2095. +static int xrx200_remove(struct platform_device *pdev)
  2096. +{
  2097. + struct net_device *dev = platform_get_drvdata(pdev);
  2098. + struct xrx200_priv *priv;
  2099. +
  2100. + if (!dev)
  2101. + return 0;
  2102. +
  2103. + priv = netdev_priv(dev);
  2104. +
  2105. + /* free stack related instances */
  2106. + netif_stop_queue(dev);
  2107. + netif_napi_del(&xrx200_hw.chan[XRX200_DMA_RX].napi);
  2108. +
  2109. + /* shut down hardware */
  2110. + xrx200_hw_cleanup(&xrx200_hw);
  2111. +
  2112. + /* remove the actual device */
  2113. + unregister_netdev(dev);
  2114. + free_netdev(dev);
  2115. +
  2116. + return 0;
  2117. +}
  2118. +
  2119. +static const struct of_device_id xrx200_match[] = {
  2120. + { .compatible = "lantiq,xrx200-net" },
  2121. + {},
  2122. +};
  2123. +MODULE_DEVICE_TABLE(of, xrx200_match);
  2124. +
  2125. +static struct platform_driver xrx200_driver = {
  2126. + .probe = xrx200_probe,
  2127. + .remove = xrx200_remove,
  2128. + .driver = {
  2129. + .name = "lantiq,xrx200-net",
  2130. + .of_match_table = xrx200_match,
  2131. + .owner = THIS_MODULE,
  2132. + },
  2133. +};
  2134. +
  2135. +module_platform_driver(xrx200_driver);
  2136. +
  2137. +MODULE_AUTHOR("John Crispin <[email protected]>");
  2138. +MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet");
  2139. +MODULE_LICENSE("GPL");
  2140. --- /dev/null
  2141. +++ b/drivers/net/ethernet/lantiq_xrx200_legacy.h
  2142. @@ -0,0 +1,1328 @@
  2143. +/*
  2144. + * This program is free software; you can redistribute it and/or modify it
  2145. + * under the terms of the GNU General Public License version 2 as published
  2146. + * by the Free Software Foundation.
  2147. + *
  2148. + * This program is distributed in the hope that it will be useful,
  2149. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  2150. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  2151. + * GNU General Public License for more details.
  2152. + *
  2153. + * You should have received a copy of the GNU General Public License
  2154. + * along with this program; if not, write to the Free Software
  2155. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  2156. + *
  2157. + * Copyright (C) 2010 Lantiq Deutschland GmbH
  2158. + * Copyright (C) 2013 Antonios Vamporakis <[email protected]>
  2159. + *
  2160. + * VR9 switch registers extracted from 310TUJ0 switch api
  2161. + * WARNING mult values of 0x00 may not be correct
  2162. + *
  2163. + */
  2164. +
  2165. +enum {
  2166. +// XRX200_ETHSW_SWRES, /* Ethernet Switch ResetControl Register */
  2167. +// XRX200_ETHSW_SWRES_R1, /* Hardware Reset */
  2168. +// XRX200_ETHSW_SWRES_R0, /* Register Configuration */
  2169. +// XRX200_ETHSW_CLK_MAC_GAT, /* Ethernet Switch Clock ControlRegister */
  2170. +// XRX200_ETHSW_CLK_EXP_SLEEP, /* Exponent to put system into sleep */
  2171. +// XRX200_ETHSW_CLK_EXP_WAKE, /* Exponent to wake up system */
  2172. +// XRX200_ETHSW_CLK_CLK2_EN, /* CLK2 Input for MAC */
  2173. +// XRX200_ETHSW_CLK_EXT_DIV_EN, /* External Clock Divider Enable */
  2174. +// XRX200_ETHSW_CLK_RAM_DBG_EN, /* Clock Gating Enable */
  2175. +// XRX200_ETHSW_CLK_REG_GAT_EN, /* Clock Gating Enable */
  2176. +// XRX200_ETHSW_CLK_GAT_EN, /* Clock Gating Enable */
  2177. +// XRX200_ETHSW_CLK_MAC_GAT_EN, /* Clock Gating Enable */
  2178. +// XRX200_ETHSW_DBG_STEP, /* Ethernet Switch Debug ControlRegister */
  2179. +// XRX200_ETHSW_DBG_CLK_SEL, /* Trigger Enable */
  2180. +// XRX200_ETHSW_DBG_MON_EN, /* Monitoring Enable */
  2181. +// XRX200_ETHSW_DBG_TRIG_EN, /* Trigger Enable */
  2182. +// XRX200_ETHSW_DBG_MODE, /* Debug Mode */
  2183. +// XRX200_ETHSW_DBG_STEP_TIME, /* Clock Step Size */
  2184. +// XRX200_ETHSW_SSB_MODE, /* Ethernet Switch SharedSegment Buffer Mode Register */
  2185. +// XRX200_ETHSW_SSB_MODE_ADDE, /* Memory Address */
  2186. +// XRX200_ETHSW_SSB_MODE_MODE, /* Memory Access Mode */
  2187. +// XRX200_ETHSW_SSB_ADDR, /* Ethernet Switch SharedSegment Buffer Address Register */
  2188. +// XRX200_ETHSW_SSB_ADDR_ADDE, /* Memory Address */
  2189. +// XRX200_ETHSW_SSB_DATA, /* Ethernet Switch SharedSegment Buffer Data Register */
  2190. +// XRX200_ETHSW_SSB_DATA_DATA, /* Data Value */
  2191. +// XRX200_ETHSW_CAP_0, /* Ethernet Switch CapabilityRegister 0 */
  2192. +// XRX200_ETHSW_CAP_0_SPEED, /* Clock frequency */
  2193. +// XRX200_ETHSW_CAP_1, /* Ethernet Switch CapabilityRegister 1 */
  2194. +// XRX200_ETHSW_CAP_1_GMAC, /* MAC operation mode */
  2195. +// XRX200_ETHSW_CAP_1_QUEUE, /* Number of queues */
  2196. +// XRX200_ETHSW_CAP_1_VPORTS, /* Number of virtual ports */
  2197. +// XRX200_ETHSW_CAP_1_PPORTS, /* Number of physical ports */
  2198. +// XRX200_ETHSW_CAP_2, /* Ethernet Switch CapabilityRegister 2 */
  2199. +// XRX200_ETHSW_CAP_2_PACKETS, /* Number of packets */
  2200. +// XRX200_ETHSW_CAP_3, /* Ethernet Switch CapabilityRegister 3 */
  2201. +// XRX200_ETHSW_CAP_3_METERS, /* Number of traffic meters */
  2202. +// XRX200_ETHSW_CAP_3_SHAPERS, /* Number of traffic shapers */
  2203. +// XRX200_ETHSW_CAP_4, /* Ethernet Switch CapabilityRegister 4 */
  2204. +// XRX200_ETHSW_CAP_4_PPPOE, /* PPPoE table size */
  2205. +// XRX200_ETHSW_CAP_4_VLAN, /* Active VLAN table size */
  2206. +// XRX200_ETHSW_CAP_5, /* Ethernet Switch CapabilityRegister 5 */
  2207. +// XRX200_ETHSW_CAP_5_IPPLEN, /* IP packet length table size */
  2208. +// XRX200_ETHSW_CAP_5_PROT, /* Protocol table size */
  2209. +// XRX200_ETHSW_CAP_6, /* Ethernet Switch CapabilityRegister 6 */
  2210. +// XRX200_ETHSW_CAP_6_MACDASA, /* MAC DA/SA table size */
  2211. +// XRX200_ETHSW_CAP_6_APPL, /* Application table size */
  2212. +// XRX200_ETHSW_CAP_7, /* Ethernet Switch CapabilityRegister 7 */
  2213. +// XRX200_ETHSW_CAP_7_IPDASAM, /* IP DA/SA MSB table size */
  2214. +// XRX200_ETHSW_CAP_7_IPDASAL, /* IP DA/SA LSB table size */
  2215. +// XRX200_ETHSW_CAP_8, /* Ethernet Switch CapabilityRegister 8 */
  2216. +// XRX200_ETHSW_CAP_8_MCAST, /* Multicast table size */
  2217. +// XRX200_ETHSW_CAP_9, /* Ethernet Switch CapabilityRegister 9 */
  2218. +// XRX200_ETHSW_CAP_9_FLAGG, /* Flow Aggregation table size */
  2219. +// XRX200_ETHSW_CAP_10, /* Ethernet Switch CapabilityRegister 10 */
  2220. +// XRX200_ETHSW_CAP_10_MACBT, /* MAC bridging table size */
  2221. +// XRX200_ETHSW_CAP_11, /* Ethernet Switch CapabilityRegister 11 */
  2222. +// XRX200_ETHSW_CAP_11_BSIZEL, /* Packet buffer size (lower part, in byte) */
  2223. +// XRX200_ETHSW_CAP_12, /* Ethernet Switch CapabilityRegister 12 */
  2224. +// XRX200_ETHSW_CAP_12_BSIZEH, /* Packet buffer size (higher part, in byte) */
  2225. +// XRX200_ETHSW_VERSION_REV, /* Ethernet Switch VersionRegister */
  2226. +// XRX200_ETHSW_VERSION_MOD_ID, /* Module Identification */
  2227. +// XRX200_ETHSW_VERSION_REV_ID, /* Hardware Revision Identification */
  2228. +// XRX200_ETHSW_IER, /* Interrupt Enable Register */
  2229. +// XRX200_ETHSW_IER_FDMAIE, /* Fetch DMA Interrupt Enable */
  2230. +// XRX200_ETHSW_IER_SDMAIE, /* Store DMA Interrupt Enable */
  2231. +// XRX200_ETHSW_IER_MACIE, /* Ethernet MAC Interrupt Enable */
  2232. +// XRX200_ETHSW_IER_PCEIE, /* Parser and Classification Engine Interrupt Enable */
  2233. +// XRX200_ETHSW_IER_BMIE, /* Buffer Manager Interrupt Enable */
  2234. +// XRX200_ETHSW_ISR, /* Interrupt Status Register */
  2235. +// XRX200_ETHSW_ISR_FDMAINT, /* Fetch DMA Interrupt */
  2236. +// XRX200_ETHSW_ISR_SDMAINT, /* Store DMA Interrupt */
  2237. +// XRX200_ETHSW_ISR_MACINT, /* Ethernet MAC Interrupt */
  2238. +// XRX200_ETHSW_ISR_PCEINT, /* Parser and Classification Engine Interrupt */
  2239. +// XRX200_ETHSW_ISR_BMINT, /* Buffer Manager Interrupt */
  2240. +// XRX200_ETHSW_SPARE_0, /* Ethernet Switch SpareCells 0 */
  2241. +// XRX200_ETHSW_SPARE_0_SPARE, /* SPARE0 */
  2242. +// XRX200_ETHSW_SPARE_1, /* Ethernet Switch SpareCells 1 */
  2243. +// XRX200_ETHSW_SPARE_1_SPARE, /* SPARE1 */
  2244. +// XRX200_ETHSW_SPARE_2, /* Ethernet Switch SpareCells 2 */
  2245. +// XRX200_ETHSW_SPARE_2_SPARE, /* SPARE2 */
  2246. +// XRX200_ETHSW_SPARE_3, /* Ethernet Switch SpareCells 3 */
  2247. +// XRX200_ETHSW_SPARE_3_SPARE, /* SPARE3 */
  2248. +// XRX200_ETHSW_SPARE_4, /* Ethernet Switch SpareCells 4 */
  2249. +// XRX200_ETHSW_SPARE_4_SPARE, /* SPARE4 */
  2250. +// XRX200_ETHSW_SPARE_5, /* Ethernet Switch SpareCells 5 */
  2251. +// XRX200_ETHSW_SPARE_5_SPARE, /* SPARE5 */
  2252. +// XRX200_ETHSW_SPARE_6, /* Ethernet Switch SpareCells 6 */
  2253. +// XRX200_ETHSW_SPARE_6_SPARE, /* SPARE6 */
  2254. +// XRX200_ETHSW_SPARE_7, /* Ethernet Switch SpareCells 7 */
  2255. +// XRX200_ETHSW_SPARE_7_SPARE, /* SPARE7 */
  2256. +// XRX200_ETHSW_SPARE_8, /* Ethernet Switch SpareCells 8 */
  2257. +// XRX200_ETHSW_SPARE_8_SPARE, /* SPARE8 */
  2258. +// XRX200_ETHSW_SPARE_9, /* Ethernet Switch SpareCells 9 */
  2259. +// XRX200_ETHSW_SPARE_9_SPARE, /* SPARE9 */
  2260. +// XRX200_ETHSW_SPARE_10, /* Ethernet Switch SpareCells 10 */
  2261. +// XRX200_ETHSW_SPARE_10_SPARE, /* SPARE10 */
  2262. +// XRX200_ETHSW_SPARE_11, /* Ethernet Switch SpareCells 11 */
  2263. +// XRX200_ETHSW_SPARE_11_SPARE, /* SPARE11 */
  2264. +// XRX200_ETHSW_SPARE_12, /* Ethernet Switch SpareCells 12 */
  2265. +// XRX200_ETHSW_SPARE_12_SPARE, /* SPARE12 */
  2266. +// XRX200_ETHSW_SPARE_13, /* Ethernet Switch SpareCells 13 */
  2267. +// XRX200_ETHSW_SPARE_13_SPARE, /* SPARE13 */
  2268. +// XRX200_ETHSW_SPARE_14, /* Ethernet Switch SpareCells 14 */
  2269. +// XRX200_ETHSW_SPARE_14_SPARE, /* SPARE14 */
  2270. +// XRX200_ETHSW_SPARE_15, /* Ethernet Switch SpareCells 15 */
  2271. +// XRX200_ETHSW_SPARE_15_SPARE, /* SPARE15 */
  2272. +// XRX200_BM_RAM_VAL_3, /* RAM Value Register 3 */
  2273. +// XRX200_BM_RAM_VAL_3_VAL3, /* Data value [15:0] */
  2274. +// XRX200_BM_RAM_VAL_2, /* RAM Value Register 2 */
  2275. +// XRX200_BM_RAM_VAL_2_VAL2, /* Data value [15:0] */
  2276. +// XRX200_BM_RAM_VAL_1, /* RAM Value Register 1 */
  2277. +// XRX200_BM_RAM_VAL_1_VAL1, /* Data value [15:0] */
  2278. +// XRX200_BM_RAM_VAL_0, /* RAM Value Register 0 */
  2279. +// XRX200_BM_RAM_VAL_0_VAL0, /* Data value [15:0] */
  2280. +// XRX200_BM_RAM_ADDR, /* RAM Address Register */
  2281. +// XRX200_BM_RAM_ADDR_ADDR, /* RAM Address */
  2282. +// XRX200_BM_RAM_CTRL, /* RAM Access Control Register */
  2283. +// XRX200_BM_RAM_CTRL_BAS, /* Access Busy/Access Start */
  2284. +// XRX200_BM_RAM_CTRL_OPMOD, /* Lookup Table Access Operation Mode */
  2285. +// XRX200_BM_RAM_CTRL_ADDR, /* Address for RAM selection */
  2286. +// XRX200_BM_FSQM_GCTRL, /* Free Segment Queue ManagerGlobal Control Register */
  2287. +// XRX200_BM_FSQM_GCTRL_SEGNUM, /* Maximum Segment Number */
  2288. +// XRX200_BM_CONS_SEG, /* Number of Consumed SegmentsRegister */
  2289. +// XRX200_BM_CONS_SEG_FSEG, /* Number of Consumed Segments */
  2290. +// XRX200_BM_CONS_PKT, /* Number of Consumed PacketPointers Register */
  2291. +// XRX200_BM_CONS_PKT_FQP, /* Number of Consumed Packet Pointers */
  2292. +// XRX200_BM_GCTRL_F, /* Buffer Manager Global ControlRegister 0 */
  2293. +// XRX200_BM_GCTRL_BM_STA, /* Buffer Manager Initialization Status Bit */
  2294. +// XRX200_BM_GCTRL_SAT, /* RMON Counter Update Mode */
  2295. +// XRX200_BM_GCTRL_FR_RBC, /* Freeze RMON RX Bad Byte 64 Bit Counter */
  2296. +// XRX200_BM_GCTRL_FR_RGC, /* Freeze RMON RX Good Byte 64 Bit Counter */
  2297. +// XRX200_BM_GCTRL_FR_TGC, /* Freeze RMON TX Good Byte 64 Bit Counter */
  2298. +// XRX200_BM_GCTRL_I_FIN, /* RAM initialization finished */
  2299. +// XRX200_BM_GCTRL_CX_INI, /* PQM Context RAM initialization */
  2300. +// XRX200_BM_GCTRL_FP_INI, /* FPQM RAM initialization */
  2301. +// XRX200_BM_GCTRL_FS_INI, /* FSQM RAM initialization */
  2302. +// XRX200_BM_GCTRL_R_SRES, /* Software Reset for RMON */
  2303. +// XRX200_BM_GCTRL_S_SRES, /* Software Reset for Scheduler */
  2304. +// XRX200_BM_GCTRL_A_SRES, /* Software Reset for AVG */
  2305. +// XRX200_BM_GCTRL_P_SRES, /* Software Reset for PQM */
  2306. +// XRX200_BM_GCTRL_F_SRES, /* Software Reset for FSQM */
  2307. +// XRX200_BM_QUEUE_GCTRL, /* Queue Manager GlobalControl Register 0 */
  2308. + XRX200_BM_QUEUE_GCTRL_GL_MOD, /* WRED Mode Signal */
  2309. +// XRX200_BM_QUEUE_GCTRL_AQUI, /* Average Queue Update Interval */
  2310. +// XRX200_BM_QUEUE_GCTRL_AQWF, /* Average Queue Weight Factor */
  2311. +// XRX200_BM_QUEUE_GCTRL_QAVGEN, /* Queue Average Calculation Enable */
  2312. +// XRX200_BM_QUEUE_GCTRL_DPROB, /* Drop Probability Profile */
  2313. +// XRX200_BM_WRED_RTH_0, /* WRED Red Threshold Register0 */
  2314. +// XRX200_BM_WRED_RTH_0_MINTH, /* Minimum Threshold */
  2315. +// XRX200_BM_WRED_RTH_1, /* WRED Red Threshold Register1 */
  2316. +// XRX200_BM_WRED_RTH_1_MAXTH, /* Maximum Threshold */
  2317. +// XRX200_BM_WRED_YTH_0, /* WRED Yellow ThresholdRegister 0 */
  2318. +// XRX200_BM_WRED_YTH_0_MINTH, /* Minimum Threshold */
  2319. +// XRX200_BM_WRED_YTH_1, /* WRED Yellow ThresholdRegister 1 */
  2320. +// XRX200_BM_WRED_YTH_1_MAXTH, /* Maximum Threshold */
  2321. +// XRX200_BM_WRED_GTH_0, /* WRED Green ThresholdRegister 0 */
  2322. +// XRX200_BM_WRED_GTH_0_MINTH, /* Minimum Threshold */
  2323. +// XRX200_BM_WRED_GTH_1, /* WRED Green ThresholdRegister 1 */
  2324. +// XRX200_BM_WRED_GTH_1_MAXTH, /* Maximum Threshold */
  2325. +// XRX200_BM_DROP_GTH_0_THR, /* Drop Threshold ConfigurationRegister 0 */
  2326. +// XRX200_BM_DROP_GTH_0_THR_FQ, /* Threshold for frames marked red */
  2327. +// XRX200_BM_DROP_GTH_1_THY, /* Drop Threshold ConfigurationRegister 1 */
  2328. +// XRX200_BM_DROP_GTH_1_THY_FQ, /* Threshold for frames marked yellow */
  2329. +// XRX200_BM_DROP_GTH_2_THG, /* Drop Threshold ConfigurationRegister 2 */
  2330. +// XRX200_BM_DROP_GTH_2_THG_FQ, /* Threshold for frames marked green */
  2331. +// XRX200_BM_IER, /* Buffer Manager Global InterruptEnable Register */
  2332. +// XRX200_BM_IER_CNT4, /* Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */
  2333. +// XRX200_BM_IER_CNT3, /* Counter Group 3 (RMON-PQM) Interrupt Enable */
  2334. +// XRX200_BM_IER_CNT2, /* Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */
  2335. +// XRX200_BM_IER_CNT1, /* Counter Group 1 (RMON-QFETCH) Interrupt Enable */
  2336. +// XRX200_BM_IER_CNT0, /* Counter Group 0 (RMON-QSTOR) Interrupt Enable */
  2337. +// XRX200_BM_IER_DEQ, /* PQM dequeue Interrupt Enable */
  2338. +// XRX200_BM_IER_ENQ, /* PQM Enqueue Interrupt Enable */
  2339. +// XRX200_BM_IER_FSQM, /* Buffer Empty Interrupt Enable */
  2340. +// XRX200_BM_ISR, /* Buffer Manager Global InterruptStatus Register */
  2341. +// XRX200_BM_ISR_CNT4, /* Counter Group 4 Interrupt */
  2342. +// XRX200_BM_ISR_CNT3, /* Counter Group 3 Interrupt */
  2343. +// XRX200_BM_ISR_CNT2, /* Counter Group 2 Interrupt */
  2344. +// XRX200_BM_ISR_CNT1, /* Counter Group 1 Interrupt */
  2345. +// XRX200_BM_ISR_CNT0, /* Counter Group 0 Interrupt */
  2346. +// XRX200_BM_ISR_DEQ, /* PQM dequeue Interrupt Enable */
  2347. +// XRX200_BM_ISR_ENQ, /* PQM Enqueue Interrupt */
  2348. +// XRX200_BM_ISR_FSQM, /* Buffer Empty Interrupt */
  2349. +// XRX200_BM_CISEL, /* Buffer Manager RMON CounterInterrupt Select Register */
  2350. +// XRX200_BM_CISEL_PORT, /* Port Number */
  2351. +// XRX200_BM_DEBUG_CTRL_DBG, /* Debug Control Register */
  2352. +// XRX200_BM_DEBUG_CTRL_DBG_SEL, /* Select Signal for Debug Multiplexer */
  2353. +// XRX200_BM_DEBUG_VAL_DBG, /* Debug Value Register */
  2354. +// XRX200_BM_DEBUG_VAL_DBG_DAT, /* Debug Data Value */
  2355. +// XRX200_BM_PCFG, /* Buffer Manager PortConfiguration Register */
  2356. +// XRX200_BM_PCFG_CNTEN, /* RMON Counter Enable */
  2357. +// XRX200_BM_RMON_CTRL_RAM1, /* Buffer ManagerRMON Control Register */
  2358. +// XRX200_BM_RMON_CTRL_RAM2_RES, /* Software Reset for RMON RAM2 */
  2359. +// XRX200_BM_RMON_CTRL_RAM1_RES, /* Software Reset for RMON RAM1 */
  2360. +// XRX200_PQM_DP, /* Packet Queue ManagerDrop Probability Register */
  2361. +// XRX200_PQM_DP_DPROB, /* Drop Probability Profile */
  2362. +// XRX200_PQM_RS, /* Packet Queue ManagerRate Shaper Assignment Register */
  2363. +// XRX200_PQM_RS_EN2, /* Rate Shaper 2 Enable */
  2364. +// XRX200_PQM_RS_RS2, /* Rate Shaper 2 */
  2365. +// XRX200_PQM_RS_EN1, /* Rate Shaper 1 Enable */
  2366. +// XRX200_PQM_RS_RS1, /* Rate Shaper 1 */
  2367. +// XRX200_RS_CTRL, /* Rate Shaper ControlRegister */
  2368. +// XRX200_RS_CTRL_RSEN, /* Rate Shaper Enable */
  2369. +// XRX200_RS_CBS, /* Rate Shaper CommittedBurst Size Register */
  2370. +// XRX200_RS_CBS_CBS, /* Committed Burst Size */
  2371. +// XRX200_RS_IBS, /* Rate Shaper InstantaneousBurst Size Register */
  2372. +// XRX200_RS_IBS_IBS, /* Instantaneous Burst Size */
  2373. +// XRX200_RS_CIR_EXP, /* Rate Shaper RateExponent Register */
  2374. +// XRX200_RS_CIR_EXP_EXP, /* Exponent */
  2375. +// XRX200_RS_CIR_MANT, /* Rate Shaper RateMantissa Register */
  2376. +// XRX200_RS_CIR_MANT_MANT, /* Mantissa */
  2377. + XRX200_PCE_TBL_KEY_7, /* Table Key Data 7 */
  2378. +// XRX200_PCE_TBL_KEY_7_KEY7, /* Key Value[15:0] */
  2379. + XRX200_PCE_TBL_KEY_6, /* Table Key Data 6 */
  2380. +// XRX200_PCE_TBL_KEY_6_KEY6, /* Key Value[15:0] */
  2381. + XRX200_PCE_TBL_KEY_5, /* Table Key Data 5 */
  2382. +// XRX200_PCE_TBL_KEY_5_KEY5, /* Key Value[15:0] */
  2383. + XRX200_PCE_TBL_KEY_4, /* Table Key Data 4 */
  2384. +// XRX200_PCE_TBL_KEY_4_KEY4, /* Key Value[15:0] */
  2385. + XRX200_PCE_TBL_KEY_3, /* Table Key Data 3 */
  2386. +// XRX200_PCE_TBL_KEY_3_KEY3, /* Key Value[15:0] */
  2387. + XRX200_PCE_TBL_KEY_2, /* Table Key Data 2 */
  2388. +// XRX200_PCE_TBL_KEY_2_KEY2, /* Key Value[15:0] */
  2389. + XRX200_PCE_TBL_KEY_1, /* Table Key Data 1 */
  2390. +// XRX200_PCE_TBL_KEY_1_KEY1, /* Key Value[31:16] */
  2391. + XRX200_PCE_TBL_KEY_0, /* Table Key Data 0 */
  2392. +// XRX200_PCE_TBL_KEY_0_KEY0, /* Key Value[15:0] */
  2393. + XRX200_PCE_TBL_MASK_0, /* Table Mask Write Register0 */
  2394. +// XRX200_PCE_TBL_MASK_0_MASK0, /* Mask Pattern [15:0] */
  2395. + XRX200_PCE_TBL_VAL_4, /* Table Value Register4 */
  2396. +// XRX200_PCE_TBL_VAL_4_VAL4, /* Data value [15:0] */
  2397. + XRX200_PCE_TBL_VAL_3, /* Table Value Register3 */
  2398. +// XRX200_PCE_TBL_VAL_3_VAL3, /* Data value [15:0] */
  2399. + XRX200_PCE_TBL_VAL_2, /* Table Value Register2 */
  2400. +// XRX200_PCE_TBL_VAL_2_VAL2, /* Data value [15:0] */
  2401. + XRX200_PCE_TBL_VAL_1, /* Table Value Register1 */
  2402. +// XRX200_PCE_TBL_VAL_1_VAL1, /* Data value [15:0] */
  2403. + XRX200_PCE_TBL_VAL_0, /* Table Value Register0 */
  2404. +// XRX200_PCE_TBL_VAL_0_VAL0, /* Data value [15:0] */
  2405. +// XRX200_PCE_TBL_ADDR, /* Table Entry AddressRegister */
  2406. + XRX200_PCE_TBL_ADDR_ADDR, /* Table Address */
  2407. +// XRX200_PCE_TBL_CTRL, /* Table Access ControlRegister */
  2408. + XRX200_PCE_TBL_CTRL_BAS, /* Access Busy/Access Start */
  2409. + XRX200_PCE_TBL_CTRL_TYPE, /* Lookup Entry Type */
  2410. + XRX200_PCE_TBL_CTRL_VLD, /* Lookup Entry Valid */
  2411. + XRX200_PCE_TBL_CTRL_GMAP, /* Group Map */
  2412. + XRX200_PCE_TBL_CTRL_OPMOD, /* Lookup Table Access Operation Mode */
  2413. + XRX200_PCE_TBL_CTRL_ADDR, /* Lookup Table Address */
  2414. +// XRX200_PCE_TBL_STAT, /* Table General StatusRegister */
  2415. +// XRX200_PCE_TBL_STAT_TBUSY, /* Table Access Busy */
  2416. +// XRX200_PCE_TBL_STAT_TEMPT, /* Table Empty */
  2417. +// XRX200_PCE_TBL_STAT_TFUL, /* Table Full */
  2418. +// XRX200_PCE_AGE_0, /* Aging Counter ConfigurationRegister 0 */
  2419. +// XRX200_PCE_AGE_0_EXP, /* Aging Counter Exponent Value */
  2420. +// XRX200_PCE_AGE_1, /* Aging Counter ConfigurationRegister 1 */
  2421. +// XRX200_PCE_AGE_1_MANT, /* Aging Counter Mantissa Value */
  2422. +// XRX200_PCE_PMAP_1, /* Port Map Register 1 */
  2423. +// XRX200_PCE_PMAP_1_MPMAP, /* Monitoring Port Map */
  2424. +// XRX200_PCE_PMAP_2, /* Port Map Register 2 */
  2425. +// XRX200_PCE_PMAP_2_DMCPMAP, /* Default Multicast Port Map */
  2426. +// XRX200_PCE_PMAP_3, /* Port Map Register 3 */
  2427. +// XRX200_PCE_PMAP_3_UUCMAP, /* Default Unknown Unicast Port Map */
  2428. +// XRX200_PCE_GCTRL_0, /* PCE Global Control Register0 */
  2429. +// XRX200_PCE_GCTRL_0_IGMP, /* IGMP Mode Selection */
  2430. + XRX200_PCE_GCTRL_0_VLAN, /* VLAN-aware Switching */
  2431. +// XRX200_PCE_GCTRL_0_NOPM, /* No Port Map Forwarding */
  2432. +// XRX200_PCE_GCTRL_0_SCONUC, /* Unknown Unicast Storm Control */
  2433. +// XRX200_PCE_GCTRL_0_SCONMC, /* Multicast Storm Control */
  2434. +// XRX200_PCE_GCTRL_0_SCONBC, /* Broadcast Storm Control */
  2435. +// XRX200_PCE_GCTRL_0_SCONMOD, /* Storm Control Mode */
  2436. +// XRX200_PCE_GCTRL_0_SCONMET, /* Storm Control Metering Instance */
  2437. +// XRX200_PCE_GCTRL_0_MC_VALID, /* Access Request */
  2438. +// XRX200_PCE_GCTRL_0_PLCKMOD, /* Port Lock Mode */
  2439. +// XRX200_PCE_GCTRL_0_PLIMMOD, /* MAC Address Learning Limitation Mode */
  2440. +// XRX200_PCE_GCTRL_0_MTFL, /* MAC Table Flushing */
  2441. +// XRX200_PCE_GCTRL_1, /* PCE Global Control Register1 */
  2442. +// XRX200_PCE_GCTRL_1_PCE_DIS, /* PCE Disable after currently processed packet */
  2443. +// XRX200_PCE_GCTRL_1_LRNMOD, /* MAC Address Learning Mode */
  2444. +// XRX200_PCE_TCM_GLOB_CTRL, /* Three-color MarkerGlobal Control Register */
  2445. +// XRX200_PCE_TCM_GLOB_CTRL_DPRED, /* Re-marking Drop Precedence Red Encoding */
  2446. +// XRX200_PCE_TCM_GLOB_CTRL_DPYEL, /* Re-marking Drop Precedence Yellow Encoding */
  2447. +// XRX200_PCE_TCM_GLOB_CTRL_DPGRN, /* Re-marking Drop Precedence Green Encoding */
  2448. +// XRX200_PCE_IGMP_CTRL, /* IGMP Control Register */
  2449. +// XRX200_PCE_IGMP_CTRL_FAGEEN, /* Force Aging of Table Entries Enable */
  2450. +// XRX200_PCE_IGMP_CTRL_FLEAVE, /* Fast Leave Enable */
  2451. +// XRX200_PCE_IGMP_CTRL_DMRTEN, /* Default Maximum Response Time Enable */
  2452. +// XRX200_PCE_IGMP_CTRL_JASUP, /* Join Aggregation Suppression Enable */
  2453. +// XRX200_PCE_IGMP_CTRL_REPSUP, /* Report Suppression Enable */
  2454. +// XRX200_PCE_IGMP_CTRL_SRPEN, /* Snooping of Router Port Enable */
  2455. +// XRX200_PCE_IGMP_CTRL_ROB, /* Robustness Variable */
  2456. +// XRX200_PCE_IGMP_CTRL_DMRT, /* IGMP Default Maximum Response Time */
  2457. +// XRX200_PCE_IGMP_DRPM, /* IGMP Default RouterPort Map Register */
  2458. +// XRX200_PCE_IGMP_DRPM_DRPM, /* IGMP Default Router Port Map */
  2459. +// XRX200_PCE_IGMP_AGE_0, /* IGMP Aging Register0 */
  2460. +// XRX200_PCE_IGMP_AGE_0_MANT, /* IGMP Group Aging Time Mantissa */
  2461. +// XRX200_PCE_IGMP_AGE_0_EXP, /* IGMP Group Aging Time Exponent */
  2462. +// XRX200_PCE_IGMP_AGE_1, /* IGMP Aging Register1 */
  2463. +// XRX200_PCE_IGMP_AGE_1_MANT, /* IGMP Router Port Aging Time Mantissa */
  2464. +// XRX200_PCE_IGMP_STAT, /* IGMP Status Register */
  2465. +// XRX200_PCE_IGMP_STAT_IGPM, /* IGMP Port Map */
  2466. +// XRX200_WOL_GLB_CTRL, /* Wake-on-LAN ControlRegister */
  2467. +// XRX200_WOL_GLB_CTRL_PASSEN, /* WoL Password Enable */
  2468. +// XRX200_WOL_DA_0, /* Wake-on-LAN DestinationAddress Register 0 */
  2469. +// XRX200_WOL_DA_0_DA0, /* WoL Destination Address [15:0] */
  2470. +// XRX200_WOL_DA_1, /* Wake-on-LAN DestinationAddress Register 1 */
  2471. +// XRX200_WOL_DA_1_DA1, /* WoL Destination Address [31:16] */
  2472. +// XRX200_WOL_DA_2, /* Wake-on-LAN DestinationAddress Register 2 */
  2473. +// XRX200_WOL_DA_2_DA2, /* WoL Destination Address [47:32] */
  2474. +// XRX200_WOL_PW_0, /* Wake-on-LAN Password Register0 */
  2475. +// XRX200_WOL_PW_0_PW0, /* WoL Password [15:0] */
  2476. +// XRX200_WOL_PW_1, /* Wake-on-LAN Password Register1 */
  2477. +// XRX200_WOL_PW_1_PW1, /* WoL Password [31:16] */
  2478. +// XRX200_WOL_PW_2, /* Wake-on-LAN Password Register2 */
  2479. +// XRX200_WOL_PW_2_PW2, /* WoL Password [47:32] */
  2480. +// XRX200_PCE_IER_0_PINT, /* Parser and ClassificationEngine Global Interrupt Enable Register 0 */
  2481. +// XRX200_PCE_IER_0_PINT_15, /* Port Interrupt Enable */
  2482. +// XRX200_PCE_IER_0_PINT_14, /* Port Interrupt Enable */
  2483. +// XRX200_PCE_IER_0_PINT_13, /* Port Interrupt Enable */
  2484. +// XRX200_PCE_IER_0_PINT_12, /* Port Interrupt Enable */
  2485. +// XRX200_PCE_IER_0_PINT_11, /* Port Interrupt Enable */
  2486. +// XRX200_PCE_IER_0_PINT_10, /* Port Interrupt Enable */
  2487. +// XRX200_PCE_IER_0_PINT_9, /* Port Interrupt Enable */
  2488. +// XRX200_PCE_IER_0_PINT_8, /* Port Interrupt Enable */
  2489. +// XRX200_PCE_IER_0_PINT_7, /* Port Interrupt Enable */
  2490. +// XRX200_PCE_IER_0_PINT_6, /* Port Interrupt Enable */
  2491. +// XRX200_PCE_IER_0_PINT_5, /* Port Interrupt Enable */
  2492. +// XRX200_PCE_IER_0_PINT_4, /* Port Interrupt Enable */
  2493. +// XRX200_PCE_IER_0_PINT_3, /* Port Interrupt Enable */
  2494. +// XRX200_PCE_IER_0_PINT_2, /* Port Interrupt Enable */
  2495. +// XRX200_PCE_IER_0_PINT_1, /* Port Interrupt Enable */
  2496. +// XRX200_PCE_IER_0_PINT_0, /* Port Interrupt Enable */
  2497. +// XRX200_PCE_IER_1, /* Parser and ClassificationEngine Global Interrupt Enable Register 1 */
  2498. +// XRX200_PCE_IER_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched Interrupt Enable */
  2499. +// XRX200_PCE_IER_1_CPH2, /* Classification Phase 2 Ready Interrupt Enable */
  2500. +// XRX200_PCE_IER_1_CPH1, /* Classification Phase 1 Ready Interrupt Enable */
  2501. +// XRX200_PCE_IER_1_CPH0, /* Classification Phase 0 Ready Interrupt Enable */
  2502. +// XRX200_PCE_IER_1_PRDY, /* Parser Ready Interrupt Enable */
  2503. +// XRX200_PCE_IER_1_IGTF, /* IGMP Table Full Interrupt Enable */
  2504. +// XRX200_PCE_IER_1_MTF, /* MAC Table Full Interrupt Enable */
  2505. +// XRX200_PCE_ISR_0_PINT, /* Parser and ClassificationEngine Global Interrupt Status Register 0 */
  2506. +// XRX200_PCE_ISR_0_PINT_15, /* Port Interrupt */
  2507. +// XRX200_PCE_ISR_0_PINT_14, /* Port Interrupt */
  2508. +// XRX200_PCE_ISR_0_PINT_13, /* Port Interrupt */
  2509. +// XRX200_PCE_ISR_0_PINT_12, /* Port Interrupt */
  2510. +// XRX200_PCE_ISR_0_PINT_11, /* Port Interrupt */
  2511. +// XRX200_PCE_ISR_0_PINT_10, /* Port Interrupt */
  2512. +// XRX200_PCE_ISR_0_PINT_9, /* Port Interrupt */
  2513. +// XRX200_PCE_ISR_0_PINT_8, /* Port Interrupt */
  2514. +// XRX200_PCE_ISR_0_PINT_7, /* Port Interrupt */
  2515. +// XRX200_PCE_ISR_0_PINT_6, /* Port Interrupt */
  2516. +// XRX200_PCE_ISR_0_PINT_5, /* Port Interrupt */
  2517. +// XRX200_PCE_ISR_0_PINT_4, /* Port Interrupt */
  2518. +// XRX200_PCE_ISR_0_PINT_3, /* Port Interrupt */
  2519. +// XRX200_PCE_ISR_0_PINT_2, /* Port Interrupt */
  2520. +// XRX200_PCE_ISR_0_PINT_1, /* Port Interrupt */
  2521. +// XRX200_PCE_ISR_0_PINT_0, /* Port Interrupt */
  2522. +// XRX200_PCE_ISR_1, /* Parser and ClassificationEngine Global Interrupt Status Register 1 */
  2523. +// XRX200_PCE_ISR_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched */
  2524. +// XRX200_PCE_ISR_1_CPH2, /* Classification Phase 2 Ready Interrupt */
  2525. +// XRX200_PCE_ISR_1_CPH1, /* Classification Phase 1 Ready Interrupt */
  2526. +// XRX200_PCE_ISR_1_CPH0, /* Classification Phase 0 Ready Interrupt */
  2527. +// XRX200_PCE_ISR_1_PRDY, /* Parser Ready Interrupt */
  2528. +// XRX200_PCE_ISR_1_IGTF, /* IGMP Table Full Interrupt */
  2529. +// XRX200_PCE_ISR_1_MTF, /* MAC Table Full Interrupt */
  2530. +// XRX200_PARSER_STAT_FIFO, /* Parser Status Register */
  2531. +// XRX200_PARSER_STAT_FSM_DAT_CNT, /* Parser FSM Data Counter */
  2532. +// XRX200_PARSER_STAT_FSM_STATE, /* Parser FSM State */
  2533. +// XRX200_PARSER_STAT_PKT_ERR, /* Packet error detected */
  2534. +// XRX200_PARSER_STAT_FSM_FIN, /* Parser FSM finished */
  2535. +// XRX200_PARSER_STAT_FSM_START, /* Parser FSM start */
  2536. +// XRX200_PARSER_STAT_FIFO_RDY, /* Parser FIFO ready for read. */
  2537. +// XRX200_PARSER_STAT_FIFO_FULL, /* Parser */
  2538. +// XRX200_PCE_PCTRL_0, /* PCE Port ControlRegister 0 */
  2539. +// XRX200_PCE_PCTRL_0_MCST, /* Multicast Forwarding Mode Selection */
  2540. +// XRX200_PCE_PCTRL_0_EGSTEN, /* Table-based Egress Special Tag Enable */
  2541. +// XRX200_PCE_PCTRL_0_IGSTEN, /* Ingress Special Tag Enable */
  2542. +// XRX200_PCE_PCTRL_0_PCPEN, /* PCP Remarking Mode */
  2543. +// XRX200_PCE_PCTRL_0_CLPEN, /* Class Remarking Mode */
  2544. +// XRX200_PCE_PCTRL_0_DPEN, /* Drop Precedence Remarking Mode */
  2545. +// XRX200_PCE_PCTRL_0_CMOD, /* Three-color Marker Color Mode */
  2546. +// XRX200_PCE_PCTRL_0_VREP, /* VLAN Replacement Mode */
  2547. + XRX200_PCE_PCTRL_0_TVM, /* Transparent VLAN Mode */
  2548. +// XRX200_PCE_PCTRL_0_PLOCK, /* Port Locking Enable */
  2549. +// XRX200_PCE_PCTRL_0_AGEDIS, /* Aging Disable */
  2550. +// XRX200_PCE_PCTRL_0_PSTATE, /* Port State */
  2551. +// XRX200_PCE_PCTRL_1, /* PCE Port ControlRegister 1 */
  2552. +// XRX200_PCE_PCTRL_1_LRNLIM, /* MAC Address Learning Limit */
  2553. +// XRX200_PCE_PCTRL_2, /* PCE Port ControlRegister 2 */
  2554. +// XRX200_PCE_PCTRL_2_DSCPMOD, /* DSCP Mode Selection */
  2555. +// XRX200_PCE_PCTRL_2_DSCP, /* Enable DSCP to select the Class of Service */
  2556. +// XRX200_PCE_PCTRL_2_PCP, /* Enable VLAN PCP to select the Class of Service */
  2557. +// XRX200_PCE_PCTRL_2_PCLASS, /* Port-based Traffic Class */
  2558. +// XRX200_PCE_PCTRL_3_VIO, /* PCE Port ControlRegister 3 */
  2559. +// XRX200_PCE_PCTRL_3_EDIR, /* Egress Redirection Mode */
  2560. +// XRX200_PCE_PCTRL_3_RXDMIR, /* Receive Mirroring Enable for dropped frames */
  2561. +// XRX200_PCE_PCTRL_3_RXVMIR, /* Receive Mirroring Enable for valid frames */
  2562. +// XRX200_PCE_PCTRL_3_TXMIR, /* Transmit Mirroring Enable */
  2563. +// XRX200_PCE_PCTRL_3_VIO_7, /* Violation Type 7 Mirroring Enable */
  2564. +// XRX200_PCE_PCTRL_3_VIO_6, /* Violation Type 6 Mirroring Enable */
  2565. +// XRX200_PCE_PCTRL_3_VIO_5, /* Violation Type 5 Mirroring Enable */
  2566. +// XRX200_PCE_PCTRL_3_VIO_4, /* Violation Type 4 Mirroring Enable */
  2567. +// XRX200_PCE_PCTRL_3_VIO_3, /* Violation Type 3 Mirroring Enable */
  2568. +// XRX200_PCE_PCTRL_3_VIO_2, /* Violation Type 2 Mirroring Enable */
  2569. +// XRX200_PCE_PCTRL_3_VIO_1, /* Violation Type 1 Mirroring Enable */
  2570. +// XRX200_PCE_PCTRL_3_VIO_0, /* Violation Type 0 Mirroring Enable */
  2571. +// XRX200_WOL_CTRL, /* Wake-on-LAN ControlRegister */
  2572. +// XRX200_WOL_CTRL_PORT, /* WoL Enable */
  2573. +// XRX200_PCE_VCTRL, /* PCE VLAN ControlRegister */
  2574. + XRX200_PCE_VCTRL_VSR, /* VLAN Security Rule */
  2575. + XRX200_PCE_VCTRL_VEMR, /* VLAN Egress Member Violation Rule */
  2576. + XRX200_PCE_VCTRL_VIMR, /* VLAN Ingress Member Violation Rule */
  2577. + XRX200_PCE_VCTRL_VINR, /* VLAN Ingress Tag Rule */
  2578. + XRX200_PCE_VCTRL_UVR, /* Unknown VLAN Rule */
  2579. +// XRX200_PCE_DEFPVID, /* PCE Default PortVID Register */
  2580. + XRX200_PCE_DEFPVID_PVID, /* Default Port VID Index */
  2581. +// XRX200_PCE_PSTAT, /* PCE Port StatusRegister */
  2582. +// XRX200_PCE_PSTAT_LRNCNT, /* Learning Count */
  2583. +// XRX200_PCE_PIER, /* Parser and ClassificationEngine Port Interrupt Enable Register */
  2584. +// XRX200_PCE_PIER_CLDRP, /* Classification Drop Interrupt Enable */
  2585. +// XRX200_PCE_PIER_PTDRP, /* Port Drop Interrupt Enable */
  2586. +// XRX200_PCE_PIER_VLAN, /* VLAN Violation Interrupt Enable */
  2587. +// XRX200_PCE_PIER_WOL, /* Wake-on-LAN Interrupt Enable */
  2588. +// XRX200_PCE_PIER_LOCK, /* Port Limit Alert Interrupt Enable */
  2589. +// XRX200_PCE_PIER_LIM, /* Port Lock Alert Interrupt Enable */
  2590. +// XRX200_PCE_PISR, /* Parser and ClassificationEngine Port Interrupt Status Register */
  2591. +// XRX200_PCE_PISR_CLDRP, /* Classification Drop Interrupt */
  2592. +// XRX200_PCE_PISR_PTDRP, /* Port Drop Interrupt */
  2593. +// XRX200_PCE_PISR_VLAN, /* VLAN Violation Interrupt */
  2594. +// XRX200_PCE_PISR_WOL, /* Wake-on-LAN Interrupt */
  2595. +// XRX200_PCE_PISR_LOCK, /* Port Lock Alert Interrupt */
  2596. +// XRX200_PCE_PISR_LIMIT, /* Port Limitation Alert Interrupt */
  2597. +// XRX200_PCE_TCM_CTRL, /* Three-colorMarker Control Register */
  2598. +// XRX200_PCE_TCM_CTRL_TCMEN, /* Three-color Marker metering instance enable */
  2599. +// XRX200_PCE_TCM_STAT, /* Three-colorMarker Status Register */
  2600. +// XRX200_PCE_TCM_STAT_AL1, /* Three-color Marker Alert 1 Status */
  2601. +// XRX200_PCE_TCM_STAT_AL0, /* Three-color Marker Alert 0 Status */
  2602. +// XRX200_PCE_TCM_CBS, /* Three-color MarkerCommitted Burst Size Register */
  2603. +// XRX200_PCE_TCM_CBS_CBS, /* Committed Burst Size */
  2604. +// XRX200_PCE_TCM_EBS, /* Three-color MarkerExcess Burst Size Register */
  2605. +// XRX200_PCE_TCM_EBS_EBS, /* Excess Burst Size */
  2606. +// XRX200_PCE_TCM_IBS, /* Three-color MarkerInstantaneous Burst Size Register */
  2607. +// XRX200_PCE_TCM_IBS_IBS, /* Instantaneous Burst Size */
  2608. +// XRX200_PCE_TCM_CIR_MANT, /* Three-colorMarker Constant Information Rate Mantissa Register */
  2609. +// XRX200_PCE_TCM_CIR_MANT_MANT, /* Rate Counter Mantissa */
  2610. +// XRX200_PCE_TCM_CIR_EXP, /* Three-colorMarker Constant Information Rate Exponent Register */
  2611. +// XRX200_PCE_TCM_CIR_EXP_EXP, /* Rate Counter Exponent */
  2612. +// XRX200_MAC_TEST, /* MAC Test Register */
  2613. +// XRX200_MAC_TEST_JTP, /* Jitter Test Pattern */
  2614. +// XRX200_MAC_PFAD_CFG, /* MAC Pause FrameSource Address Configuration Register */
  2615. +// XRX200_MAC_PFAD_CFG_SAMOD, /* Source Address Mode */
  2616. +// XRX200_MAC_PFSA_0, /* Pause Frame SourceAddress Part 0 */
  2617. +// XRX200_MAC_PFSA_0_PFAD, /* Pause Frame Source Address Part 0 */
  2618. +// XRX200_MAC_PFSA_1, /* Pause Frame SourceAddress Part 1 */
  2619. +// XRX200_MAC_PFSA_1_PFAD, /* Pause Frame Source Address Part 1 */
  2620. +// XRX200_MAC_PFSA_2, /* Pause Frame SourceAddress Part 2 */
  2621. +// XRX200_MAC_PFSA_2_PFAD, /* Pause Frame Source Address Part 2 */
  2622. +// XRX200_MAC_FLEN, /* MAC Frame Length Register */
  2623. +// XRX200_MAC_FLEN_LEN, /* Maximum Frame Length */
  2624. +// XRX200_MAC_VLAN_ETYPE_0, /* MAC VLAN EthertypeRegister 0 */
  2625. +// XRX200_MAC_VLAN_ETYPE_0_OUTER, /* Ethertype */
  2626. +// XRX200_MAC_VLAN_ETYPE_1, /* MAC VLAN EthertypeRegister 1 */
  2627. +// XRX200_MAC_VLAN_ETYPE_1_INNER, /* Ethertype */
  2628. +// XRX200_MAC_IER, /* MAC Interrupt EnableRegister */
  2629. +// XRX200_MAC_IER_MACIEN, /* MAC Interrupt Enable */
  2630. +// XRX200_MAC_ISR, /* MAC Interrupt StatusRegister */
  2631. +// XRX200_MAC_ISR_MACINT, /* MAC Interrupt */
  2632. +// XRX200_MAC_PSTAT, /* MAC Port Status Register */
  2633. +// XRX200_MAC_PSTAT_PACT, /* PHY Active Status */
  2634. + XRX200_MAC_PSTAT_GBIT, /* Gigabit Speed Status */
  2635. + XRX200_MAC_PSTAT_MBIT, /* Megabit Speed Status */
  2636. + XRX200_MAC_PSTAT_FDUP, /* Full Duplex Status */
  2637. +// XRX200_MAC_PSTAT_RXPAU, /* Receive Pause Status */
  2638. +// XRX200_MAC_PSTAT_TXPAU, /* Transmit Pause Status */
  2639. +// XRX200_MAC_PSTAT_RXPAUEN, /* Receive Pause Enable Status */
  2640. +// XRX200_MAC_PSTAT_TXPAUEN, /* Transmit Pause Enable Status */
  2641. + XRX200_MAC_PSTAT_LSTAT, /* Link Status */
  2642. +// XRX200_MAC_PSTAT_CRS, /* Carrier Sense Status */
  2643. +// XRX200_MAC_PSTAT_TXLPI, /* Transmit Low-power Idle Status */
  2644. +// XRX200_MAC_PSTAT_RXLPI, /* Receive Low-power Idle Status */
  2645. +// XRX200_MAC_PISR, /* MAC Interrupt Status Register */
  2646. +// XRX200_MAC_PISR_PACT, /* PHY Active Status */
  2647. +// XRX200_MAC_PISR_SPEED, /* Megabit Speed Status */
  2648. +// XRX200_MAC_PISR_FDUP, /* Full Duplex Status */
  2649. +// XRX200_MAC_PISR_RXPAUEN, /* Receive Pause Enable Status */
  2650. +// XRX200_MAC_PISR_TXPAUEN, /* Transmit Pause Enable Status */
  2651. +// XRX200_MAC_PISR_LPIOFF, /* Receive Low-power Idle Mode is left */
  2652. +// XRX200_MAC_PISR_LPION, /* Receive Low-power Idle Mode is entered */
  2653. +// XRX200_MAC_PISR_JAM, /* Jam Status Detected */
  2654. +// XRX200_MAC_PISR_TOOSHORT, /* Too Short Frame Error Detected */
  2655. +// XRX200_MAC_PISR_TOOLONG, /* Too Long Frame Error Detected */
  2656. +// XRX200_MAC_PISR_LENERR, /* Length Mismatch Error Detected */
  2657. +// XRX200_MAC_PISR_FCSERR, /* Frame Checksum Error Detected */
  2658. +// XRX200_MAC_PISR_TXPAUSE, /* Pause Frame Transmitted */
  2659. +// XRX200_MAC_PISR_RXPAUSE, /* Pause Frame Received */
  2660. +// XRX200_MAC_PIER, /* MAC Interrupt Enable Register */
  2661. +// XRX200_MAC_PIER_PACT, /* PHY Active Status */
  2662. +// XRX200_MAC_PIER_SPEED, /* Megabit Speed Status */
  2663. +// XRX200_MAC_PIER_FDUP, /* Full Duplex Status */
  2664. +// XRX200_MAC_PIER_RXPAUEN, /* Receive Pause Enable Status */
  2665. +// XRX200_MAC_PIER_TXPAUEN, /* Transmit Pause Enable Status */
  2666. +// XRX200_MAC_PIER_LPIOFF, /* Low-power Idle Off Interrupt Mask */
  2667. +// XRX200_MAC_PIER_LPION, /* Low-power Idle On Interrupt Mask */
  2668. +// XRX200_MAC_PIER_JAM, /* Jam Status Interrupt Mask */
  2669. +// XRX200_MAC_PIER_TOOSHORT, /* Too Short Frame Error Interrupt Mask */
  2670. +// XRX200_MAC_PIER_TOOLONG, /* Too Long Frame Error Interrupt Mask */
  2671. +// XRX200_MAC_PIER_LENERR, /* Length Mismatch Error Interrupt Mask */
  2672. +// XRX200_MAC_PIER_FCSERR, /* Frame Checksum Error Interrupt Mask */
  2673. +// XRX200_MAC_PIER_TXPAUSE, /* Transmit Pause Frame Interrupt Mask */
  2674. +// XRX200_MAC_PIER_RXPAUSE, /* Receive Pause Frame Interrupt Mask */
  2675. +// XRX200_MAC_CTRL_0, /* MAC Control Register0 */
  2676. +// XRX200_MAC_CTRL_0_LCOL, /* Late Collision Control */
  2677. +// XRX200_MAC_CTRL_0_BM, /* Burst Mode Control */
  2678. +// XRX200_MAC_CTRL_0_APADEN, /* Automatic VLAN Padding Enable */
  2679. +// XRX200_MAC_CTRL_0_VPAD2EN, /* Stacked VLAN Padding Enable */
  2680. +// XRX200_MAC_CTRL_0_VPADEN, /* VLAN Padding Enable */
  2681. +// XRX200_MAC_CTRL_0_PADEN, /* Padding Enable */
  2682. +// XRX200_MAC_CTRL_0_FCS, /* Transmit FCS Control */
  2683. + XRX200_MAC_CTRL_0_FCON, /* Flow Control Mode */
  2684. +// XRX200_MAC_CTRL_0_FDUP, /* Full Duplex Control */
  2685. +// XRX200_MAC_CTRL_0_GMII, /* GMII/MII interface mode selection */
  2686. +// XRX200_MAC_CTRL_1, /* MAC Control Register1 */
  2687. +// XRX200_MAC_CTRL_1_SHORTPRE, /* Short Preamble Control */
  2688. +// XRX200_MAC_CTRL_1_IPG, /* Minimum Inter Packet Gap Size */
  2689. +// XRX200_MAC_CTRL_2, /* MAC Control Register2 */
  2690. +// XRX200_MAC_CTRL_2_MLEN, /* Maximum Untagged Frame Length */
  2691. +// XRX200_MAC_CTRL_2_LCHKL, /* Frame Length Check Long Enable */
  2692. +// XRX200_MAC_CTRL_2_LCHKS, /* Frame Length Check Short Enable */
  2693. +// XRX200_MAC_CTRL_3, /* MAC Control Register3 */
  2694. +// XRX200_MAC_CTRL_3_RCNT, /* Retry Count */
  2695. +// XRX200_MAC_CTRL_4, /* MAC Control Register4 */
  2696. +// XRX200_MAC_CTRL_4_LPIEN, /* LPI Mode Enable */
  2697. +// XRX200_MAC_CTRL_4_WAIT, /* LPI Wait Time */
  2698. +// XRX200_MAC_CTRL_5_PJPS, /* MAC Control Register5 */
  2699. +// XRX200_MAC_CTRL_5_PJPS_NOBP, /* Prolonged Jam pattern size during no-backpressure state */
  2700. +// XRX200_MAC_CTRL_5_PJPS_BP, /* Prolonged Jam pattern size during backpressure state */
  2701. +// XRX200_MAC_CTRL_6_XBUF, /* Transmit and ReceiveBuffer Control Register */
  2702. +// XRX200_MAC_CTRL_6_RBUF_DLY_WP, /* Delay */
  2703. +// XRX200_MAC_CTRL_6_RBUF_INIT, /* Receive Buffer Initialization */
  2704. +// XRX200_MAC_CTRL_6_RBUF_BYPASS, /* Bypass the Receive Buffer */
  2705. +// XRX200_MAC_CTRL_6_XBUF_DLY_WP, /* Delay */
  2706. +// XRX200_MAC_CTRL_6_XBUF_INIT, /* Initialize the Transmit Buffer */
  2707. +// XRX200_MAC_CTRL_6_XBUF_BYPASS, /* Bypass the Transmit Buffer */
  2708. +// XRX200_MAC_BUFST_XBUF, /* MAC Receive and TransmitBuffer Status Register */
  2709. +// XRX200_MAC_BUFST_RBUF_UFL, /* Receive Buffer Underflow Indicator */
  2710. +// XRX200_MAC_BUFST_RBUF_OFL, /* Receive Buffer Overflow Indicator */
  2711. +// XRX200_MAC_BUFST_XBUF_UFL, /* Transmit Buffer Underflow Indicator */
  2712. +// XRX200_MAC_BUFST_XBUF_OFL, /* Transmit Buffer Overflow Indicator */
  2713. +// XRX200_MAC_TESTEN, /* MAC Test Enable Register */
  2714. +// XRX200_MAC_TESTEN_JTEN, /* Jitter Test Enable */
  2715. +// XRX200_MAC_TESTEN_TXER, /* Transmit Error Insertion */
  2716. +// XRX200_MAC_TESTEN_LOOP, /* MAC Loopback Enable */
  2717. +// XRX200_FDMA_CTRL, /* Ethernet Switch FetchDMA Control Register */
  2718. +// XRX200_FDMA_CTRL_LPI_THRESHOLD, /* Low Power Idle Threshold */
  2719. +// XRX200_FDMA_CTRL_LPI_MODE, /* Low Power Idle Mode */
  2720. +// XRX200_FDMA_CTRL_EGSTAG, /* Egress Special Tag Size */
  2721. +// XRX200_FDMA_CTRL_IGSTAG, /* Ingress Special Tag Size */
  2722. +// XRX200_FDMA_CTRL_EXCOL, /* Excessive Collision Handling */
  2723. +// XRX200_FDMA_STETYPE, /* Special Tag EthertypeControl Register */
  2724. +// XRX200_FDMA_STETYPE_ETYPE, /* Special Tag Ethertype */
  2725. +// XRX200_FDMA_VTETYPE, /* VLAN Tag EthertypeControl Register */
  2726. +// XRX200_FDMA_VTETYPE_ETYPE, /* VLAN Tag Ethertype */
  2727. +// XRX200_FDMA_STAT_0, /* FDMA Status Register0 */
  2728. +// XRX200_FDMA_STAT_0_FSMS, /* FSM states status */
  2729. +// XRX200_FDMA_IER, /* Fetch DMA Global InterruptEnable Register */
  2730. +// XRX200_FDMA_IER_PCKD, /* Packet Drop Interrupt Enable */
  2731. +// XRX200_FDMA_IER_PCKR, /* Packet Ready Interrupt Enable */
  2732. +// XRX200_FDMA_IER_PCKT, /* Packet Sent Interrupt Enable */
  2733. +// XRX200_FDMA_ISR, /* Fetch DMA Global InterruptStatus Register */
  2734. +// XRX200_FDMA_ISR_PCKTD, /* Packet Drop */
  2735. +// XRX200_FDMA_ISR_PCKR, /* Packet is Ready for Transmission */
  2736. +// XRX200_FDMA_ISR_PCKT, /* Packet Sent Event */
  2737. +// XRX200_FDMA_PCTRL, /* Ethernet SwitchFetch DMA Port Control Register */
  2738. +// XRX200_FDMA_PCTRL_VLANMOD, /* VLAN Modification Enable */
  2739. +// XRX200_FDMA_PCTRL_DSCPRM, /* DSCP Re-marking Enable */
  2740. +// XRX200_FDMA_PCTRL_STEN, /* Special Tag Insertion Enable */
  2741. +// XRX200_FDMA_PCTRL_EN, /* FDMA Port Enable */
  2742. +// XRX200_FDMA_PRIO, /* Ethernet SwitchFetch DMA Port Priority Register */
  2743. +// XRX200_FDMA_PRIO_PRIO, /* FDMA PRIO */
  2744. +// XRX200_FDMA_PSTAT0, /* Ethernet SwitchFetch DMA Port Status Register 0 */
  2745. +// XRX200_FDMA_PSTAT0_PKT_AVAIL, /* Port Egress Packet Available */
  2746. +// XRX200_FDMA_PSTAT0_POK, /* Port Status OK */
  2747. +// XRX200_FDMA_PSTAT0_PSEG, /* Port Egress Segment Count */
  2748. +// XRX200_FDMA_PSTAT1_HDR, /* Ethernet SwitchFetch DMA Port Status Register 1 */
  2749. +// XRX200_FDMA_PSTAT1_HDR_PTR, /* Header Pointer */
  2750. +// XRX200_FDMA_TSTAMP0, /* Egress TimeStamp Register 0 */
  2751. +// XRX200_FDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */
  2752. +// XRX200_FDMA_TSTAMP1, /* Egress TimeStamp Register 1 */
  2753. +// XRX200_FDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */
  2754. +// XRX200_SDMA_CTRL, /* Ethernet Switch StoreDMA Control Register */
  2755. +// XRX200_SDMA_CTRL_TSTEN, /* Time Stamp Enable */
  2756. +// XRX200_SDMA_FCTHR1, /* SDMA Flow Control Threshold1 Register */
  2757. +// XRX200_SDMA_FCTHR1_THR1, /* Threshold 1 */
  2758. +// XRX200_SDMA_FCTHR2, /* SDMA Flow Control Threshold2 Register */
  2759. +// XRX200_SDMA_FCTHR2_THR2, /* Threshold 2 */
  2760. +// XRX200_SDMA_FCTHR3, /* SDMA Flow Control Threshold3 Register */
  2761. +// XRX200_SDMA_FCTHR3_THR3, /* Threshold 3 */
  2762. +// XRX200_SDMA_FCTHR4, /* SDMA Flow Control Threshold4 Register */
  2763. +// XRX200_SDMA_FCTHR4_THR4, /* Threshold 4 */
  2764. +// XRX200_SDMA_FCTHR5, /* SDMA Flow Control Threshold5 Register */
  2765. +// XRX200_SDMA_FCTHR5_THR5, /* Threshold 5 */
  2766. +// XRX200_SDMA_FCTHR6, /* SDMA Flow Control Threshold6 Register */
  2767. +// XRX200_SDMA_FCTHR6_THR6, /* Threshold 6 */
  2768. +// XRX200_SDMA_FCTHR7, /* SDMA Flow Control Threshold7 Register */
  2769. +// XRX200_SDMA_FCTHR7_THR7, /* Threshold 7 */
  2770. +// XRX200_SDMA_STAT_0, /* SDMA Status Register0 */
  2771. +// XRX200_SDMA_STAT_0_BPS_FILL, /* Back Pressure Status */
  2772. +// XRX200_SDMA_STAT_0_BPS_PNT, /* Back Pressure Status */
  2773. +// XRX200_SDMA_STAT_0_DROP, /* Back Pressure Status */
  2774. +// XRX200_SDMA_STAT_1, /* SDMA Status Register1 */
  2775. +// XRX200_SDMA_STAT_1_FILL, /* Buffer Filling Level */
  2776. +// XRX200_SDMA_STAT_2, /* SDMA Status Register2 */
  2777. +// XRX200_SDMA_STAT_2_FSMS, /* FSM states status */
  2778. +// XRX200_SDMA_IER, /* SDMA Interrupt Enable Register */
  2779. +// XRX200_SDMA_IER_BPEX, /* Buffer Pointers Exceeded */
  2780. +// XRX200_SDMA_IER_BFULL, /* Buffer Full */
  2781. +// XRX200_SDMA_IER_FERR, /* Frame Error */
  2782. +// XRX200_SDMA_IER_FRX, /* Frame Received Successfully */
  2783. +// XRX200_SDMA_ISR, /* SDMA Interrupt Status Register */
  2784. +// XRX200_SDMA_ISR_BPEX, /* Packet Descriptors Exceeded */
  2785. +// XRX200_SDMA_ISR_BFULL, /* Buffer Full */
  2786. +// XRX200_SDMA_ISR_FERR, /* Frame Error */
  2787. +// XRX200_SDMA_ISR_FRX, /* Frame Received Successfully */
  2788. +// XRX200_SDMA_PCTRL, /* Ethernet SwitchStore DMA Port Control Register */
  2789. +// XRX200_SDMA_PCTRL_DTHR, /* Drop Threshold Selection */
  2790. +// XRX200_SDMA_PCTRL_PTHR, /* Pause Threshold Selection */
  2791. +// XRX200_SDMA_PCTRL_PHYEFWD, /* Forward PHY Error Frames */
  2792. +// XRX200_SDMA_PCTRL_ALGFWD, /* Forward Alignment Error Frames */
  2793. +// XRX200_SDMA_PCTRL_LENFWD, /* Forward Length Errored Frames */
  2794. +// XRX200_SDMA_PCTRL_OSFWD, /* Forward Oversized Frames */
  2795. +// XRX200_SDMA_PCTRL_USFWD, /* Forward Undersized Frames */
  2796. +// XRX200_SDMA_PCTRL_FCSIGN, /* Ignore FCS Errors */
  2797. +// XRX200_SDMA_PCTRL_FCSFWD, /* Forward FCS Errored Frames */
  2798. +// XRX200_SDMA_PCTRL_PAUFWD, /* Pause Frame Forwarding */
  2799. +// XRX200_SDMA_PCTRL_MFCEN, /* Metering Flow Control Enable */
  2800. +// XRX200_SDMA_PCTRL_FCEN, /* Flow Control Enable */
  2801. +// XRX200_SDMA_PCTRL_PEN, /* Port Enable */
  2802. +// XRX200_SDMA_PRIO, /* Ethernet SwitchStore DMA Port Priority Register */
  2803. +// XRX200_SDMA_PRIO_PRIO, /* SDMA PRIO */
  2804. +// XRX200_SDMA_PSTAT0_HDR, /* Ethernet SwitchStore DMA Port Status Register 0 */
  2805. +// XRX200_SDMA_PSTAT0_HDR_PTR, /* Port Ingress Queue Header Pointer */
  2806. +// XRX200_SDMA_PSTAT1, /* Ethernet SwitchStore DMA Port Status Register 1 */
  2807. +// XRX200_SDMA_PSTAT1_PPKT, /* Port Ingress Packet Count */
  2808. +// XRX200_SDMA_TSTAMP0, /* Ingress TimeStamp Register 0 */
  2809. +// XRX200_SDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */
  2810. +// XRX200_SDMA_TSTAMP1, /* Ingress TimeStamp Register 1 */
  2811. +// XRX200_SDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */
  2812. +};
  2813. +
  2814. +
  2815. +struct xrx200sw_reg {
  2816. + int offset;
  2817. + int shift;
  2818. + int size;
  2819. + int mult;
  2820. +} xrx200sw_reg[] = {
  2821. +// offeset shift size mult
  2822. +// {0x0000, 0, 16, 0x00}, /* XRX200_ETHSW_SWRES Ethernet Switch ResetControl Register */
  2823. +// {0x0000, 1, 1, 0x00}, /* XRX200_ETHSW_SWRES_R1 Hardware Reset */
  2824. +// {0x0000, 0, 1, 0x00}, /* XRX200_ETHSW_SWRES_R0 Register Configuration */
  2825. +// {0x0004, 0, 16, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT Ethernet Switch Clock ControlRegister */
  2826. +// {0x0004, 12, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_SLEEP Exponent to put system into sleep */
  2827. +// {0x0004, 8, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_WAKE Exponent to wake up system */
  2828. +// {0x0004, 7, 1, 0x00}, /* XRX200_ETHSW_CLK_CLK2_EN CLK2 Input for MAC */
  2829. +// {0x0004, 6, 1, 0x00}, /* XRX200_ETHSW_CLK_EXT_DIV_EN External Clock Divider Enable */
  2830. +// {0x0004, 5, 1, 0x00}, /* XRX200_ETHSW_CLK_RAM_DBG_EN Clock Gating Enable */
  2831. +// {0x0004, 4, 1, 0x00}, /* XRX200_ETHSW_CLK_REG_GAT_EN Clock Gating Enable */
  2832. +// {0x0004, 3, 1, 0x00}, /* XRX200_ETHSW_CLK_GAT_EN Clock Gating Enable */
  2833. +// {0x0004, 2, 1, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT_EN Clock Gating Enable */
  2834. +// {0x0008, 0, 16, 0x00}, /* XRX200_ETHSW_DBG_STEP Ethernet Switch Debug ControlRegister */
  2835. +// {0x0008, 12, 4, 0x00}, /* XRX200_ETHSW_DBG_CLK_SEL Trigger Enable */
  2836. +// {0x0008, 11, 1, 0x00}, /* XRX200_ETHSW_DBG_MON_EN Monitoring Enable */
  2837. +// {0x0008, 9, 2, 0x00}, /* XRX200_ETHSW_DBG_TRIG_EN Trigger Enable */
  2838. +// {0x0008, 8, 1, 0x00}, /* XRX200_ETHSW_DBG_MODE Debug Mode */
  2839. +// {0x0008, 0, 8, 0x00}, /* XRX200_ETHSW_DBG_STEP_TIME Clock Step Size */
  2840. +// {0x000C, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_MODE Ethernet Switch SharedSegment Buffer Mode Register */
  2841. +// {0x000C, 2, 4, 0x00}, /* XRX200_ETHSW_SSB_MODE_ADDE Memory Address */
  2842. +// {0x000C, 0, 2, 0x00}, /* XRX200_ETHSW_SSB_MODE_MODE Memory Access Mode */
  2843. +// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR Ethernet Switch SharedSegment Buffer Address Register */
  2844. +// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR_ADDE Memory Address */
  2845. +// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA Ethernet Switch SharedSegment Buffer Data Register */
  2846. +// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA_DATA Data Value */
  2847. +// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0 Ethernet Switch CapabilityRegister 0 */
  2848. +// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0_SPEED Clock frequency */
  2849. +// {0x001C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_1 Ethernet Switch CapabilityRegister 1 */
  2850. +// {0x001C, 15, 1, 0x00}, /* XRX200_ETHSW_CAP_1_GMAC MAC operation mode */
  2851. +// {0x001C, 8, 7, 0x00}, /* XRX200_ETHSW_CAP_1_QUEUE Number of queues */
  2852. +// {0x001C, 4, 4, 0x00}, /* XRX200_ETHSW_CAP_1_VPORTS Number of virtual ports */
  2853. +// {0x001C, 0, 4, 0x00}, /* XRX200_ETHSW_CAP_1_PPORTS Number of physical ports */
  2854. +// {0x0020, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_2 Ethernet Switch CapabilityRegister 2 */
  2855. +// {0x0020, 0, 11, 0x00}, /* XRX200_ETHSW_CAP_2_PACKETS Number of packets */
  2856. +// {0x0024, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_3 Ethernet Switch CapabilityRegister 3 */
  2857. +// {0x0024, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_3_METERS Number of traffic meters */
  2858. +// {0x0024, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_3_SHAPERS Number of traffic shapers */
  2859. +// {0x0028, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_4 Ethernet Switch CapabilityRegister 4 */
  2860. +// {0x0028, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_4_PPPOE PPPoE table size */
  2861. +// {0x0028, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_4_VLAN Active VLAN table size */
  2862. +// {0x002C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_5 Ethernet Switch CapabilityRegister 5 */
  2863. +// {0x002C, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_5_IPPLEN IP packet length table size */
  2864. +// {0x002C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_5_PROT Protocol table size */
  2865. +// {0x0030, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_6 Ethernet Switch CapabilityRegister 6 */
  2866. +// {0x0030, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_6_MACDASA MAC DA/SA table size */
  2867. +// {0x0030, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_6_APPL Application table size */
  2868. +// {0x0034, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_7 Ethernet Switch CapabilityRegister 7 */
  2869. +// {0x0034, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAM IP DA/SA MSB table size */
  2870. +// {0x0034, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAL IP DA/SA LSB table size */
  2871. +// {0x0038, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_8 Ethernet Switch CapabilityRegister 8 */
  2872. +// {0x0038, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_8_MCAST Multicast table size */
  2873. +// {0x003C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_9 Ethernet Switch CapabilityRegister 9 */
  2874. +// {0x003C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_9_FLAGG Flow Aggregation table size */
  2875. +// {0x0040, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_10 Ethernet Switch CapabilityRegister 10 */
  2876. +// {0x0040, 0, 13, 0x00}, /* XRX200_ETHSW_CAP_10_MACBT MAC bridging table size */
  2877. +// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11 Ethernet Switch CapabilityRegister 11 */
  2878. +// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11_BSIZEL Packet buffer size (lower part, in byte) */
  2879. +// {0x0048, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_12 Ethernet Switch CapabilityRegister 12 */
  2880. +// {0x0048, 0, 3, 0x00}, /* XRX200_ETHSW_CAP_12_BSIZEH Packet buffer size (higher part, in byte) */
  2881. +// {0x004C, 0, 16, 0x00}, /* XRX200_ETHSW_VERSION_REV Ethernet Switch VersionRegister */
  2882. +// {0x004C, 8, 8, 0x00}, /* XRX200_ETHSW_VERSION_MOD_ID Module Identification */
  2883. +// {0x004C, 0, 8, 0x00}, /* XRX200_ETHSW_VERSION_REV_ID Hardware Revision Identification */
  2884. +// {0x0050, 0, 16, 0x00}, /* XRX200_ETHSW_IER Interrupt Enable Register */
  2885. +// {0x0050, 4, 1, 0x00}, /* XRX200_ETHSW_IER_FDMAIE Fetch DMA Interrupt Enable */
  2886. +// {0x0050, 3, 1, 0x00}, /* XRX200_ETHSW_IER_SDMAIE Store DMA Interrupt Enable */
  2887. +// {0x0050, 2, 1, 0x00}, /* XRX200_ETHSW_IER_MACIE Ethernet MAC Interrupt Enable */
  2888. +// {0x0050, 1, 1, 0x00}, /* XRX200_ETHSW_IER_PCEIE Parser and Classification Engine Interrupt Enable */
  2889. +// {0x0050, 0, 1, 0x00}, /* XRX200_ETHSW_IER_BMIE Buffer Manager Interrupt Enable */
  2890. +// {0x0054, 0, 16, 0x00}, /* XRX200_ETHSW_ISR Interrupt Status Register */
  2891. +// {0x0054, 4, 1, 0x00}, /* XRX200_ETHSW_ISR_FDMAINT Fetch DMA Interrupt */
  2892. +// {0x0054, 3, 1, 0x00}, /* XRX200_ETHSW_ISR_SDMAINT Store DMA Interrupt */
  2893. +// {0x0054, 2, 1, 0x00}, /* XRX200_ETHSW_ISR_MACINT Ethernet MAC Interrupt */
  2894. +// {0x0054, 1, 1, 0x00}, /* XRX200_ETHSW_ISR_PCEINT Parser and Classification Engine Interrupt */
  2895. +// {0x0054, 0, 1, 0x00}, /* XRX200_ETHSW_ISR_BMINT Buffer Manager Interrupt */
  2896. +// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0 Ethernet Switch SpareCells 0 */
  2897. +// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0_SPARE SPARE0 */
  2898. +// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1 Ethernet Switch SpareCells 1 */
  2899. +// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1_SPARE SPARE1 */
  2900. +// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2 Ethernet Switch SpareCells 2 */
  2901. +// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2_SPARE SPARE2 */
  2902. +// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3 Ethernet Switch SpareCells 3 */
  2903. +// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3_SPARE SPARE3 */
  2904. +// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4 Ethernet Switch SpareCells 4 */
  2905. +// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4_SPARE SPARE4 */
  2906. +// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5 Ethernet Switch SpareCells 5 */
  2907. +// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5_SPARE SPARE5 */
  2908. +// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6 Ethernet Switch SpareCells 6 */
  2909. +// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6_SPARE SPARE6 */
  2910. +// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7 Ethernet Switch SpareCells 7 */
  2911. +// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7_SPARE SPARE7 */
  2912. +// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8 Ethernet Switch SpareCells 8 */
  2913. +// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8_SPARE SPARE8 */
  2914. +// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9 Ethernet Switch SpareCells 9 */
  2915. +// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9_SPARE SPARE9 */
  2916. +// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10 Ethernet Switch SpareCells 10 */
  2917. +// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10_SPARE SPARE10 */
  2918. +// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11 Ethernet Switch SpareCells 11 */
  2919. +// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11_SPARE SPARE11 */
  2920. +// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12 Ethernet Switch SpareCells 12 */
  2921. +// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12_SPARE SPARE12 */
  2922. +// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13 Ethernet Switch SpareCells 13 */
  2923. +// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13_SPARE SPARE13 */
  2924. +// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14 Ethernet Switch SpareCells 14 */
  2925. +// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14_SPARE SPARE14 */
  2926. +// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15 Ethernet Switch SpareCells 15 */
  2927. +// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15_SPARE SPARE15 */
  2928. +// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3 RAM Value Register 3 */
  2929. +// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3_VAL3 Data value [15:0] */
  2930. +// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2 RAM Value Register 2 */
  2931. +// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2_VAL2 Data value [15:0] */
  2932. +// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1 RAM Value Register 1 */
  2933. +// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1_VAL1 Data value [15:0] */
  2934. +// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0 RAM Value Register 0 */
  2935. +// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0_VAL0 Data value [15:0] */
  2936. +// {0x0110, 0, 16, 0x00}, /* XRX200_BM_RAM_ADDR RAM Address Register */
  2937. +// {0x0110, 0, 11, 0x00}, /* XRX200_BM_RAM_ADDR_ADDR RAM Address */
  2938. +// {0x0114, 0, 16, 0x00}, /* XRX200_BM_RAM_CTRL RAM Access Control Register */
  2939. +// {0x0114, 15, 1, 0x00}, /* XRX200_BM_RAM_CTRL_BAS Access Busy/Access Start */
  2940. +// {0x0114, 5, 1, 0x00}, /* XRX200_BM_RAM_CTRL_OPMOD Lookup Table Access Operation Mode */
  2941. +// {0x0114, 0, 5, 0x00}, /* XRX200_BM_RAM_CTRL_ADDR Address for RAM selection */
  2942. +// {0x0118, 0, 16, 0x00}, /* XRX200_BM_FSQM_GCTRL Free Segment Queue ManagerGlobal Control Register */
  2943. +// {0x0118, 0, 10, 0x00}, /* XRX200_BM_FSQM_GCTRL_SEGNUM Maximum Segment Number */
  2944. +// {0x011C, 0, 16, 0x00}, /* XRX200_BM_CONS_SEG Number of Consumed SegmentsRegister */
  2945. +// {0x011C, 0, 10, 0x00}, /* XRX200_BM_CONS_SEG_FSEG Number of Consumed Segments */
  2946. +// {0x0120, 0, 16, 0x00}, /* XRX200_BM_CONS_PKT Number of Consumed PacketPointers Register */
  2947. +// {0x0120, 0, 11, 0x00}, /* XRX200_BM_CONS_PKT_FQP Number of Consumed Packet Pointers */
  2948. +// {0x0124, 0, 16, 0x00}, /* XRX200_BM_GCTRL_F Buffer Manager Global ControlRegister 0 */
  2949. +// {0x0124, 13, 1, 0x00}, /* XRX200_BM_GCTRL_BM_STA Buffer Manager Initialization Status Bit */
  2950. +// {0x0124, 12, 1, 0x00}, /* XRX200_BM_GCTRL_SAT RMON Counter Update Mode */
  2951. +// {0x0124, 11, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RBC Freeze RMON RX Bad Byte 64 Bit Counter */
  2952. +// {0x0124, 10, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RGC Freeze RMON RX Good Byte 64 Bit Counter */
  2953. +// {0x0124, 9, 1, 0x00}, /* XRX200_BM_GCTRL_FR_TGC Freeze RMON TX Good Byte 64 Bit Counter */
  2954. +// {0x0124, 8, 1, 0x00}, /* XRX200_BM_GCTRL_I_FIN RAM initialization finished */
  2955. +// {0x0124, 7, 1, 0x00}, /* XRX200_BM_GCTRL_CX_INI PQM Context RAM initialization */
  2956. +// {0x0124, 6, 1, 0x00}, /* XRX200_BM_GCTRL_FP_INI FPQM RAM initialization */
  2957. +// {0x0124, 5, 1, 0x00}, /* XRX200_BM_GCTRL_FS_INI FSQM RAM initialization */
  2958. +// {0x0124, 4, 1, 0x00}, /* XRX200_BM_GCTRL_R_SRES Software Reset for RMON */
  2959. +// {0x0124, 3, 1, 0x00}, /* XRX200_BM_GCTRL_S_SRES Software Reset for Scheduler */
  2960. +// {0x0124, 2, 1, 0x00}, /* XRX200_BM_GCTRL_A_SRES Software Reset for AVG */
  2961. +// {0x0124, 1, 1, 0x00}, /* XRX200_BM_GCTRL_P_SRES Software Reset for PQM */
  2962. +// {0x0124, 0, 1, 0x00}, /* XRX200_BM_GCTRL_F_SRES Software Reset for FSQM */
  2963. +// {0x0128, 0, 16, 0x00}, /* XRX200_BM_QUEUE_GCTRL Queue Manager GlobalControl Register 0 */
  2964. + {0x0128, 10, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_GL_MOD WRED Mode Signal */
  2965. +// {0x0128, 7, 3, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQUI Average Queue Update Interval */
  2966. +// {0x0128, 3, 4, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQWF Average Queue Weight Factor */
  2967. +// {0x0128, 2, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_QAVGEN Queue Average Calculation Enable */
  2968. +// {0x0128, 0, 2, 0x00}, /* XRX200_BM_QUEUE_GCTRL_DPROB Drop Probability Profile */
  2969. +// {0x012C, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_0 WRED Red Threshold Register0 */
  2970. +// {0x012C, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_0_MINTH Minimum Threshold */
  2971. +// {0x0130, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_1 WRED Red Threshold Register1 */
  2972. +// {0x0130, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_1_MAXTH Maximum Threshold */
  2973. +// {0x0134, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_0 WRED Yellow ThresholdRegister 0 */
  2974. +// {0x0134, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_0_MINTH Minimum Threshold */
  2975. +// {0x0138, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_1 WRED Yellow ThresholdRegister 1 */
  2976. +// {0x0138, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_1_MAXTH Maximum Threshold */
  2977. +// {0x013C, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_0 WRED Green ThresholdRegister 0 */
  2978. +// {0x013C, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_0_MINTH Minimum Threshold */
  2979. +// {0x0140, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_1 WRED Green ThresholdRegister 1 */
  2980. +// {0x0140, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_1_MAXTH Maximum Threshold */
  2981. +// {0x0144, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_0_THR Drop Threshold ConfigurationRegister 0 */
  2982. +// {0x0144, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_0_THR_FQ Threshold for frames marked red */
  2983. +// {0x0148, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_1_THY Drop Threshold ConfigurationRegister 1 */
  2984. +// {0x0148, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_1_THY_FQ Threshold for frames marked yellow */
  2985. +// {0x014C, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_2_THG Drop Threshold ConfigurationRegister 2 */
  2986. +// {0x014C, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_2_THG_FQ Threshold for frames marked green */
  2987. +// {0x0150, 0, 16, 0x00}, /* XRX200_BM_IER Buffer Manager Global InterruptEnable Register */
  2988. +// {0x0150, 7, 1, 0x00}, /* XRX200_BM_IER_CNT4 Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */
  2989. +// {0x0150, 6, 1, 0x00}, /* XRX200_BM_IER_CNT3 Counter Group 3 (RMON-PQM) Interrupt Enable */
  2990. +// {0x0150, 5, 1, 0x00}, /* XRX200_BM_IER_CNT2 Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */
  2991. +// {0x0150, 4, 1, 0x00}, /* XRX200_BM_IER_CNT1 Counter Group 1 (RMON-QFETCH) Interrupt Enable */
  2992. +// {0x0150, 3, 1, 0x00}, /* XRX200_BM_IER_CNT0 Counter Group 0 (RMON-QSTOR) Interrupt Enable */
  2993. +// {0x0150, 2, 1, 0x00}, /* XRX200_BM_IER_DEQ PQM dequeue Interrupt Enable */
  2994. +// {0x0150, 1, 1, 0x00}, /* XRX200_BM_IER_ENQ PQM Enqueue Interrupt Enable */
  2995. +// {0x0150, 0, 1, 0x00}, /* XRX200_BM_IER_FSQM Buffer Empty Interrupt Enable */
  2996. +// {0x0154, 0, 16, 0x00}, /* XRX200_BM_ISR Buffer Manager Global InterruptStatus Register */
  2997. +// {0x0154, 7, 1, 0x00}, /* XRX200_BM_ISR_CNT4 Counter Group 4 Interrupt */
  2998. +// {0x0154, 6, 1, 0x00}, /* XRX200_BM_ISR_CNT3 Counter Group 3 Interrupt */
  2999. +// {0x0154, 5, 1, 0x00}, /* XRX200_BM_ISR_CNT2 Counter Group 2 Interrupt */
  3000. +// {0x0154, 4, 1, 0x00}, /* XRX200_BM_ISR_CNT1 Counter Group 1 Interrupt */
  3001. +// {0x0154, 3, 1, 0x00}, /* XRX200_BM_ISR_CNT0 Counter Group 0 Interrupt */
  3002. +// {0x0154, 2, 1, 0x00}, /* XRX200_BM_ISR_DEQ PQM dequeue Interrupt Enable */
  3003. +// {0x0154, 1, 1, 0x00}, /* XRX200_BM_ISR_ENQ PQM Enqueue Interrupt */
  3004. +// {0x0154, 0, 1, 0x00}, /* XRX200_BM_ISR_FSQM Buffer Empty Interrupt */
  3005. +// {0x0158, 0, 16, 0x00}, /* XRX200_BM_CISEL Buffer Manager RMON CounterInterrupt Select Register */
  3006. +// {0x0158, 0, 3, 0x00}, /* XRX200_BM_CISEL_PORT Port Number */
  3007. +// {0x015C, 0, 16, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG Debug Control Register */
  3008. +// {0x015C, 0, 8, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG_SEL Select Signal for Debug Multiplexer */
  3009. +// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG Debug Value Register */
  3010. +// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG_DAT Debug Data Value */
  3011. +// {0x0200, 0, 16, 0x08}, /* XRX200_BM_PCFG Buffer Manager PortConfiguration Register */
  3012. +// {0x0200, 0, 1, 0x08}, /* XRX200_BM_PCFG_CNTEN RMON Counter Enable */
  3013. +// {0x0204, 0, 16, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1 Buffer ManagerRMON Control Register */
  3014. +// {0x0204, 1, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM2_RES Software Reset for RMON RAM2 */
  3015. +// {0x0204, 0, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1_RES Software Reset for RMON RAM1 */
  3016. +// {0x0400, 0, 16, 0x08}, /* XRX200_PQM_DP Packet Queue ManagerDrop Probability Register */
  3017. +// {0x0400, 0, 2, 0x08}, /* XRX200_PQM_DP_DPROB Drop Probability Profile */
  3018. +// {0x0404, 0, 16, 0x08}, /* XRX200_PQM_RS Packet Queue ManagerRate Shaper Assignment Register */
  3019. +// {0x0404, 15, 1, 0x08}, /* XRX200_PQM_RS_EN2 Rate Shaper 2 Enable */
  3020. +// {0x0404, 8, 6, 0x08}, /* XRX200_PQM_RS_RS2 Rate Shaper 2 */
  3021. +// {0x0404, 7, 1, 0x08}, /* XRX200_PQM_RS_EN1 Rate Shaper 1 Enable */
  3022. +// {0x0404, 0, 6, 0x08}, /* XRX200_PQM_RS_RS1 Rate Shaper 1 */
  3023. +// {0x0500, 0, 16, 0x14}, /* XRX200_RS_CTRL Rate Shaper ControlRegister */
  3024. +// {0x0500, 0, 1, 0x14}, /* XRX200_RS_CTRL_RSEN Rate Shaper Enable */
  3025. +// {0x0504, 0, 16, 0x14}, /* XRX200_RS_CBS Rate Shaper CommittedBurst Size Register */
  3026. +// {0x0504, 0, 10, 0x14}, /* XRX200_RS_CBS_CBS Committed Burst Size */
  3027. +// {0x0508, 0, 16, 0x14}, /* XRX200_RS_IBS Rate Shaper InstantaneousBurst Size Register */
  3028. +// {0x0508, 0, 2, 0x14}, /* XRX200_RS_IBS_IBS Instantaneous Burst Size */
  3029. +// {0x050C, 0, 16, 0x14}, /* XRX200_RS_CIR_EXP Rate Shaper RateExponent Register */
  3030. +// {0x050C, 0, 4, 0x14}, /* XRX200_RS_CIR_EXP_EXP Exponent */
  3031. +// {0x0510, 0, 16, 0x14}, /* XRX200_RS_CIR_MANT Rate Shaper RateMantissa Register */
  3032. +// {0x0510, 0, 10, 0x14}, /* XRX200_RS_CIR_MANT_MANT Mantissa */
  3033. + {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7 Table Key Data 7 */
  3034. +// {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7_KEY7 Key Value[15:0] */
  3035. + {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6 Table Key Data 6 */
  3036. +// {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6_KEY6 Key Value[15:0] */
  3037. + {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5 Table Key Data 5 */
  3038. +// {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5_KEY5 Key Value[15:0] */
  3039. + {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4 Table Key Data 4 */
  3040. +// {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4_KEY4 Key Value[15:0] */
  3041. + {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3 Table Key Data 3 */
  3042. +// {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3_KEY3 Key Value[15:0] */
  3043. + {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2 Table Key Data 2 */
  3044. +// {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2_KEY2 Key Value[15:0] */
  3045. + {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1 Table Key Data 1 */
  3046. +// {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1_KEY1 Key Value[31:16] */
  3047. + {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0 Table Key Data 0 */
  3048. +// {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0_KEY0 Key Value[15:0] */
  3049. + {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0 Table Mask Write Register0 */
  3050. +// {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0_MASK0 Mask Pattern [15:0] */
  3051. + {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4 Table Value Register4 */
  3052. +// {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4_VAL4 Data value [15:0] */
  3053. + {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3 Table Value Register3 */
  3054. +// {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3_VAL3 Data value [15:0] */
  3055. + {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2 Table Value Register2 */
  3056. +// {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2_VAL2 Data value [15:0] */
  3057. + {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1 Table Value Register1 */
  3058. +// {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1_VAL1 Data value [15:0] */
  3059. + {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0 Table Value Register0 */
  3060. +// {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0_VAL0 Data value [15:0] */
  3061. +// {0x1138, 0, 16, 0x00}, /* XRX200_PCE_TBL_ADDR Table Entry AddressRegister */
  3062. + {0x1138, 0, 11, 0x00}, /* XRX200_PCE_TBL_ADDR_ADDR Table Address */
  3063. +// {0x113C, 0, 16, 0x00}, /* XRX200_PCE_TBL_CTRL Table Access ControlRegister */
  3064. + {0x113C, 15, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_BAS Access Busy/Access Start */
  3065. + {0x113C, 13, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_TYPE Lookup Entry Type */
  3066. + {0x113C, 12, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_VLD Lookup Entry Valid */
  3067. + {0x113C, 7, 4, 0x00}, /* XRX200_PCE_TBL_CTRL_GMAP Group Map */
  3068. + {0x113C, 5, 2, 0x00}, /* XRX200_PCE_TBL_CTRL_OPMOD Lookup Table Access Operation Mode */
  3069. + {0x113C, 0, 5, 0x00}, /* XRX200_PCE_TBL_CTRL_ADDR Lookup Table Address */
  3070. +// {0x1140, 0, 16, 0x00}, /* XRX200_PCE_TBL_STAT Table General StatusRegister */
  3071. +// {0x1140, 2, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TBUSY Table Access Busy */
  3072. +// {0x1140, 1, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TEMPT Table Empty */
  3073. +// {0x1140, 0, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TFUL Table Full */
  3074. +// {0x1144, 0, 16, 0x00}, /* XRX200_PCE_AGE_0 Aging Counter ConfigurationRegister 0 */
  3075. +// {0x1144, 0, 4, 0x00}, /* XRX200_PCE_AGE_0_EXP Aging Counter Exponent Value */
  3076. +// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1 Aging Counter ConfigurationRegister 1 */
  3077. +// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1_MANT Aging Counter Mantissa Value */
  3078. +// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1 Port Map Register 1 */
  3079. +// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1_MPMAP Monitoring Port Map */
  3080. +// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2 Port Map Register 2 */
  3081. +// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2_DMCPMAP Default Multicast Port Map */
  3082. +// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3 Port Map Register 3 */
  3083. +// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3_UUCMAP Default Unknown Unicast Port Map */
  3084. +// {0x1158, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_0 PCE Global Control Register0 */
  3085. +// {0x1158, 15, 1, 0x00}, /* XRX200_PCE_GCTRL_0_IGMP IGMP Mode Selection */
  3086. + {0x1158, 14, 1, 0x00}, /* XRX200_PCE_GCTRL_0_VLAN VLAN-aware Switching */
  3087. +// {0x1158, 13, 1, 0x00}, /* XRX200_PCE_GCTRL_0_NOPM No Port Map Forwarding */
  3088. +// {0x1158, 12, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONUC Unknown Unicast Storm Control */
  3089. +// {0x1158, 11, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMC Multicast Storm Control */
  3090. +// {0x1158, 10, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONBC Broadcast Storm Control */
  3091. +// {0x1158, 8, 2, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMOD Storm Control Mode */
  3092. +// {0x1158, 4, 4, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMET Storm Control Metering Instance */
  3093. +// {0x1158, 3, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MC_VALID Access Request */
  3094. +// {0x1158, 2, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLCKMOD Port Lock Mode */
  3095. +// {0x1158, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLIMMOD MAC Address Learning Limitation Mode */
  3096. +// {0x1158, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MTFL MAC Table Flushing */
  3097. +// {0x115C, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_1 PCE Global Control Register1 */
  3098. +// {0x115C, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_1_PCE_DIS PCE Disable after currently processed packet */
  3099. +// {0x115C, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_1_LRNMOD MAC Address Learning Mode */
  3100. +// {0x1160, 0, 16, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL Three-color MarkerGlobal Control Register */
  3101. +// {0x1160, 6, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPRED Re-marking Drop Precedence Red Encoding */
  3102. +// {0x1160, 3, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPYEL Re-marking Drop Precedence Yellow Encoding */
  3103. +// {0x1160, 0, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPGRN Re-marking Drop Precedence Green Encoding */
  3104. +// {0x1164, 0, 16, 0x00}, /* XRX200_PCE_IGMP_CTRL IGMP Control Register */
  3105. +// {0x1164, 15, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FAGEEN Force Aging of Table Entries Enable */
  3106. +// {0x1164, 14, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FLEAVE Fast Leave Enable */
  3107. +// {0x1164, 13, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRTEN Default Maximum Response Time Enable */
  3108. +// {0x1164, 12, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_JASUP Join Aggregation Suppression Enable */
  3109. +// {0x1164, 11, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_REPSUP Report Suppression Enable */
  3110. +// {0x1164, 10, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_SRPEN Snooping of Router Port Enable */
  3111. +// {0x1164, 8, 2, 0x00}, /* XRX200_PCE_IGMP_CTRL_ROB Robustness Variable */
  3112. +// {0x1164, 0, 8, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRT IGMP Default Maximum Response Time */
  3113. +// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM IGMP Default RouterPort Map Register */
  3114. +// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM_DRPM IGMP Default Router Port Map */
  3115. +// {0x116C, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_0 IGMP Aging Register0 */
  3116. +// {0x116C, 3, 8, 0x00}, /* XRX200_PCE_IGMP_AGE_0_MANT IGMP Group Aging Time Mantissa */
  3117. +// {0x116C, 0, 3, 0x00}, /* XRX200_PCE_IGMP_AGE_0_EXP IGMP Group Aging Time Exponent */
  3118. +// {0x1170, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_1 IGMP Aging Register1 */
  3119. +// {0x1170, 0, 12, 0x00}, /* XRX200_PCE_IGMP_AGE_1_MANT IGMP Router Port Aging Time Mantissa */
  3120. +// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT IGMP Status Register */
  3121. +// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT_IGPM IGMP Port Map */
  3122. +// {0x1178, 0, 16, 0x00}, /* XRX200_WOL_GLB_CTRL Wake-on-LAN ControlRegister */
  3123. +// {0x1178, 0, 1, 0x00}, /* XRX200_WOL_GLB_CTRL_PASSEN WoL Password Enable */
  3124. +// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0 Wake-on-LAN DestinationAddress Register 0 */
  3125. +// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0_DA0 WoL Destination Address [15:0] */
  3126. +// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1 Wake-on-LAN DestinationAddress Register 1 */
  3127. +// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1_DA1 WoL Destination Address [31:16] */
  3128. +// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2 Wake-on-LAN DestinationAddress Register 2 */
  3129. +// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2_DA2 WoL Destination Address [47:32] */
  3130. +// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0 Wake-on-LAN Password Register0 */
  3131. +// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0_PW0 WoL Password [15:0] */
  3132. +// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1 Wake-on-LAN Password Register1 */
  3133. +// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1_PW1 WoL Password [31:16] */
  3134. +// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2 Wake-on-LAN Password Register2 */
  3135. +// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2_PW2 WoL Password [47:32] */
  3136. +// {0x1194, 0, 16, 0x00}, /* XRX200_PCE_IER_0_PINT Parser and ClassificationEngine Global Interrupt Enable Register 0 */
  3137. +// {0x1194, 15, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_15 Port Interrupt Enable */
  3138. +// {0x1194, 14, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_14 Port Interrupt Enable */
  3139. +// {0x1194, 13, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_13 Port Interrupt Enable */
  3140. +// {0x1194, 12, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_12 Port Interrupt Enable */
  3141. +// {0x1194, 11, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_11 Port Interrupt Enable */
  3142. +// {0x1194, 10, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_10 Port Interrupt Enable */
  3143. +// {0x1194, 9, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_9 Port Interrupt Enable */
  3144. +// {0x1194, 8, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_8 Port Interrupt Enable */
  3145. +// {0x1194, 7, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_7 Port Interrupt Enable */
  3146. +// {0x1194, 6, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_6 Port Interrupt Enable */
  3147. +// {0x1194, 5, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_5 Port Interrupt Enable */
  3148. +// {0x1194, 4, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_4 Port Interrupt Enable */
  3149. +// {0x1194, 3, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_3 Port Interrupt Enable */
  3150. +// {0x1194, 2, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_2 Port Interrupt Enable */
  3151. +// {0x1194, 1, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_1 Port Interrupt Enable */
  3152. +// {0x1194, 0, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_0 Port Interrupt Enable */
  3153. +// {0x1198, 0, 16, 0x00}, /* XRX200_PCE_IER_1 Parser and ClassificationEngine Global Interrupt Enable Register 1 */
  3154. +// {0x1198, 6, 1, 0x00}, /* XRX200_PCE_IER_1_FLOWINT Traffic Flow Table Interrupt Rule matched Interrupt Enable */
  3155. +// {0x1198, 5, 1, 0x00}, /* XRX200_PCE_IER_1_CPH2 Classification Phase 2 Ready Interrupt Enable */
  3156. +// {0x1198, 4, 1, 0x00}, /* XRX200_PCE_IER_1_CPH1 Classification Phase 1 Ready Interrupt Enable */
  3157. +// {0x1198, 3, 1, 0x00}, /* XRX200_PCE_IER_1_CPH0 Classification Phase 0 Ready Interrupt Enable */
  3158. +// {0x1198, 2, 1, 0x00}, /* XRX200_PCE_IER_1_PRDY Parser Ready Interrupt Enable */
  3159. +// {0x1198, 1, 1, 0x00}, /* XRX200_PCE_IER_1_IGTF IGMP Table Full Interrupt Enable */
  3160. +// {0x1198, 0, 1, 0x00}, /* XRX200_PCE_IER_1_MTF MAC Table Full Interrupt Enable */
  3161. +// {0x119C, 0, 16, 0x00}, /* XRX200_PCE_ISR_0_PINT Parser and ClassificationEngine Global Interrupt Status Register 0 */
  3162. +// {0x119C, 15, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_15 Port Interrupt */
  3163. +// {0x119C, 14, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_14 Port Interrupt */
  3164. +// {0x119C, 13, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_13 Port Interrupt */
  3165. +// {0x119C, 12, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_12 Port Interrupt */
  3166. +// {0x119C, 11, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_11 Port Interrupt */
  3167. +// {0x119C, 10, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_10 Port Interrupt */
  3168. +// {0x119C, 9, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_9 Port Interrupt */
  3169. +// {0x119C, 8, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_8 Port Interrupt */
  3170. +// {0x119C, 7, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_7 Port Interrupt */
  3171. +// {0x119C, 6, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_6 Port Interrupt */
  3172. +// {0x119C, 5, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_5 Port Interrupt */
  3173. +// {0x119C, 4, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_4 Port Interrupt */
  3174. +// {0x119C, 3, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_3 Port Interrupt */
  3175. +// {0x119C, 2, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_2 Port Interrupt */
  3176. +// {0x119C, 1, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_1 Port Interrupt */
  3177. +// {0x119C, 0, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_0 Port Interrupt */
  3178. +// {0x11A0, 0, 16, 0x00}, /* XRX200_PCE_ISR_1 Parser and ClassificationEngine Global Interrupt Status Register 1 */
  3179. +// {0x11A0, 6, 1, 0x00}, /* XRX200_PCE_ISR_1_FLOWINT Traffic Flow Table Interrupt Rule matched */
  3180. +// {0x11A0, 5, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH2 Classification Phase 2 Ready Interrupt */
  3181. +// {0x11A0, 4, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH1 Classification Phase 1 Ready Interrupt */
  3182. +// {0x11A0, 3, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH0 Classification Phase 0 Ready Interrupt */
  3183. +// {0x11A0, 2, 1, 0x00}, /* XRX200_PCE_ISR_1_PRDY Parser Ready Interrupt */
  3184. +// {0x11A0, 1, 1, 0x00}, /* XRX200_PCE_ISR_1_IGTF IGMP Table Full Interrupt */
  3185. +// {0x11A0, 0, 1, 0x00}, /* XRX200_PCE_ISR_1_MTF MAC Table Full Interrupt */
  3186. +// {0x11A4, 0, 16, 0x00}, /* XRX200_PARSER_STAT_FIFO Parser Status Register */
  3187. +// {0x11A4, 8, 8, 0x00}, /* XRX200_PARSER_STAT_FSM_DAT_CNT Parser FSM Data Counter */
  3188. +// {0x11A4, 5, 3, 0x00}, /* XRX200_PARSER_STAT_FSM_STATE Parser FSM State */
  3189. +// {0x11A4, 4, 1, 0x00}, /* XRX200_PARSER_STAT_PKT_ERR Packet error detected */
  3190. +// {0x11A4, 3, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_FIN Parser FSM finished */
  3191. +// {0x11A4, 2, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_START Parser FSM start */
  3192. +// {0x11A4, 1, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_RDY Parser FIFO ready for read. */
  3193. +// {0x11A4, 0, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_FULL Parser */
  3194. +// {0x1200, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_0 PCE Port ControlRegister 0 */
  3195. +// {0x1200, 13, 1, 0x28}, /* XRX200_PCE_PCTRL_0_MCST Multicast Forwarding Mode Selection */
  3196. +// {0x1200, 12, 1, 0x28}, /* XRX200_PCE_PCTRL_0_EGSTEN Table-based Egress Special Tag Enable */
  3197. +// {0x1200, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_0_IGSTEN Ingress Special Tag Enable */
  3198. +// {0x1200, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PCPEN PCP Remarking Mode */
  3199. +// {0x1200, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CLPEN Class Remarking Mode */
  3200. +// {0x1200, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_0_DPEN Drop Precedence Remarking Mode */
  3201. +// {0x1200, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CMOD Three-color Marker Color Mode */
  3202. +// {0x1200, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_0_VREP VLAN Replacement Mode */
  3203. + {0x1200, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_0_TVM Transparent VLAN Mode */
  3204. +// {0x1200, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PLOCK Port Locking Enable */
  3205. +// {0x1200, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_0_AGEDIS Aging Disable */
  3206. +// {0x1200, 0, 3, 0x28}, /* XRX200_PCE_PCTRL_0_PSTATE Port State */
  3207. +// {0x1204, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_1 PCE Port ControlRegister 1 */
  3208. +// {0x1204, 0, 8, 0x28}, /* XRX200_PCE_PCTRL_1_LRNLIM MAC Address Learning Limit */
  3209. +// {0x1208, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_2 PCE Port ControlRegister 2 */
  3210. +// {0x1208, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_2_DSCPMOD DSCP Mode Selection */
  3211. +// {0x1208, 5, 2, 0x28}, /* XRX200_PCE_PCTRL_2_DSCP Enable DSCP to select the Class of Service */
  3212. +// {0x1208, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_2_PCP Enable VLAN PCP to select the Class of Service */
  3213. +// {0x1208, 0, 4, 0x28}, /* XRX200_PCE_PCTRL_2_PCLASS Port-based Traffic Class */
  3214. +// {0x120C, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_3_VIO PCE Port ControlRegister 3 */
  3215. +// {0x120C, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_3_EDIR Egress Redirection Mode */
  3216. +// {0x120C, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXDMIR Receive Mirroring Enable for dropped frames */
  3217. +// {0x120C, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXVMIR Receive Mirroring Enable for valid frames */
  3218. +// {0x120C, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_3_TXMIR Transmit Mirroring Enable */
  3219. +// {0x120C, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_7 Violation Type 7 Mirroring Enable */
  3220. +// {0x120C, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_6 Violation Type 6 Mirroring Enable */
  3221. +// {0x120C, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_5 Violation Type 5 Mirroring Enable */
  3222. +// {0x120C, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_4 Violation Type 4 Mirroring Enable */
  3223. +// {0x120C, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_3 Violation Type 3 Mirroring Enable */
  3224. +// {0x120C, 2, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_2 Violation Type 2 Mirroring Enable */
  3225. +// {0x120C, 1, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_1 Violation Type 1 Mirroring Enable */
  3226. +// {0x120C, 0, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_0 Violation Type 0 Mirroring Enable */
  3227. +// {0x1210, 0, 16, 0x28}, /* XRX200_WOL_CTRL Wake-on-LAN ControlRegister */
  3228. +// {0x1210, 0, 1, 0x28}, /* XRX200_WOL_CTRL_PORT WoL Enable */
  3229. +// {0x1214, 0, 16, 0x28}, /* XRX200_PCE_VCTRL PCE VLAN ControlRegister */
  3230. + {0x1214, 5, 1, 0x28}, /* XRX200_PCE_VCTRL_VSR VLAN Security Rule */
  3231. + {0x1214, 4, 1, 0x28}, /* XRX200_PCE_VCTRL_VEMR VLAN Egress Member Violation Rule */
  3232. + {0x1214, 3, 1, 0x28}, /* XRX200_PCE_VCTRL_VIMR VLAN Ingress Member Violation Rule */
  3233. + {0x1214, 1, 2, 0x28}, /* XRX200_PCE_VCTRL_VINR VLAN Ingress Tag Rule */
  3234. + {0x1214, 0, 1, 0x28}, /* XRX200_PCE_VCTRL_UVR Unknown VLAN Rule */
  3235. +// {0x1218, 0, 16, 0x28}, /* XRX200_PCE_DEFPVID PCE Default PortVID Register */
  3236. + {0x1218, 0, 6, 0x28}, /* XRX200_PCE_DEFPVID_PVID Default Port VID Index */
  3237. +// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT PCE Port StatusRegister */
  3238. +// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT_LRNCNT Learning Count */
  3239. +// {0x1220, 0, 16, 0x28}, /* XRX200_PCE_PIER Parser and ClassificationEngine Port Interrupt Enable Register */
  3240. +// {0x1220, 5, 1, 0x28}, /* XRX200_PCE_PIER_CLDRP Classification Drop Interrupt Enable */
  3241. +// {0x1220, 4, 1, 0x28}, /* XRX200_PCE_PIER_PTDRP Port Drop Interrupt Enable */
  3242. +// {0x1220, 3, 1, 0x28}, /* XRX200_PCE_PIER_VLAN VLAN Violation Interrupt Enable */
  3243. +// {0x1220, 2, 1, 0x28}, /* XRX200_PCE_PIER_WOL Wake-on-LAN Interrupt Enable */
  3244. +// {0x1220, 1, 1, 0x28}, /* XRX200_PCE_PIER_LOCK Port Limit Alert Interrupt Enable */
  3245. +// {0x1220, 0, 1, 0x28}, /* XRX200_PCE_PIER_LIM Port Lock Alert Interrupt Enable */
  3246. +// {0x1224, 0, 16, 0x28}, /* XRX200_PCE_PISR Parser and ClassificationEngine Port Interrupt Status Register */
  3247. +// {0x1224, 5, 1, 0x28}, /* XRX200_PCE_PISR_CLDRP Classification Drop Interrupt */
  3248. +// {0x1224, 4, 1, 0x28}, /* XRX200_PCE_PISR_PTDRP Port Drop Interrupt */
  3249. +// {0x1224, 3, 1, 0x28}, /* XRX200_PCE_PISR_VLAN VLAN Violation Interrupt */
  3250. +// {0x1224, 2, 1, 0x28}, /* XRX200_PCE_PISR_WOL Wake-on-LAN Interrupt */
  3251. +// {0x1224, 1, 1, 0x28}, /* XRX200_PCE_PISR_LOCK Port Lock Alert Interrupt */
  3252. +// {0x1224, 0, 1, 0x28}, /* XRX200_PCE_PISR_LIMIT Port Limitation Alert Interrupt */
  3253. +// {0x1600, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CTRL Three-colorMarker Control Register */
  3254. +// {0x1600, 0, 1, 0x1c}, /* XRX200_PCE_TCM_CTRL_TCMEN Three-color Marker metering instance enable */
  3255. +// {0x1604, 0, 16, 0x1c}, /* XRX200_PCE_TCM_STAT Three-colorMarker Status Register */
  3256. +// {0x1604, 1, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL1 Three-color Marker Alert 1 Status */
  3257. +// {0x1604, 0, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL0 Three-color Marker Alert 0 Status */
  3258. +// {0x1608, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CBS Three-color MarkerCommitted Burst Size Register */
  3259. +// {0x1608, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CBS_CBS Committed Burst Size */
  3260. +// {0x160C, 0, 16, 0x1c}, /* XRX200_PCE_TCM_EBS Three-color MarkerExcess Burst Size Register */
  3261. +// {0x160C, 0, 10, 0x1c}, /* XRX200_PCE_TCM_EBS_EBS Excess Burst Size */
  3262. +// {0x1610, 0, 16, 0x1c}, /* XRX200_PCE_TCM_IBS Three-color MarkerInstantaneous Burst Size Register */
  3263. +// {0x1610, 0, 2, 0x1c}, /* XRX200_PCE_TCM_IBS_IBS Instantaneous Burst Size */
  3264. +// {0x1614, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT Three-colorMarker Constant Information Rate Mantissa Register */
  3265. +// {0x1614, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT_MANT Rate Counter Mantissa */
  3266. +// {0x1618, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP Three-colorMarker Constant Information Rate Exponent Register */
  3267. +// {0x1618, 0, 4, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP_EXP Rate Counter Exponent */
  3268. +// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST MAC Test Register */
  3269. +// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST_JTP Jitter Test Pattern */
  3270. +// {0x2304, 0, 16, 0x00}, /* XRX200_MAC_PFAD_CFG MAC Pause FrameSource Address Configuration Register */
  3271. +// {0x2304, 0, 1, 0x00}, /* XRX200_MAC_PFAD_CFG_SAMOD Source Address Mode */
  3272. +// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0 Pause Frame SourceAddress Part 0 */
  3273. +// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0_PFAD Pause Frame Source Address Part 0 */
  3274. +// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1 Pause Frame SourceAddress Part 1 */
  3275. +// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1_PFAD Pause Frame Source Address Part 1 */
  3276. +// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2 Pause Frame SourceAddress Part 2 */
  3277. +// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2_PFAD Pause Frame Source Address Part 2 */
  3278. +// {0x2314, 0, 16, 0x00}, /* XRX200_MAC_FLEN MAC Frame Length Register */
  3279. +// {0x2314, 0, 14, 0x00}, /* XRX200_MAC_FLEN_LEN Maximum Frame Length */
  3280. +// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0 MAC VLAN EthertypeRegister 0 */
  3281. +// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0_OUTER Ethertype */
  3282. +// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1 MAC VLAN EthertypeRegister 1 */
  3283. +// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1_INNER Ethertype */
  3284. +// {0x2320, 0, 16, 0x00}, /* XRX200_MAC_IER MAC Interrupt EnableRegister */
  3285. +// {0x2320, 0, 8, 0x00}, /* XRX200_MAC_IER_MACIEN MAC Interrupt Enable */
  3286. +// {0x2324, 0, 16, 0x00}, /* XRX200_MAC_ISR MAC Interrupt StatusRegister */
  3287. +// {0x2324, 0, 8, 0x00}, /* XRX200_MAC_ISR_MACINT MAC Interrupt */
  3288. +// {0x2400, 0, 16, 0x30}, /* XRX200_MAC_PSTAT MAC Port Status Register */
  3289. +// {0x2400, 11, 1, 0x30}, /* XRX200_MAC_PSTAT_PACT PHY Active Status */
  3290. + {0x2400, 10, 1, 0x30}, /* XRX200_MAC_PSTAT_GBIT Gigabit Speed Status */
  3291. + {0x2400, 9, 1, 0x30}, /* XRX200_MAC_PSTAT_MBIT Megabit Speed Status */
  3292. + {0x2400, 8, 1, 0x30}, /* XRX200_MAC_PSTAT_FDUP Full Duplex Status */
  3293. +// {0x2400, 7, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAU Receive Pause Status */
  3294. +// {0x2400, 6, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAU Transmit Pause Status */
  3295. +// {0x2400, 5, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAUEN Receive Pause Enable Status */
  3296. +// {0x2400, 4, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAUEN Transmit Pause Enable Status */
  3297. + {0x2400, 3, 1, 0x30}, /* XRX200_MAC_PSTAT_LSTAT Link Status */
  3298. +// {0x2400, 2, 1, 0x30}, /* XRX200_MAC_PSTAT_CRS Carrier Sense Status */
  3299. +// {0x2400, 1, 1, 0x30}, /* XRX200_MAC_PSTAT_TXLPI Transmit Low-power Idle Status */
  3300. +// {0x2400, 0, 1, 0x30}, /* XRX200_MAC_PSTAT_RXLPI Receive Low-power Idle Status */
  3301. +// {0x2404, 0, 16, 0x30}, /* XRX200_MAC_PISR MAC Interrupt Status Register */
  3302. +// {0x2404, 13, 1, 0x30}, /* XRX200_MAC_PISR_PACT PHY Active Status */
  3303. +// {0x2404, 12, 1, 0x30}, /* XRX200_MAC_PISR_SPEED Megabit Speed Status */
  3304. +// {0x2404, 11, 1, 0x30}, /* XRX200_MAC_PISR_FDUP Full Duplex Status */
  3305. +// {0x2404, 10, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUEN Receive Pause Enable Status */
  3306. +// {0x2404, 9, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUEN Transmit Pause Enable Status */
  3307. +// {0x2404, 8, 1, 0x30}, /* XRX200_MAC_PISR_LPIOFF Receive Low-power Idle Mode is left */
  3308. +// {0x2404, 7, 1, 0x30}, /* XRX200_MAC_PISR_LPION Receive Low-power Idle Mode is entered */
  3309. +// {0x2404, 6, 1, 0x30}, /* XRX200_MAC_PISR_JAM Jam Status Detected */
  3310. +// {0x2404, 5, 1, 0x30}, /* XRX200_MAC_PISR_TOOSHORT Too Short Frame Error Detected */
  3311. +// {0x2404, 4, 1, 0x30}, /* XRX200_MAC_PISR_TOOLONG Too Long Frame Error Detected */
  3312. +// {0x2404, 3, 1, 0x30}, /* XRX200_MAC_PISR_LENERR Length Mismatch Error Detected */
  3313. +// {0x2404, 2, 1, 0x30}, /* XRX200_MAC_PISR_FCSERR Frame Checksum Error Detected */
  3314. +// {0x2404, 1, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUSE Pause Frame Transmitted */
  3315. +// {0x2404, 0, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUSE Pause Frame Received */
  3316. +// {0x2408, 0, 16, 0x30}, /* XRX200_MAC_PIER MAC Interrupt Enable Register */
  3317. +// {0x2408, 13, 1, 0x30}, /* XRX200_MAC_PIER_PACT PHY Active Status */
  3318. +// {0x2408, 12, 1, 0x30}, /* XRX200_MAC_PIER_SPEED Megabit Speed Status */
  3319. +// {0x2408, 11, 1, 0x30}, /* XRX200_MAC_PIER_FDUP Full Duplex Status */
  3320. +// {0x2408, 10, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUEN Receive Pause Enable Status */
  3321. +// {0x2408, 9, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUEN Transmit Pause Enable Status */
  3322. +// {0x2408, 8, 1, 0x30}, /* XRX200_MAC_PIER_LPIOFF Low-power Idle Off Interrupt Mask */
  3323. +// {0x2408, 7, 1, 0x30}, /* XRX200_MAC_PIER_LPION Low-power Idle On Interrupt Mask */
  3324. +// {0x2408, 6, 1, 0x30}, /* XRX200_MAC_PIER_JAM Jam Status Interrupt Mask */
  3325. +// {0x2408, 5, 1, 0x30}, /* XRX200_MAC_PIER_TOOSHORT Too Short Frame Error Interrupt Mask */
  3326. +// {0x2408, 4, 1, 0x30}, /* XRX200_MAC_PIER_TOOLONG Too Long Frame Error Interrupt Mask */
  3327. +// {0x2408, 3, 1, 0x30}, /* XRX200_MAC_PIER_LENERR Length Mismatch Error Interrupt Mask */
  3328. +// {0x2408, 2, 1, 0x30}, /* XRX200_MAC_PIER_FCSERR Frame Checksum Error Interrupt Mask */
  3329. +// {0x2408, 1, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUSE Transmit Pause Frame Interrupt Mask */
  3330. +// {0x2408, 0, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUSE Receive Pause Frame Interrupt Mask */
  3331. +// {0x240C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_0 MAC Control Register0 */
  3332. +// {0x240C, 13, 2, 0x30}, /* XRX200_MAC_CTRL_0_LCOL Late Collision Control */
  3333. +// {0x240C, 12, 1, 0x30}, /* XRX200_MAC_CTRL_0_BM Burst Mode Control */
  3334. +// {0x240C, 11, 1, 0x30}, /* XRX200_MAC_CTRL_0_APADEN Automatic VLAN Padding Enable */
  3335. +// {0x240C, 10, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPAD2EN Stacked VLAN Padding Enable */
  3336. +// {0x240C, 9, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPADEN VLAN Padding Enable */
  3337. +// {0x240C, 8, 1, 0x30}, /* XRX200_MAC_CTRL_0_PADEN Padding Enable */
  3338. +// {0x240C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_0_FCS Transmit FCS Control */
  3339. + {0x240C, 4, 3, 0x30}, /* XRX200_MAC_CTRL_0_FCON Flow Control Mode */
  3340. +// {0x240C, 2, 2, 0x30}, /* XRX200_MAC_CTRL_0_FDUP Full Duplex Control */
  3341. +// {0x240C, 0, 2, 0x30}, /* XRX200_MAC_CTRL_0_GMII GMII/MII interface mode selection */
  3342. +// {0x2410, 0, 16, 0x30}, /* XRX200_MAC_CTRL_1 MAC Control Register1 */
  3343. +// {0x2410, 8, 1, 0x30}, /* XRX200_MAC_CTRL_1_SHORTPRE Short Preamble Control */
  3344. +// {0x2410, 0, 4, 0x30}, /* XRX200_MAC_CTRL_1_IPG Minimum Inter Packet Gap Size */
  3345. +// {0x2414, 0, 16, 0x30}, /* XRX200_MAC_CTRL_2 MAC Control Register2 */
  3346. +// {0x2414, 3, 1, 0x30}, /* XRX200_MAC_CTRL_2_MLEN Maximum Untagged Frame Length */
  3347. +// {0x2414, 2, 1, 0x30}, /* XRX200_MAC_CTRL_2_LCHKL Frame Length Check Long Enable */
  3348. +// {0x2414, 0, 2, 0x30}, /* XRX200_MAC_CTRL_2_LCHKS Frame Length Check Short Enable */
  3349. +// {0x2418, 0, 16, 0x30}, /* XRX200_MAC_CTRL_3 MAC Control Register3 */
  3350. +// {0x2418, 0, 4, 0x30}, /* XRX200_MAC_CTRL_3_RCNT Retry Count */
  3351. +// {0x241C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_4 MAC Control Register4 */
  3352. +// {0x241C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_4_LPIEN LPI Mode Enable */
  3353. +// {0x241C, 0, 7, 0x30}, /* XRX200_MAC_CTRL_4_WAIT LPI Wait Time */
  3354. +// {0x2420, 0, 16, 0x30}, /* XRX200_MAC_CTRL_5_PJPS MAC Control Register5 */
  3355. +// {0x2420, 1, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_NOBP Prolonged Jam pattern size during no-backpressure state */
  3356. +// {0x2420, 0, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_BP Prolonged Jam pattern size during backpressure state */
  3357. +// {0x2424, 0, 16, 0x30}, /* XRX200_MAC_CTRL_6_XBUF Transmit and ReceiveBuffer Control Register */
  3358. +// {0x2424, 9, 3, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_DLY_WP Delay */
  3359. +// {0x2424, 8, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_INIT Receive Buffer Initialization */
  3360. +// {0x2424, 6, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_BYPASS Bypass the Receive Buffer */
  3361. +// {0x2424, 3, 3, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_DLY_WP Delay */
  3362. +// {0x2424, 2, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_INIT Initialize the Transmit Buffer */
  3363. +// {0x2424, 0, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_BYPASS Bypass the Transmit Buffer */
  3364. +// {0x2428, 0, 16, 0x30}, /* XRX200_MAC_BUFST_XBUF MAC Receive and TransmitBuffer Status Register */
  3365. +// {0x2428, 3, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_UFL Receive Buffer Underflow Indicator */
  3366. +// {0x2428, 2, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_OFL Receive Buffer Overflow Indicator */
  3367. +// {0x2428, 1, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_UFL Transmit Buffer Underflow Indicator */
  3368. +// {0x2428, 0, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_OFL Transmit Buffer Overflow Indicator */
  3369. +// {0x242C, 0, 16, 0x30}, /* XRX200_MAC_TESTEN MAC Test Enable Register */
  3370. +// {0x242C, 2, 1, 0x30}, /* XRX200_MAC_TESTEN_JTEN Jitter Test Enable */
  3371. +// {0x242C, 1, 1, 0x30}, /* XRX200_MAC_TESTEN_TXER Transmit Error Insertion */
  3372. +// {0x242C, 0, 1, 0x30}, /* XRX200_MAC_TESTEN_LOOP MAC Loopback Enable */
  3373. +// {0x2900, 0, 16, 0x00}, /* XRX200_FDMA_CTRL Ethernet Switch FetchDMA Control Register */
  3374. +// {0x2900, 7, 5, 0x00}, /* XRX200_FDMA_CTRL_LPI_THRESHOLD Low Power Idle Threshold */
  3375. +// {0x2900, 4, 3, 0x00}, /* XRX200_FDMA_CTRL_LPI_MODE Low Power Idle Mode */
  3376. +// {0x2900, 2, 2, 0x00}, /* XRX200_FDMA_CTRL_EGSTAG Egress Special Tag Size */
  3377. +// {0x2900, 1, 1, 0x00}, /* XRX200_FDMA_CTRL_IGSTAG Ingress Special Tag Size */
  3378. +// {0x2900, 0, 1, 0x00}, /* XRX200_FDMA_CTRL_EXCOL Excessive Collision Handling */
  3379. +// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE Special Tag EthertypeControl Register */
  3380. +// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE_ETYPE Special Tag Ethertype */
  3381. +// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE VLAN Tag EthertypeControl Register */
  3382. +// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE_ETYPE VLAN Tag Ethertype */
  3383. +// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0 FDMA Status Register0 */
  3384. +// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0_FSMS FSM states status */
  3385. +// {0x2910, 0, 16, 0x00}, /* XRX200_FDMA_IER Fetch DMA Global InterruptEnable Register */
  3386. +// {0x2910, 14, 1, 0x00}, /* XRX200_FDMA_IER_PCKD Packet Drop Interrupt Enable */
  3387. +// {0x2910, 13, 1, 0x00}, /* XRX200_FDMA_IER_PCKR Packet Ready Interrupt Enable */
  3388. +// {0x2910, 0, 8, 0x00}, /* XRX200_FDMA_IER_PCKT Packet Sent Interrupt Enable */
  3389. +// {0x2914, 0, 16, 0x00}, /* XRX200_FDMA_ISR Fetch DMA Global InterruptStatus Register */
  3390. +// {0x2914, 14, 1, 0x00}, /* XRX200_FDMA_ISR_PCKTD Packet Drop */
  3391. +// {0x2914, 13, 1, 0x00}, /* XRX200_FDMA_ISR_PCKR Packet is Ready for Transmission */
  3392. +// {0x2914, 0, 8, 0x00}, /* XRX200_FDMA_ISR_PCKT Packet Sent Event */
  3393. +// {0x2A00, 0, 16, 0x18}, /* XRX200_FDMA_PCTRL Ethernet SwitchFetch DMA Port Control Register */
  3394. +// {0x2A00, 3, 2, 0x18}, /* XRX200_FDMA_PCTRL_VLANMOD VLAN Modification Enable */
  3395. +// {0x2A00, 2, 1, 0x18}, /* XRX200_FDMA_PCTRL_DSCPRM DSCP Re-marking Enable */
  3396. +// {0x2A00, 1, 1, 0x18}, /* XRX200_FDMA_PCTRL_STEN Special Tag Insertion Enable */
  3397. +// {0x2A00, 0, 1, 0x18}, /* XRX200_FDMA_PCTRL_EN FDMA Port Enable */
  3398. +// {0x2A04, 0, 16, 0x18}, /* XRX200_FDMA_PRIO Ethernet SwitchFetch DMA Port Priority Register */
  3399. +// {0x2A04, 0, 2, 0x18}, /* XRX200_FDMA_PRIO_PRIO FDMA PRIO */
  3400. +// {0x2A08, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT0 Ethernet SwitchFetch DMA Port Status Register 0 */
  3401. +// {0x2A08, 15, 1, 0x18}, /* XRX200_FDMA_PSTAT0_PKT_AVAIL Port Egress Packet Available */
  3402. +// {0x2A08, 14, 1, 0x18}, /* XRX200_FDMA_PSTAT0_POK Port Status OK */
  3403. +// {0x2A08, 0, 6, 0x18}, /* XRX200_FDMA_PSTAT0_PSEG Port Egress Segment Count */
  3404. +// {0x2A0C, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT1_HDR Ethernet SwitchFetch DMA Port Status Register 1 */
  3405. +// {0x2A0C, 0, 10, 0x18}, /* XRX200_FDMA_PSTAT1_HDR_PTR Header Pointer */
  3406. +// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0 Egress TimeStamp Register 0 */
  3407. +// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0_TSTL Time Stamp [15:0] */
  3408. +// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1 Egress TimeStamp Register 1 */
  3409. +// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1_TSTH Time Stamp [31:16] */
  3410. +// {0x2D00, 0, 16, 0x00}, /* XRX200_SDMA_CTRL Ethernet Switch StoreDMA Control Register */
  3411. +// {0x2D00, 0, 1, 0x00}, /* XRX200_SDMA_CTRL_TSTEN Time Stamp Enable */
  3412. +// {0x2D04, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR1 SDMA Flow Control Threshold1 Register */
  3413. +// {0x2D04, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR1_THR1 Threshold 1 */
  3414. +// {0x2D08, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR2 SDMA Flow Control Threshold2 Register */
  3415. +// {0x2D08, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR2_THR2 Threshold 2 */
  3416. +// {0x2D0C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR3 SDMA Flow Control Threshold3 Register */
  3417. +// {0x2D0C, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR3_THR3 Threshold 3 */
  3418. +// {0x2D10, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR4 SDMA Flow Control Threshold4 Register */
  3419. +// {0x2D10, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR4_THR4 Threshold 4 */
  3420. +// {0x2D14, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR5 SDMA Flow Control Threshold5 Register */
  3421. +// {0x2D14, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR5_THR5 Threshold 5 */
  3422. +// {0x2D18, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR6 SDMA Flow Control Threshold6 Register */
  3423. +// {0x2D18, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR6_THR6 Threshold 6 */
  3424. +// {0x2D1C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR7 SDMA Flow Control Threshold7 Register */
  3425. +// {0x2D1C, 0, 11, 0x00}, /* XRX200_SDMA_FCTHR7_THR7 Threshold 7 */
  3426. +// {0x2D20, 0, 16, 0x00}, /* XRX200_SDMA_STAT_0 SDMA Status Register0 */
  3427. +// {0x2D20, 4, 3, 0x00}, /* XRX200_SDMA_STAT_0_BPS_FILL Back Pressure Status */
  3428. +// {0x2D20, 2, 2, 0x00}, /* XRX200_SDMA_STAT_0_BPS_PNT Back Pressure Status */
  3429. +// {0x2D20, 0, 2, 0x00}, /* XRX200_SDMA_STAT_0_DROP Back Pressure Status */
  3430. +// {0x2D24, 0, 16, 0x00}, /* XRX200_SDMA_STAT_1 SDMA Status Register1 */
  3431. +// {0x2D24, 0, 10, 0x00}, /* XRX200_SDMA_STAT_1_FILL Buffer Filling Level */
  3432. +// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2 SDMA Status Register2 */
  3433. +// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2_FSMS FSM states status */
  3434. +// {0x2D2C, 0, 16, 0x00}, /* XRX200_SDMA_IER SDMA Interrupt Enable Register */
  3435. +// {0x2D2C, 15, 1, 0x00}, /* XRX200_SDMA_IER_BPEX Buffer Pointers Exceeded */
  3436. +// {0x2D2C, 14, 1, 0x00}, /* XRX200_SDMA_IER_BFULL Buffer Full */
  3437. +// {0x2D2C, 13, 1, 0x00}, /* XRX200_SDMA_IER_FERR Frame Error */
  3438. +// {0x2D2C, 0, 8, 0x00}, /* XRX200_SDMA_IER_FRX Frame Received Successfully */
  3439. +// {0x2D30, 0, 16, 0x00}, /* XRX200_SDMA_ISR SDMA Interrupt Status Register */
  3440. +// {0x2D30, 15, 1, 0x00}, /* XRX200_SDMA_ISR_BPEX Packet Descriptors Exceeded */
  3441. +// {0x2D30, 14, 1, 0x00}, /* XRX200_SDMA_ISR_BFULL Buffer Full */
  3442. +// {0x2D30, 13, 1, 0x00}, /* XRX200_SDMA_ISR_FERR Frame Error */
  3443. +// {0x2D30, 0, 8, 0x00}, /* XRX200_SDMA_ISR_FRX Frame Received Successfully */
  3444. +// {0x2F00, 0, 16, 0x18}, /* XRX200_SDMA_PCTRL Ethernet SwitchStore DMA Port Control Register */
  3445. +// {0x2F00, 13, 2, 0x18}, /* XRX200_SDMA_PCTRL_DTHR Drop Threshold Selection */
  3446. +// {0x2F00, 11, 2, 0x18}, /* XRX200_SDMA_PCTRL_PTHR Pause Threshold Selection */
  3447. +// {0x2F00, 10, 1, 0x18}, /* XRX200_SDMA_PCTRL_PHYEFWD Forward PHY Error Frames */
  3448. +// {0x2F00, 9, 1, 0x18}, /* XRX200_SDMA_PCTRL_ALGFWD Forward Alignment Error Frames */
  3449. +// {0x2F00, 8, 1, 0x18}, /* XRX200_SDMA_PCTRL_LENFWD Forward Length Errored Frames */
  3450. +// {0x2F00, 7, 1, 0x18}, /* XRX200_SDMA_PCTRL_OSFWD Forward Oversized Frames */
  3451. +// {0x2F00, 6, 1, 0x18}, /* XRX200_SDMA_PCTRL_USFWD Forward Undersized Frames */
  3452. +// {0x2F00, 5, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSIGN Ignore FCS Errors */
  3453. +// {0x2F00, 4, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSFWD Forward FCS Errored Frames */
  3454. +// {0x2F00, 3, 1, 0x18}, /* XRX200_SDMA_PCTRL_PAUFWD Pause Frame Forwarding */
  3455. +// {0x2F00, 2, 1, 0x18}, /* XRX200_SDMA_PCTRL_MFCEN Metering Flow Control Enable */
  3456. +// {0x2F00, 1, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCEN Flow Control Enable */
  3457. +// {0x2F00, 0, 1, 0x18}, /* XRX200_SDMA_PCTRL_PEN Port Enable */
  3458. +// {0x2F04, 0, 16, 0x18}, /* XRX200_SDMA_PRIO Ethernet SwitchStore DMA Port Priority Register */
  3459. +// {0x2F04, 0, 2, 0x18}, /* XRX200_SDMA_PRIO_PRIO SDMA PRIO */
  3460. +// {0x2F08, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT0_HDR Ethernet SwitchStore DMA Port Status Register 0 */
  3461. +// {0x2F08, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT0_HDR_PTR Port Ingress Queue Header Pointer */
  3462. +// {0x2F0C, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT1 Ethernet SwitchStore DMA Port Status Register 1 */
  3463. +// {0x2F0C, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT1_PPKT Port Ingress Packet Count */
  3464. +// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0 Ingress TimeStamp Register 0 */
  3465. +// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0_TSTL Time Stamp [15:0] */
  3466. +// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1 Ingress TimeStamp Register 1 */
  3467. +// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1_TSTH Time Stamp [31:16] */
  3468. +};
  3469. +
  3470. +