300-pending_work.patch 267 KB

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  1. --- a/drivers/net/wireless/ath/ath10k/mac.c
  2. +++ b/drivers/net/wireless/ath/ath10k/mac.c
  3. @@ -1351,12 +1351,12 @@ static int ath10k_update_channel_list(st
  4. ch->allow_vht = true;
  5. ch->allow_ibss =
  6. - !(channel->flags & IEEE80211_CHAN_NO_IBSS);
  7. + !(channel->flags & IEEE80211_CHAN_NO_IR);
  8. ch->ht40plus =
  9. !(channel->flags & IEEE80211_CHAN_NO_HT40PLUS);
  10. - passive = channel->flags & IEEE80211_CHAN_PASSIVE_SCAN;
  11. + passive = channel->flags & IEEE80211_CHAN_NO_IR;
  12. ch->passive = passive;
  13. ch->freq = channel->center_freq;
  14. --- a/drivers/net/wireless/ath/ath9k/Kconfig
  15. +++ b/drivers/net/wireless/ath/ath9k/Kconfig
  16. @@ -90,7 +90,7 @@ config ATH9K_DFS_CERTIFIED
  17. config ATH9K_TX99
  18. bool "Atheros ath9k TX99 testing support"
  19. - depends on CFG80211_CERTIFICATION_ONUS
  20. + depends on ATH9K_DEBUGFS && CFG80211_CERTIFICATION_ONUS
  21. default n
  22. ---help---
  23. Say N. This should only be enabled on systems undergoing
  24. @@ -108,6 +108,14 @@ config ATH9K_TX99
  25. be evaluated to meet the RF exposure limits set forth in the
  26. governmental SAR regulations.
  27. +config ATH9K_WOW
  28. + bool "Wake on Wireless LAN support (EXPERIMENTAL)"
  29. + depends on ATH9K && PM
  30. + default n
  31. + ---help---
  32. + This option enables Wake on Wireless LAN support for certain cards.
  33. + Currently, AR9462 is supported.
  34. +
  35. config ATH9K_LEGACY_RATE_CONTROL
  36. bool "Atheros ath9k rate control"
  37. depends on ATH9K
  38. --- a/drivers/net/wireless/ath/ath9k/Makefile
  39. +++ b/drivers/net/wireless/ath/ath9k/Makefile
  40. @@ -13,9 +13,9 @@ ath9k-$(CPTCFG_ATH9K_PCI) += pci.o
  41. ath9k-$(CPTCFG_ATH9K_AHB) += ahb.o
  42. ath9k-$(CPTCFG_ATH9K_DEBUGFS) += debug.o
  43. ath9k-$(CPTCFG_ATH9K_DFS_DEBUGFS) += dfs_debug.o
  44. -ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += \
  45. - dfs.o
  46. -ath9k-$(CONFIG_PM_SLEEP) += wow.o
  47. +ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += dfs.o
  48. +ath9k-$(CPTCFG_ATH9K_TX99) += tx99.o
  49. +ath9k-$(CPTCFG_ATH9K_WOW) += wow.o
  50. obj-$(CPTCFG_ATH9K) += ath9k.o
  51. @@ -41,6 +41,8 @@ ath9k_hw-y:= \
  52. ar9003_eeprom.o \
  53. ar9003_paprd.o
  54. +ath9k_hw-$(CPTCFG_ATH9K_WOW) += ar9003_wow.o
  55. +
  56. ath9k_hw-$(CPTCFG_ATH9K_BTCOEX_SUPPORT) += btcoex.o \
  57. ar9003_mci.o
  58. obj-$(CPTCFG_ATH9K_HW) += ath9k_hw.o
  59. --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
  60. +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
  61. @@ -26,6 +26,7 @@
  62. #include "ar9462_2p0_initvals.h"
  63. #include "ar9462_2p1_initvals.h"
  64. #include "ar9565_1p0_initvals.h"
  65. +#include "ar9565_1p1_initvals.h"
  66. /* General hardware code for the AR9003 hadware family */
  67. @@ -187,17 +188,17 @@ static void ar9003_hw_init_mode_regs(str
  68. INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
  69. ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
  70. - /* Load PCIE SERDES settings from INI */
  71. -
  72. - /* Awake Setting */
  73. -
  74. - INIT_INI_ARRAY(&ah->iniPcieSerdes,
  75. - ar9485_1_1_pcie_phy_clkreq_disable_L1);
  76. -
  77. - /* Sleep Setting */
  78. -
  79. - INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
  80. - ar9485_1_1_pcie_phy_clkreq_disable_L1);
  81. + if (ah->config.no_pll_pwrsave) {
  82. + INIT_INI_ARRAY(&ah->iniPcieSerdes,
  83. + ar9485_1_1_pcie_phy_clkreq_disable_L1);
  84. + INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
  85. + ar9485_1_1_pcie_phy_clkreq_disable_L1);
  86. + } else {
  87. + INIT_INI_ARRAY(&ah->iniPcieSerdes,
  88. + ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
  89. + INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
  90. + ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
  91. + }
  92. } else if (AR_SREV_9462_21(ah)) {
  93. INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  94. ar9462_2p1_mac_core);
  95. @@ -223,6 +224,10 @@ static void ar9003_hw_init_mode_regs(str
  96. ar9462_2p1_modes_fast_clock);
  97. INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
  98. ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
  99. + INIT_INI_ARRAY(&ah->iniPcieSerdes,
  100. + ar9462_2p1_pciephy_clkreq_disable_L1);
  101. + INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
  102. + ar9462_2p1_pciephy_clkreq_disable_L1);
  103. } else if (AR_SREV_9462_20(ah)) {
  104. INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
  105. @@ -247,18 +252,18 @@ static void ar9003_hw_init_mode_regs(str
  106. ar9462_2p0_soc_postamble);
  107. INIT_INI_ARRAY(&ah->iniModesRxGain,
  108. - ar9462_common_rx_gain_table_2p0);
  109. + ar9462_2p0_common_rx_gain);
  110. /* Awake -> Sleep Setting */
  111. INIT_INI_ARRAY(&ah->iniPcieSerdes,
  112. - ar9462_pciephy_clkreq_disable_L1_2p0);
  113. + ar9462_2p0_pciephy_clkreq_disable_L1);
  114. /* Sleep -> Awake Setting */
  115. INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
  116. - ar9462_pciephy_clkreq_disable_L1_2p0);
  117. + ar9462_2p0_pciephy_clkreq_disable_L1);
  118. /* Fast clock modal settings */
  119. INIT_INI_ARRAY(&ah->iniModesFastClock,
  120. - ar9462_modes_fast_clock_2p0);
  121. + ar9462_2p0_modes_fast_clock);
  122. INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
  123. ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
  124. @@ -331,6 +336,41 @@ static void ar9003_hw_init_mode_regs(str
  125. INIT_INI_ARRAY(&ah->iniModesFastClock,
  126. ar9580_1p0_modes_fast_clock);
  127. + } else if (AR_SREV_9565_11_OR_LATER(ah)) {
  128. + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  129. + ar9565_1p1_mac_core);
  130. + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
  131. + ar9565_1p1_mac_postamble);
  132. +
  133. + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
  134. + ar9565_1p1_baseband_core);
  135. + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
  136. + ar9565_1p1_baseband_postamble);
  137. +
  138. + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
  139. + ar9565_1p1_radio_core);
  140. + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
  141. + ar9565_1p1_radio_postamble);
  142. +
  143. + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
  144. + ar9565_1p1_soc_preamble);
  145. + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
  146. + ar9565_1p1_soc_postamble);
  147. +
  148. + INIT_INI_ARRAY(&ah->iniModesRxGain,
  149. + ar9565_1p1_Common_rx_gain_table);
  150. + INIT_INI_ARRAY(&ah->iniModesTxGain,
  151. + ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
  152. +
  153. + INIT_INI_ARRAY(&ah->iniPcieSerdes,
  154. + ar9565_1p1_pciephy_clkreq_disable_L1);
  155. + INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
  156. + ar9565_1p1_pciephy_clkreq_disable_L1);
  157. +
  158. + INIT_INI_ARRAY(&ah->iniModesFastClock,
  159. + ar9565_1p1_modes_fast_clock);
  160. + INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
  161. + ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
  162. } else if (AR_SREV_9565(ah)) {
  163. INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  164. ar9565_1p0_mac_core);
  165. @@ -440,7 +480,10 @@ static void ar9003_tx_gain_table_mode0(s
  166. ar9462_2p1_modes_low_ob_db_tx_gain);
  167. else if (AR_SREV_9462_20(ah))
  168. INIT_INI_ARRAY(&ah->iniModesTxGain,
  169. - ar9462_modes_low_ob_db_tx_gain_table_2p0);
  170. + ar9462_2p0_modes_low_ob_db_tx_gain);
  171. + else if (AR_SREV_9565_11(ah))
  172. + INIT_INI_ARRAY(&ah->iniModesTxGain,
  173. + ar9565_1p1_modes_low_ob_db_tx_gain_table);
  174. else if (AR_SREV_9565(ah))
  175. INIT_INI_ARRAY(&ah->iniModesTxGain,
  176. ar9565_1p0_modes_low_ob_db_tx_gain_table);
  177. @@ -474,7 +517,10 @@ static void ar9003_tx_gain_table_mode1(s
  178. ar9462_2p1_modes_high_ob_db_tx_gain);
  179. else if (AR_SREV_9462_20(ah))
  180. INIT_INI_ARRAY(&ah->iniModesTxGain,
  181. - ar9462_modes_high_ob_db_tx_gain_table_2p0);
  182. + ar9462_2p0_modes_high_ob_db_tx_gain);
  183. + else if (AR_SREV_9565_11(ah))
  184. + INIT_INI_ARRAY(&ah->iniModesTxGain,
  185. + ar9565_1p1_modes_high_ob_db_tx_gain_table);
  186. else if (AR_SREV_9565(ah))
  187. INIT_INI_ARRAY(&ah->iniModesTxGain,
  188. ar9565_1p0_modes_high_ob_db_tx_gain_table);
  189. @@ -500,6 +546,9 @@ static void ar9003_tx_gain_table_mode2(s
  190. else if (AR_SREV_9580(ah))
  191. INIT_INI_ARRAY(&ah->iniModesTxGain,
  192. ar9580_1p0_low_ob_db_tx_gain_table);
  193. + else if (AR_SREV_9565_11(ah))
  194. + INIT_INI_ARRAY(&ah->iniModesTxGain,
  195. + ar9565_1p1_modes_low_ob_db_tx_gain_table);
  196. else if (AR_SREV_9565(ah))
  197. INIT_INI_ARRAY(&ah->iniModesTxGain,
  198. ar9565_1p0_modes_low_ob_db_tx_gain_table);
  199. @@ -525,6 +574,9 @@ static void ar9003_tx_gain_table_mode3(s
  200. else if (AR_SREV_9580(ah))
  201. INIT_INI_ARRAY(&ah->iniModesTxGain,
  202. ar9580_1p0_high_power_tx_gain_table);
  203. + else if (AR_SREV_9565_11(ah))
  204. + INIT_INI_ARRAY(&ah->iniModesTxGain,
  205. + ar9565_1p1_modes_high_power_tx_gain_table);
  206. else if (AR_SREV_9565(ah))
  207. INIT_INI_ARRAY(&ah->iniModesTxGain,
  208. ar9565_1p0_modes_high_power_tx_gain_table);
  209. @@ -546,7 +598,7 @@ static void ar9003_tx_gain_table_mode4(s
  210. ar9462_2p1_modes_mix_ob_db_tx_gain);
  211. else if (AR_SREV_9462_20(ah))
  212. INIT_INI_ARRAY(&ah->iniModesTxGain,
  213. - ar9462_modes_mix_ob_db_tx_gain_table_2p0);
  214. + ar9462_2p0_modes_mix_ob_db_tx_gain);
  215. else
  216. INIT_INI_ARRAY(&ah->iniModesTxGain,
  217. ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
  218. @@ -581,6 +633,13 @@ static void ar9003_tx_gain_table_mode6(s
  219. ar9580_1p0_type6_tx_gain_table);
  220. }
  221. +static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)
  222. +{
  223. + if (AR_SREV_9340(ah))
  224. + INIT_INI_ARRAY(&ah->iniModesTxGain,
  225. + ar9340_cus227_tx_gain_table_1p0);
  226. +}
  227. +
  228. typedef void (*ath_txgain_tab)(struct ath_hw *ah);
  229. static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
  230. @@ -593,6 +652,7 @@ static void ar9003_tx_gain_table_apply(s
  231. ar9003_tx_gain_table_mode4,
  232. ar9003_tx_gain_table_mode5,
  233. ar9003_tx_gain_table_mode6,
  234. + ar9003_tx_gain_table_mode7,
  235. };
  236. int idx = ar9003_hw_get_tx_gain_idx(ah);
  237. @@ -629,7 +689,10 @@ static void ar9003_rx_gain_table_mode0(s
  238. ar9462_2p1_common_rx_gain);
  239. else if (AR_SREV_9462_20(ah))
  240. INIT_INI_ARRAY(&ah->iniModesRxGain,
  241. - ar9462_common_rx_gain_table_2p0);
  242. + ar9462_2p0_common_rx_gain);
  243. + else if (AR_SREV_9565_11(ah))
  244. + INIT_INI_ARRAY(&ah->iniModesRxGain,
  245. + ar9565_1p1_Common_rx_gain_table);
  246. else if (AR_SREV_9565(ah))
  247. INIT_INI_ARRAY(&ah->iniModesRxGain,
  248. ar9565_1p0_Common_rx_gain_table);
  249. @@ -657,7 +720,7 @@ static void ar9003_rx_gain_table_mode1(s
  250. ar9462_2p1_common_wo_xlna_rx_gain);
  251. else if (AR_SREV_9462_20(ah))
  252. INIT_INI_ARRAY(&ah->iniModesRxGain,
  253. - ar9462_common_wo_xlna_rx_gain_table_2p0);
  254. + ar9462_2p0_common_wo_xlna_rx_gain);
  255. else if (AR_SREV_9550(ah)) {
  256. INIT_INI_ARRAY(&ah->iniModesRxGain,
  257. ar955x_1p0_common_wo_xlna_rx_gain_table);
  258. @@ -666,6 +729,9 @@ static void ar9003_rx_gain_table_mode1(s
  259. } else if (AR_SREV_9580(ah))
  260. INIT_INI_ARRAY(&ah->iniModesRxGain,
  261. ar9580_1p0_wo_xlna_rx_gain_table);
  262. + else if (AR_SREV_9565_11(ah))
  263. + INIT_INI_ARRAY(&ah->iniModesRxGain,
  264. + ar9565_1p1_common_wo_xlna_rx_gain_table);
  265. else if (AR_SREV_9565(ah))
  266. INIT_INI_ARRAY(&ah->iniModesRxGain,
  267. ar9565_1p0_common_wo_xlna_rx_gain_table);
  268. @@ -687,7 +753,7 @@ static void ar9003_rx_gain_table_mode2(s
  269. ar9462_2p1_baseband_postamble_5g_xlna);
  270. } else if (AR_SREV_9462_20(ah)) {
  271. INIT_INI_ARRAY(&ah->iniModesRxGain,
  272. - ar9462_common_mixed_rx_gain_table_2p0);
  273. + ar9462_2p0_common_mixed_rx_gain);
  274. INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
  275. ar9462_2p0_baseband_core_mix_rxgain);
  276. INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
  277. @@ -701,12 +767,12 @@ static void ar9003_rx_gain_table_mode3(s
  278. {
  279. if (AR_SREV_9462_21(ah)) {
  280. INIT_INI_ARRAY(&ah->iniModesRxGain,
  281. - ar9462_2p1_common_5g_xlna_only_rx_gain);
  282. + ar9462_2p1_common_5g_xlna_only_rxgain);
  283. INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
  284. ar9462_2p1_baseband_postamble_5g_xlna);
  285. } else if (AR_SREV_9462_20(ah)) {
  286. INIT_INI_ARRAY(&ah->iniModesRxGain,
  287. - ar9462_2p0_5g_xlna_only_rxgain);
  288. + ar9462_2p0_common_5g_xlna_only_rxgain);
  289. INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
  290. ar9462_2p0_baseband_postamble_5g_xlna);
  291. }
  292. @@ -750,6 +816,9 @@ static void ar9003_hw_init_mode_gain_reg
  293. static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
  294. bool power_off)
  295. {
  296. + unsigned int i;
  297. + struct ar5416IniArray *array;
  298. +
  299. /*
  300. * Increase L1 Entry Latency. Some WB222 boards don't have
  301. * this change in eeprom/OTP.
  302. @@ -775,18 +844,13 @@ static void ar9003_hw_configpcipowersave
  303. * Configire PCIE after Ini init. SERDES values now come from ini file
  304. * This enables PCIe low power mode.
  305. */
  306. - if (ah->config.pcieSerDesWrite) {
  307. - unsigned int i;
  308. - struct ar5416IniArray *array;
  309. -
  310. - array = power_off ? &ah->iniPcieSerdes :
  311. - &ah->iniPcieSerdesLowPower;
  312. -
  313. - for (i = 0; i < array->ia_rows; i++) {
  314. - REG_WRITE(ah,
  315. - INI_RA(array, i, 0),
  316. - INI_RA(array, i, 1));
  317. - }
  318. + array = power_off ? &ah->iniPcieSerdes :
  319. + &ah->iniPcieSerdesLowPower;
  320. +
  321. + for (i = 0; i < array->ia_rows; i++) {
  322. + REG_WRITE(ah,
  323. + INI_RA(array, i, 0),
  324. + INI_RA(array, i, 1));
  325. }
  326. }
  327. --- a/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
  328. +++ b/drivers/net/wireless/ath/ath9k/ar9340_initvals.h
  329. @@ -1447,4 +1447,106 @@ static const u32 ar9340_1p0_soc_preamble
  330. {0x00007038, 0x000004c2},
  331. };
  332. +static const u32 ar9340_cus227_tx_gain_table_1p0[][5] = {
  333. + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  334. + {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
  335. + {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
  336. + {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
  337. + {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
  338. + {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
  339. + {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  340. + {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
  341. + {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
  342. + {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
  343. + {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
  344. + {0x0000a514, 0x1c000223, 0x1c000223, 0x11000400, 0x11000400},
  345. + {0x0000a518, 0x21002220, 0x21002220, 0x15000402, 0x15000402},
  346. + {0x0000a51c, 0x27002223, 0x27002223, 0x19000404, 0x19000404},
  347. + {0x0000a520, 0x2c022220, 0x2c022220, 0x1b000603, 0x1b000603},
  348. + {0x0000a524, 0x30022222, 0x30022222, 0x1f000a02, 0x1f000a02},
  349. + {0x0000a528, 0x35022225, 0x35022225, 0x23000a04, 0x23000a04},
  350. + {0x0000a52c, 0x3b02222a, 0x3b02222a, 0x26000a20, 0x26000a20},
  351. + {0x0000a530, 0x3f02222c, 0x3f02222c, 0x2a000e20, 0x2a000e20},
  352. + {0x0000a534, 0x4202242a, 0x4202242a, 0x2e000e22, 0x2e000e22},
  353. + {0x0000a538, 0x4702244a, 0x4702244a, 0x31000e24, 0x31000e24},
  354. + {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x34001640, 0x34001640},
  355. + {0x0000a540, 0x4e02246c, 0x4e02246c, 0x38001660, 0x38001660},
  356. + {0x0000a544, 0x5302266c, 0x5302266c, 0x3b001861, 0x3b001861},
  357. + {0x0000a548, 0x5702286c, 0x5702286c, 0x3e001a81, 0x3e001a81},
  358. + {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x42001a83, 0x42001a83},
  359. + {0x0000a550, 0x61024a6c, 0x61024a6c, 0x44001c84, 0x44001c84},
  360. + {0x0000a554, 0x66026a6c, 0x66026a6c, 0x48001ce3, 0x48001ce3},
  361. + {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x4c001ce5, 0x4c001ce5},
  362. + {0x0000a55c, 0x7002708c, 0x7002708c, 0x50001ce9, 0x50001ce9},
  363. + {0x0000a560, 0x7302b08a, 0x7302b08a, 0x54001ceb, 0x54001ceb},
  364. + {0x0000a564, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
  365. + {0x0000a568, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
  366. + {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
  367. + {0x0000a570, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
  368. + {0x0000a574, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
  369. + {0x0000a578, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
  370. + {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x56001eec, 0x56001eec},
  371. + {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
  372. + {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
  373. + {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
  374. + {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
  375. + {0x0000a590, 0x16800220, 0x16800220, 0x0f800202, 0x0f800202},
  376. + {0x0000a594, 0x1c800223, 0x1c800223, 0x11800400, 0x11800400},
  377. + {0x0000a598, 0x21820220, 0x21820220, 0x15800402, 0x15800402},
  378. + {0x0000a59c, 0x27820223, 0x27820223, 0x19800404, 0x19800404},
  379. + {0x0000a5a0, 0x2b822220, 0x2b822220, 0x1b800603, 0x1b800603},
  380. + {0x0000a5a4, 0x2f822222, 0x2f822222, 0x1f800a02, 0x1f800a02},
  381. + {0x0000a5a8, 0x34822225, 0x34822225, 0x23800a04, 0x23800a04},
  382. + {0x0000a5ac, 0x3a82222a, 0x3a82222a, 0x26800a20, 0x26800a20},
  383. + {0x0000a5b0, 0x3e82222c, 0x3e82222c, 0x2a800e20, 0x2a800e20},
  384. + {0x0000a5b4, 0x4282242a, 0x4282242a, 0x2e800e22, 0x2e800e22},
  385. + {0x0000a5b8, 0x4782244a, 0x4782244a, 0x31800e24, 0x31800e24},
  386. + {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x34801640, 0x34801640},
  387. + {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x38801660, 0x38801660},
  388. + {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3b801861, 0x3b801861},
  389. + {0x0000a5c8, 0x5782286c, 0x5782286c, 0x3e801a81, 0x3e801a81},
  390. + {0x0000a5cc, 0x5c84286b, 0x5c84286b, 0x42801a83, 0x42801a83},
  391. + {0x0000a5d0, 0x61842a6c, 0x61842a6c, 0x44801c84, 0x44801c84},
  392. + {0x0000a5d4, 0x66862a6c, 0x66862a6c, 0x48801ce3, 0x48801ce3},
  393. + {0x0000a5d8, 0x6b862e6c, 0x6b862e6c, 0x4c801ce5, 0x4c801ce5},
  394. + {0x0000a5dc, 0x7086308c, 0x7086308c, 0x50801ce9, 0x50801ce9},
  395. + {0x0000a5e0, 0x738a308a, 0x738a308a, 0x54801ceb, 0x54801ceb},
  396. + {0x0000a5e4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
  397. + {0x0000a5e8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
  398. + {0x0000a5ec, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
  399. + {0x0000a5f0, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
  400. + {0x0000a5f4, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
  401. + {0x0000a5f8, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
  402. + {0x0000a5fc, 0x778a308c, 0x778a308c, 0x56801eec, 0x56801eec},
  403. + {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  404. + {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  405. + {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  406. + {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  407. + {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  408. + {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
  409. + {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
  410. + {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
  411. + {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
  412. + {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
  413. + {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
  414. + {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
  415. + {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
  416. + {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
  417. + {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
  418. + {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
  419. + {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
  420. + {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
  421. + {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
  422. + {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
  423. + {0x00016044, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
  424. + {0x00016048, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
  425. + {0x00016280, 0x01000015, 0x01000015, 0x01001015, 0x01001015},
  426. + {0x00016288, 0x30318000, 0x30318000, 0x00318000, 0x00318000},
  427. + {0x00016444, 0x056db2db, 0x056db2db, 0x03b6d2e4, 0x03b6d2e4},
  428. + {0x00016448, 0x24925666, 0x24925666, 0x8e481266, 0x8e481266},
  429. + {0x0000a3a4, 0x00000011, 0x00000011, 0x00000011, 0x00000011},
  430. + {0x0000a3a8, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c, 0x3c3c3c3c},
  431. + {0x0000a3ac, 0x30303030, 0x30303030, 0x30303030, 0x30303030},
  432. +};
  433. +
  434. #endif /* INITVALS_9340_H */
  435. --- a/drivers/net/wireless/ath/ath9k/ath9k.h
  436. +++ b/drivers/net/wireless/ath/ath9k/ath9k.h
  437. @@ -459,6 +459,7 @@ void ath_check_ani(struct ath_softc *sc)
  438. int ath_update_survey_stats(struct ath_softc *sc);
  439. void ath_update_survey_nf(struct ath_softc *sc, int channel);
  440. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
  441. +void ath_ps_full_sleep(unsigned long data);
  442. /**********/
  443. /* BTCOEX */
  444. @@ -570,6 +571,34 @@ static inline void ath_fill_led_pin(stru
  445. }
  446. #endif
  447. +/************************/
  448. +/* Wake on Wireless LAN */
  449. +/************************/
  450. +
  451. +#ifdef CONFIG_ATH9K_WOW
  452. +void ath9k_init_wow(struct ieee80211_hw *hw);
  453. +int ath9k_suspend(struct ieee80211_hw *hw,
  454. + struct cfg80211_wowlan *wowlan);
  455. +int ath9k_resume(struct ieee80211_hw *hw);
  456. +void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled);
  457. +#else
  458. +static inline void ath9k_init_wow(struct ieee80211_hw *hw)
  459. +{
  460. +}
  461. +static inline int ath9k_suspend(struct ieee80211_hw *hw,
  462. + struct cfg80211_wowlan *wowlan)
  463. +{
  464. + return 0;
  465. +}
  466. +static inline int ath9k_resume(struct ieee80211_hw *hw)
  467. +{
  468. + return 0;
  469. +}
  470. +static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  471. +{
  472. +}
  473. +#endif /* CONFIG_ATH9K_WOW */
  474. +
  475. /*******************************/
  476. /* Antenna diversity/combining */
  477. /*******************************/
  478. @@ -632,15 +661,16 @@ void ath_ant_comb_scan(struct ath_softc
  479. /* Main driver core */
  480. /********************/
  481. -#define ATH9K_PCI_CUS198 0x0001
  482. -#define ATH9K_PCI_CUS230 0x0002
  483. -#define ATH9K_PCI_CUS217 0x0004
  484. -#define ATH9K_PCI_CUS252 0x0008
  485. -#define ATH9K_PCI_WOW 0x0010
  486. -#define ATH9K_PCI_BT_ANT_DIV 0x0020
  487. -#define ATH9K_PCI_D3_L1_WAR 0x0040
  488. -#define ATH9K_PCI_AR9565_1ANT 0x0080
  489. -#define ATH9K_PCI_AR9565_2ANT 0x0100
  490. +#define ATH9K_PCI_CUS198 0x0001
  491. +#define ATH9K_PCI_CUS230 0x0002
  492. +#define ATH9K_PCI_CUS217 0x0004
  493. +#define ATH9K_PCI_CUS252 0x0008
  494. +#define ATH9K_PCI_WOW 0x0010
  495. +#define ATH9K_PCI_BT_ANT_DIV 0x0020
  496. +#define ATH9K_PCI_D3_L1_WAR 0x0040
  497. +#define ATH9K_PCI_AR9565_1ANT 0x0080
  498. +#define ATH9K_PCI_AR9565_2ANT 0x0100
  499. +#define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200
  500. /*
  501. * Default cache line size, in bytes.
  502. @@ -723,6 +753,7 @@ struct ath_softc {
  503. struct work_struct hw_check_work;
  504. struct work_struct hw_reset_work;
  505. struct completion paprd_complete;
  506. + wait_queue_head_t tx_wait;
  507. unsigned int hw_busy_count;
  508. unsigned long sc_flags;
  509. @@ -759,6 +790,7 @@ struct ath_softc {
  510. struct delayed_work tx_complete_work;
  511. struct delayed_work hw_pll_work;
  512. struct timer_list rx_poll_timer;
  513. + struct timer_list sleep_timer;
  514. #ifdef CPTCFG_ATH9K_BTCOEX_SUPPORT
  515. struct ath_btcoex btcoex;
  516. @@ -783,7 +815,7 @@ struct ath_softc {
  517. bool tx99_state;
  518. s16 tx99_power;
  519. -#ifdef CONFIG_PM_SLEEP
  520. +#ifdef CONFIG_ATH9K_WOW
  521. atomic_t wow_got_bmiss_intr;
  522. atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */
  523. u32 wow_intr_before_sleep;
  524. @@ -946,10 +978,25 @@ struct fft_sample_ht20_40 {
  525. u8 data[SPECTRAL_HT20_40_NUM_BINS];
  526. } __packed;
  527. -int ath9k_tx99_init(struct ath_softc *sc);
  528. -void ath9k_tx99_deinit(struct ath_softc *sc);
  529. +/********/
  530. +/* TX99 */
  531. +/********/
  532. +
  533. +#ifdef CONFIG_ATH9K_TX99
  534. +void ath9k_tx99_init_debug(struct ath_softc *sc);
  535. int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
  536. struct ath_tx_control *txctl);
  537. +#else
  538. +static inline void ath9k_tx99_init_debug(struct ath_softc *sc)
  539. +{
  540. +}
  541. +static inline int ath9k_tx99_send(struct ath_softc *sc,
  542. + struct sk_buff *skb,
  543. + struct ath_tx_control *txctl)
  544. +{
  545. + return 0;
  546. +}
  547. +#endif /* CONFIG_ATH9K_TX99 */
  548. void ath9k_tasklet(unsigned long data);
  549. int ath_cabq_update(struct ath_softc *);
  550. @@ -966,6 +1013,9 @@ extern bool is_ath9k_unloaded;
  551. u8 ath9k_parse_mpdudensity(u8 mpdudensity);
  552. irqreturn_t ath_isr(int irq, void *dev);
  553. +int ath_reset(struct ath_softc *sc);
  554. +void ath_cancel_work(struct ath_softc *sc);
  555. +void ath_restart_work(struct ath_softc *sc);
  556. int ath9k_init_device(u16 devid, struct ath_softc *sc,
  557. const struct ath_bus_ops *bus_ops);
  558. void ath9k_deinit_device(struct ath_softc *sc);
  559. --- a/drivers/net/wireless/ath/ath9k/debug.c
  560. +++ b/drivers/net/wireless/ath/ath9k/debug.c
  561. @@ -1782,111 +1782,6 @@ void ath9k_deinit_debug(struct ath_softc
  562. }
  563. }
  564. -static ssize_t read_file_tx99(struct file *file, char __user *user_buf,
  565. - size_t count, loff_t *ppos)
  566. -{
  567. - struct ath_softc *sc = file->private_data;
  568. - char buf[3];
  569. - unsigned int len;
  570. -
  571. - len = sprintf(buf, "%d\n", sc->tx99_state);
  572. - return simple_read_from_buffer(user_buf, count, ppos, buf, len);
  573. -}
  574. -
  575. -static ssize_t write_file_tx99(struct file *file, const char __user *user_buf,
  576. - size_t count, loff_t *ppos)
  577. -{
  578. - struct ath_softc *sc = file->private_data;
  579. - struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  580. - char buf[32];
  581. - bool start;
  582. - ssize_t len;
  583. - int r;
  584. -
  585. - if (sc->nvifs > 1)
  586. - return -EOPNOTSUPP;
  587. -
  588. - len = min(count, sizeof(buf) - 1);
  589. - if (copy_from_user(buf, user_buf, len))
  590. - return -EFAULT;
  591. -
  592. - if (strtobool(buf, &start))
  593. - return -EINVAL;
  594. -
  595. - if (start == sc->tx99_state) {
  596. - if (!start)
  597. - return count;
  598. - ath_dbg(common, XMIT, "Resetting TX99\n");
  599. - ath9k_tx99_deinit(sc);
  600. - }
  601. -
  602. - if (!start) {
  603. - ath9k_tx99_deinit(sc);
  604. - return count;
  605. - }
  606. -
  607. - r = ath9k_tx99_init(sc);
  608. - if (r)
  609. - return r;
  610. -
  611. - return count;
  612. -}
  613. -
  614. -static const struct file_operations fops_tx99 = {
  615. - .read = read_file_tx99,
  616. - .write = write_file_tx99,
  617. - .open = simple_open,
  618. - .owner = THIS_MODULE,
  619. - .llseek = default_llseek,
  620. -};
  621. -
  622. -static ssize_t read_file_tx99_power(struct file *file,
  623. - char __user *user_buf,
  624. - size_t count, loff_t *ppos)
  625. -{
  626. - struct ath_softc *sc = file->private_data;
  627. - char buf[32];
  628. - unsigned int len;
  629. -
  630. - len = sprintf(buf, "%d (%d dBm)\n",
  631. - sc->tx99_power,
  632. - sc->tx99_power / 2);
  633. -
  634. - return simple_read_from_buffer(user_buf, count, ppos, buf, len);
  635. -}
  636. -
  637. -static ssize_t write_file_tx99_power(struct file *file,
  638. - const char __user *user_buf,
  639. - size_t count, loff_t *ppos)
  640. -{
  641. - struct ath_softc *sc = file->private_data;
  642. - int r;
  643. - u8 tx_power;
  644. -
  645. - r = kstrtou8_from_user(user_buf, count, 0, &tx_power);
  646. - if (r)
  647. - return r;
  648. -
  649. - if (tx_power > MAX_RATE_POWER)
  650. - return -EINVAL;
  651. -
  652. - sc->tx99_power = tx_power;
  653. -
  654. - ath9k_ps_wakeup(sc);
  655. - ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power);
  656. - ath9k_ps_restore(sc);
  657. -
  658. - return count;
  659. -}
  660. -
  661. -static const struct file_operations fops_tx99_power = {
  662. - .read = read_file_tx99_power,
  663. - .write = write_file_tx99_power,
  664. - .open = simple_open,
  665. - .owner = THIS_MODULE,
  666. - .llseek = default_llseek,
  667. -};
  668. -
  669. int ath9k_init_debug(struct ath_hw *ah)
  670. {
  671. struct ath_common *common = ath9k_hw_common(ah);
  672. @@ -1903,6 +1798,7 @@ int ath9k_init_debug(struct ath_hw *ah)
  673. #endif
  674. ath9k_dfs_init_debug(sc);
  675. + ath9k_tx99_init_debug(sc);
  676. debugfs_create_file("dma", S_IRUSR, sc->debug.debugfs_phy, sc,
  677. &fops_dma);
  678. @@ -1978,15 +1874,6 @@ int ath9k_init_debug(struct ath_hw *ah)
  679. debugfs_create_file("btcoex", S_IRUSR, sc->debug.debugfs_phy, sc,
  680. &fops_btcoex);
  681. #endif
  682. - if (config_enabled(CPTCFG_ATH9K_TX99) &&
  683. - AR_SREV_9300_20_OR_LATER(ah)) {
  684. - debugfs_create_file("tx99", S_IRUSR | S_IWUSR,
  685. - sc->debug.debugfs_phy, sc,
  686. - &fops_tx99);
  687. - debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR,
  688. - sc->debug.debugfs_phy, sc,
  689. - &fops_tx99_power);
  690. - }
  691. return 0;
  692. }
  693. --- a/drivers/net/wireless/ath/ath9k/hw.c
  694. +++ b/drivers/net/wireless/ath/ath9k/hw.c
  695. @@ -17,6 +17,7 @@
  696. #include <linux/io.h>
  697. #include <linux/slab.h>
  698. #include <linux/module.h>
  699. +#include <linux/time.h>
  700. #include <asm/unaligned.h>
  701. #include "hw.h"
  702. @@ -454,7 +455,6 @@ static void ath9k_hw_init_config(struct
  703. }
  704. ah->config.rx_intr_mitigation = true;
  705. - ah->config.pcieSerDesWrite = true;
  706. /*
  707. * We need this for PCI devices only (Cardbus, PCI, miniPCI)
  708. @@ -1502,8 +1502,9 @@ static bool ath9k_hw_channel_change(stru
  709. int r;
  710. if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
  711. - band_switch = IS_CHAN_5GHZ(ah->curchan) != IS_CHAN_5GHZ(chan);
  712. - mode_diff = (chan->channelFlags != ah->curchan->channelFlags);
  713. + u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
  714. + band_switch = !!(flags_diff & CHANNEL_5GHZ);
  715. + mode_diff = !!(flags_diff & ~CHANNEL_HT);
  716. }
  717. for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
  718. @@ -1815,7 +1816,7 @@ static int ath9k_hw_do_fastcc(struct ath
  719. * If cross-band fcc is not supoprted, bail out if channelFlags differ.
  720. */
  721. if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
  722. - chan->channelFlags != ah->curchan->channelFlags)
  723. + ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
  724. goto fail;
  725. if (!ath9k_hw_check_alive(ah))
  726. @@ -1856,10 +1857,12 @@ int ath9k_hw_reset(struct ath_hw *ah, st
  727. struct ath9k_hw_cal_data *caldata, bool fastcc)
  728. {
  729. struct ath_common *common = ath9k_hw_common(ah);
  730. + struct timespec ts;
  731. u32 saveLedState;
  732. u32 saveDefAntenna;
  733. u32 macStaId1;
  734. u64 tsf = 0;
  735. + s64 usec = 0;
  736. int r;
  737. bool start_mci_reset = false;
  738. bool save_fullsleep = ah->chip_fullsleep;
  739. @@ -1902,10 +1905,10 @@ int ath9k_hw_reset(struct ath_hw *ah, st
  740. macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
  741. - /* For chips on which RTC reset is done, save TSF before it gets cleared */
  742. - if (AR_SREV_9100(ah) ||
  743. - (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
  744. - tsf = ath9k_hw_gettsf64(ah);
  745. + /* Save TSF before chip reset, a cold reset clears it */
  746. + tsf = ath9k_hw_gettsf64(ah);
  747. + getrawmonotonic(&ts);
  748. + usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000;
  749. saveLedState = REG_READ(ah, AR_CFG_LED) &
  750. (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
  751. @@ -1938,8 +1941,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st
  752. }
  753. /* Restore TSF */
  754. - if (tsf)
  755. - ath9k_hw_settsf64(ah, tsf);
  756. + getrawmonotonic(&ts);
  757. + usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000 - usec;
  758. + ath9k_hw_settsf64(ah, tsf + usec);
  759. if (AR_SREV_9280_20_OR_LATER(ah))
  760. REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
  761. --- a/drivers/net/wireless/ath/ath9k/hw.h
  762. +++ b/drivers/net/wireless/ath/ath9k/hw.h
  763. @@ -283,7 +283,6 @@ struct ath9k_ops_config {
  764. int additional_swba_backoff;
  765. int ack_6mb;
  766. u32 cwm_ignore_extcca;
  767. - bool pcieSerDesWrite;
  768. u8 pcie_clock_req;
  769. u32 pcie_waen;
  770. u8 analog_shiftreg;
  771. @@ -316,6 +315,7 @@ struct ath9k_ops_config {
  772. u32 ant_ctrl_comm2g_switch_enable;
  773. bool xatten_margin_cfg;
  774. bool alt_mingainidx;
  775. + bool no_pll_pwrsave;
  776. };
  777. enum ath9k_int {
  778. @@ -920,7 +920,7 @@ struct ath_hw {
  779. /* Enterprise mode cap */
  780. u32 ent_mode;
  781. -#ifdef CONFIG_PM_SLEEP
  782. +#ifdef CONFIG_ATH9K_WOW
  783. u32 wow_event_mask;
  784. #endif
  785. bool is_clk_25mhz;
  786. @@ -1126,7 +1126,7 @@ ath9k_hw_get_btcoex_scheme(struct ath_hw
  787. #endif /* CPTCFG_ATH9K_BTCOEX_SUPPORT */
  788. -#ifdef CONFIG_PM_SLEEP
  789. +#ifdef CONFIG_ATH9K_WOW
  790. const char *ath9k_hw_wow_event_to_string(u32 wow_event);
  791. void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
  792. u8 *user_mask, int pattern_count,
  793. --- a/drivers/net/wireless/ath/ath9k/init.c
  794. +++ b/drivers/net/wireless/ath/ath9k/init.c
  795. @@ -609,6 +609,11 @@ static void ath9k_init_platform(struct a
  796. ah->config.pcie_waen = 0x0040473b;
  797. ath_info(common, "Enable WAR for ASPM D3/L1\n");
  798. }
  799. +
  800. + if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
  801. + ah->config.no_pll_pwrsave = true;
  802. + ath_info(common, "Disable PLL PowerSave\n");
  803. + }
  804. }
  805. static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
  806. @@ -683,6 +688,7 @@ static int ath9k_init_softc(u16 devid, s
  807. common = ath9k_hw_common(ah);
  808. sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
  809. sc->tx99_power = MAX_RATE_POWER + 1;
  810. + init_waitqueue_head(&sc->tx_wait);
  811. if (!pdata) {
  812. ah->ah_flags |= AH_USE_EEPROM;
  813. @@ -730,6 +736,7 @@ static int ath9k_init_softc(u16 devid, s
  814. tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
  815. (unsigned long)sc);
  816. + setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
  817. INIT_WORK(&sc->hw_reset_work, ath_reset_work);
  818. INIT_WORK(&sc->hw_check_work, ath_hw_check);
  819. INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
  820. @@ -845,7 +852,8 @@ static const struct ieee80211_iface_limi
  821. };
  822. static const struct ieee80211_iface_limit if_dfs_limits[] = {
  823. - { .max = 1, .types = BIT(NL80211_IFTYPE_AP) },
  824. + { .max = 1, .types = BIT(NL80211_IFTYPE_AP) |
  825. + BIT(NL80211_IFTYPE_ADHOC) },
  826. };
  827. static const struct ieee80211_iface_combination if_comb[] = {
  828. @@ -862,20 +870,11 @@ static const struct ieee80211_iface_comb
  829. .max_interfaces = 1,
  830. .num_different_channels = 1,
  831. .beacon_int_infra_match = true,
  832. - .radar_detect_widths = BIT(NL80211_CHAN_NO_HT) |
  833. - BIT(NL80211_CHAN_HT20),
  834. + .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
  835. + BIT(NL80211_CHAN_WIDTH_20),
  836. }
  837. };
  838. -#ifdef CONFIG_PM
  839. -static const struct wiphy_wowlan_support ath9k_wowlan_support = {
  840. - .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
  841. - .n_patterns = MAX_NUM_USER_PATTERN,
  842. - .pattern_min_len = 1,
  843. - .pattern_max_len = MAX_PATTERN_SIZE,
  844. -};
  845. -#endif
  846. -
  847. void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
  848. {
  849. struct ath_hw *ah = sc->sc_ah;
  850. @@ -925,16 +924,6 @@ void ath9k_set_hw_capab(struct ath_softc
  851. hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
  852. hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
  853. -#ifdef CONFIG_PM_SLEEP
  854. - if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
  855. - (sc->driver_data & ATH9K_PCI_WOW) &&
  856. - device_can_wakeup(sc->dev))
  857. - hw->wiphy->wowlan = &ath9k_wowlan_support;
  858. -
  859. - atomic_set(&sc->wow_sleep_proc_intr, -1);
  860. - atomic_set(&sc->wow_got_bmiss_intr, -1);
  861. -#endif
  862. -
  863. hw->queues = 4;
  864. hw->max_rates = 4;
  865. hw->channel_change_time = 5000;
  866. @@ -960,6 +949,7 @@ void ath9k_set_hw_capab(struct ath_softc
  867. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  868. &sc->sbands[IEEE80211_BAND_5GHZ];
  869. + ath9k_init_wow(hw);
  870. ath9k_reload_chainmask_settings(sc);
  871. SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
  872. @@ -1058,6 +1048,7 @@ static void ath9k_deinit_softc(struct at
  873. if (ATH_TXQ_SETUP(sc, i))
  874. ath_tx_cleanupq(sc, &sc->tx.txq[i]);
  875. + del_timer_sync(&sc->sleep_timer);
  876. ath9k_hw_deinit(sc->sc_ah);
  877. if (sc->dfs_detector != NULL)
  878. sc->dfs_detector->exit(sc->dfs_detector);
  879. --- a/drivers/net/wireless/ath/ath9k/main.c
  880. +++ b/drivers/net/wireless/ath/ath9k/main.c
  881. @@ -82,6 +82,22 @@ static bool ath9k_setpower(struct ath_so
  882. return ret;
  883. }
  884. +void ath_ps_full_sleep(unsigned long data)
  885. +{
  886. + struct ath_softc *sc = (struct ath_softc *) data;
  887. + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  888. + bool reset;
  889. +
  890. + spin_lock(&common->cc_lock);
  891. + ath_hw_cycle_counters_update(common);
  892. + spin_unlock(&common->cc_lock);
  893. +
  894. + ath9k_hw_setrxabort(sc->sc_ah, 1);
  895. + ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  896. +
  897. + ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  898. +}
  899. +
  900. void ath9k_ps_wakeup(struct ath_softc *sc)
  901. {
  902. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  903. @@ -92,6 +108,7 @@ void ath9k_ps_wakeup(struct ath_softc *s
  904. if (++sc->ps_usecount != 1)
  905. goto unlock;
  906. + del_timer_sync(&sc->sleep_timer);
  907. power_mode = sc->sc_ah->power_mode;
  908. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  909. @@ -117,17 +134,17 @@ void ath9k_ps_restore(struct ath_softc *
  910. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  911. enum ath9k_power_mode mode;
  912. unsigned long flags;
  913. - bool reset;
  914. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  915. if (--sc->ps_usecount != 0)
  916. goto unlock;
  917. if (sc->ps_idle) {
  918. - ath9k_hw_setrxabort(sc->sc_ah, 1);
  919. - ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  920. - mode = ATH9K_PM_FULL_SLEEP;
  921. - } else if (sc->ps_enabled &&
  922. + mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
  923. + goto unlock;
  924. + }
  925. +
  926. + if (sc->ps_enabled &&
  927. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  928. PS_WAIT_FOR_CAB |
  929. PS_WAIT_FOR_PSPOLL_DATA |
  930. @@ -163,13 +180,13 @@ static void __ath_cancel_work(struct ath
  931. #endif
  932. }
  933. -static void ath_cancel_work(struct ath_softc *sc)
  934. +void ath_cancel_work(struct ath_softc *sc)
  935. {
  936. __ath_cancel_work(sc);
  937. cancel_work_sync(&sc->hw_reset_work);
  938. }
  939. -static void ath_restart_work(struct ath_softc *sc)
  940. +void ath_restart_work(struct ath_softc *sc)
  941. {
  942. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  943. @@ -487,6 +504,8 @@ void ath9k_tasklet(unsigned long data)
  944. ath_tx_edma_tasklet(sc);
  945. else
  946. ath_tx_tasklet(sc);
  947. +
  948. + wake_up(&sc->tx_wait);
  949. }
  950. ath9k_btcoex_handle_interrupt(sc, status);
  951. @@ -579,7 +598,8 @@ irqreturn_t ath_isr(int irq, void *dev)
  952. goto chip_reset;
  953. }
  954. -#ifdef CONFIG_PM_SLEEP
  955. +
  956. +#ifdef CONFIG_ATH9K_WOW
  957. if (status & ATH9K_INT_BMISS) {
  958. if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
  959. ath_dbg(common, ANY, "during WoW we got a BMISS\n");
  960. @@ -588,6 +608,8 @@ irqreturn_t ath_isr(int irq, void *dev)
  961. }
  962. }
  963. #endif
  964. +
  965. +
  966. if (status & ATH9K_INT_SWBA)
  967. tasklet_schedule(&sc->bcon_tasklet);
  968. @@ -627,7 +649,7 @@ chip_reset:
  969. #undef SCHED_INTR
  970. }
  971. -static int ath_reset(struct ath_softc *sc)
  972. +int ath_reset(struct ath_softc *sc)
  973. {
  974. int r;
  975. @@ -1817,13 +1839,31 @@ static void ath9k_set_coverage_class(str
  976. mutex_unlock(&sc->mutex);
  977. }
  978. +static bool ath9k_has_tx_pending(struct ath_softc *sc)
  979. +{
  980. + int i, npend;
  981. +
  982. + for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  983. + if (!ATH_TXQ_SETUP(sc, i))
  984. + continue;
  985. +
  986. + if (!sc->tx.txq[i].axq_depth)
  987. + continue;
  988. +
  989. + npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  990. + if (npend)
  991. + break;
  992. + }
  993. +
  994. + return !!npend;
  995. +}
  996. +
  997. static void ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
  998. {
  999. struct ath_softc *sc = hw->priv;
  1000. struct ath_hw *ah = sc->sc_ah;
  1001. struct ath_common *common = ath9k_hw_common(ah);
  1002. - int timeout = 200; /* ms */
  1003. - int i, j;
  1004. + int timeout = HZ / 5; /* 200 ms */
  1005. bool drain_txq;
  1006. mutex_lock(&sc->mutex);
  1007. @@ -1841,25 +1881,9 @@ static void ath9k_flush(struct ieee80211
  1008. return;
  1009. }
  1010. - for (j = 0; j < timeout; j++) {
  1011. - bool npend = false;
  1012. -
  1013. - if (j)
  1014. - usleep_range(1000, 2000);
  1015. -
  1016. - for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1017. - if (!ATH_TXQ_SETUP(sc, i))
  1018. - continue;
  1019. -
  1020. - npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1021. -
  1022. - if (npend)
  1023. - break;
  1024. - }
  1025. -
  1026. - if (!npend)
  1027. - break;
  1028. - }
  1029. + if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc),
  1030. + timeout) > 0)
  1031. + drop = false;
  1032. if (drop) {
  1033. ath9k_ps_wakeup(sc);
  1034. @@ -2021,333 +2045,6 @@ static int ath9k_get_antenna(struct ieee
  1035. return 0;
  1036. }
  1037. -#ifdef CONFIG_PM_SLEEP
  1038. -
  1039. -static void ath9k_wow_map_triggers(struct ath_softc *sc,
  1040. - struct cfg80211_wowlan *wowlan,
  1041. - u32 *wow_triggers)
  1042. -{
  1043. - if (wowlan->disconnect)
  1044. - *wow_triggers |= AH_WOW_LINK_CHANGE |
  1045. - AH_WOW_BEACON_MISS;
  1046. - if (wowlan->magic_pkt)
  1047. - *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
  1048. -
  1049. - if (wowlan->n_patterns)
  1050. - *wow_triggers |= AH_WOW_USER_PATTERN_EN;
  1051. -
  1052. - sc->wow_enabled = *wow_triggers;
  1053. -
  1054. -}
  1055. -
  1056. -static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
  1057. -{
  1058. - struct ath_hw *ah = sc->sc_ah;
  1059. - struct ath_common *common = ath9k_hw_common(ah);
  1060. - int pattern_count = 0;
  1061. - int i, byte_cnt;
  1062. - u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
  1063. - u8 dis_deauth_mask[MAX_PATTERN_SIZE];
  1064. -
  1065. - memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
  1066. - memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
  1067. -
  1068. - /*
  1069. - * Create Dissassociate / Deauthenticate packet filter
  1070. - *
  1071. - * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
  1072. - * +--------------+----------+---------+--------+--------+----
  1073. - * + Frame Control+ Duration + DA + SA + BSSID +
  1074. - * +--------------+----------+---------+--------+--------+----
  1075. - *
  1076. - * The above is the management frame format for disassociate/
  1077. - * deauthenticate pattern, from this we need to match the first byte
  1078. - * of 'Frame Control' and DA, SA, and BSSID fields
  1079. - * (skipping 2nd byte of FC and Duration feild.
  1080. - *
  1081. - * Disassociate pattern
  1082. - * --------------------
  1083. - * Frame control = 00 00 1010
  1084. - * DA, SA, BSSID = x:x:x:x:x:x
  1085. - * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1086. - * | x:x:x:x:x:x -- 22 bytes
  1087. - *
  1088. - * Deauthenticate pattern
  1089. - * ----------------------
  1090. - * Frame control = 00 00 1100
  1091. - * DA, SA, BSSID = x:x:x:x:x:x
  1092. - * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1093. - * | x:x:x:x:x:x -- 22 bytes
  1094. - */
  1095. -
  1096. - /* Create Disassociate Pattern first */
  1097. -
  1098. - byte_cnt = 0;
  1099. -
  1100. - /* Fill out the mask with all FF's */
  1101. -
  1102. - for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
  1103. - dis_deauth_mask[i] = 0xff;
  1104. -
  1105. - /* copy the first byte of frame control field */
  1106. - dis_deauth_pattern[byte_cnt] = 0xa0;
  1107. - byte_cnt++;
  1108. -
  1109. - /* skip 2nd byte of frame control and Duration field */
  1110. - byte_cnt += 3;
  1111. -
  1112. - /*
  1113. - * need not match the destination mac address, it can be a broadcast
  1114. - * mac address or an unicast to this station
  1115. - */
  1116. - byte_cnt += 6;
  1117. -
  1118. - /* copy the source mac address */
  1119. - memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1120. -
  1121. - byte_cnt += 6;
  1122. -
  1123. - /* copy the bssid, its same as the source mac address */
  1124. -
  1125. - memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1126. -
  1127. - /* Create Disassociate pattern mask */
  1128. -
  1129. - dis_deauth_mask[0] = 0xfe;
  1130. - dis_deauth_mask[1] = 0x03;
  1131. - dis_deauth_mask[2] = 0xc0;
  1132. -
  1133. - ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
  1134. -
  1135. - ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1136. - pattern_count, byte_cnt);
  1137. -
  1138. - pattern_count++;
  1139. - /*
  1140. - * for de-authenticate pattern, only the first byte of the frame
  1141. - * control field gets changed from 0xA0 to 0xC0
  1142. - */
  1143. - dis_deauth_pattern[0] = 0xC0;
  1144. -
  1145. - ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1146. - pattern_count, byte_cnt);
  1147. -
  1148. -}
  1149. -
  1150. -static void ath9k_wow_add_pattern(struct ath_softc *sc,
  1151. - struct cfg80211_wowlan *wowlan)
  1152. -{
  1153. - struct ath_hw *ah = sc->sc_ah;
  1154. - struct ath9k_wow_pattern *wow_pattern = NULL;
  1155. - struct cfg80211_pkt_pattern *patterns = wowlan->patterns;
  1156. - int mask_len;
  1157. - s8 i = 0;
  1158. -
  1159. - if (!wowlan->n_patterns)
  1160. - return;
  1161. -
  1162. - /*
  1163. - * Add the new user configured patterns
  1164. - */
  1165. - for (i = 0; i < wowlan->n_patterns; i++) {
  1166. -
  1167. - wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
  1168. -
  1169. - if (!wow_pattern)
  1170. - return;
  1171. -
  1172. - /*
  1173. - * TODO: convert the generic user space pattern to
  1174. - * appropriate chip specific/802.11 pattern.
  1175. - */
  1176. -
  1177. - mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
  1178. - memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
  1179. - memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
  1180. - memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
  1181. - patterns[i].pattern_len);
  1182. - memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
  1183. - wow_pattern->pattern_len = patterns[i].pattern_len;
  1184. -
  1185. - /*
  1186. - * just need to take care of deauth and disssoc pattern,
  1187. - * make sure we don't overwrite them.
  1188. - */
  1189. -
  1190. - ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
  1191. - wow_pattern->mask_bytes,
  1192. - i + 2,
  1193. - wow_pattern->pattern_len);
  1194. - kfree(wow_pattern);
  1195. -
  1196. - }
  1197. -
  1198. -}
  1199. -
  1200. -static int ath9k_suspend(struct ieee80211_hw *hw,
  1201. - struct cfg80211_wowlan *wowlan)
  1202. -{
  1203. - struct ath_softc *sc = hw->priv;
  1204. - struct ath_hw *ah = sc->sc_ah;
  1205. - struct ath_common *common = ath9k_hw_common(ah);
  1206. - u32 wow_triggers_enabled = 0;
  1207. - int ret = 0;
  1208. -
  1209. - mutex_lock(&sc->mutex);
  1210. -
  1211. - ath_cancel_work(sc);
  1212. - ath_stop_ani(sc);
  1213. - del_timer_sync(&sc->rx_poll_timer);
  1214. -
  1215. - if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1216. - ath_dbg(common, ANY, "Device not present\n");
  1217. - ret = -EINVAL;
  1218. - goto fail_wow;
  1219. - }
  1220. -
  1221. - if (WARN_ON(!wowlan)) {
  1222. - ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
  1223. - ret = -EINVAL;
  1224. - goto fail_wow;
  1225. - }
  1226. -
  1227. - if (!device_can_wakeup(sc->dev)) {
  1228. - ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
  1229. - ret = 1;
  1230. - goto fail_wow;
  1231. - }
  1232. -
  1233. - /*
  1234. - * none of the sta vifs are associated
  1235. - * and we are not currently handling multivif
  1236. - * cases, for instance we have to seperately
  1237. - * configure 'keep alive frame' for each
  1238. - * STA.
  1239. - */
  1240. -
  1241. - if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1242. - ath_dbg(common, WOW, "None of the STA vifs are associated\n");
  1243. - ret = 1;
  1244. - goto fail_wow;
  1245. - }
  1246. -
  1247. - if (sc->nvifs > 1) {
  1248. - ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
  1249. - ret = 1;
  1250. - goto fail_wow;
  1251. - }
  1252. -
  1253. - ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
  1254. -
  1255. - ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
  1256. - wow_triggers_enabled);
  1257. -
  1258. - ath9k_ps_wakeup(sc);
  1259. -
  1260. - ath9k_stop_btcoex(sc);
  1261. -
  1262. - /*
  1263. - * Enable wake up on recieving disassoc/deauth
  1264. - * frame by default.
  1265. - */
  1266. - ath9k_wow_add_disassoc_deauth_pattern(sc);
  1267. -
  1268. - if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
  1269. - ath9k_wow_add_pattern(sc, wowlan);
  1270. -
  1271. - spin_lock_bh(&sc->sc_pcu_lock);
  1272. - /*
  1273. - * To avoid false wake, we enable beacon miss interrupt only
  1274. - * when we go to sleep. We save the current interrupt mask
  1275. - * so we can restore it after the system wakes up
  1276. - */
  1277. - sc->wow_intr_before_sleep = ah->imask;
  1278. - ah->imask &= ~ATH9K_INT_GLOBAL;
  1279. - ath9k_hw_disable_interrupts(ah);
  1280. - ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
  1281. - ath9k_hw_set_interrupts(ah);
  1282. - ath9k_hw_enable_interrupts(ah);
  1283. -
  1284. - spin_unlock_bh(&sc->sc_pcu_lock);
  1285. -
  1286. - /*
  1287. - * we can now sync irq and kill any running tasklets, since we already
  1288. - * disabled interrupts and not holding a spin lock
  1289. - */
  1290. - synchronize_irq(sc->irq);
  1291. - tasklet_kill(&sc->intr_tq);
  1292. -
  1293. - ath9k_hw_wow_enable(ah, wow_triggers_enabled);
  1294. -
  1295. - ath9k_ps_restore(sc);
  1296. - ath_dbg(common, ANY, "WoW enabled in ath9k\n");
  1297. - atomic_inc(&sc->wow_sleep_proc_intr);
  1298. -
  1299. -fail_wow:
  1300. - mutex_unlock(&sc->mutex);
  1301. - return ret;
  1302. -}
  1303. -
  1304. -static int ath9k_resume(struct ieee80211_hw *hw)
  1305. -{
  1306. - struct ath_softc *sc = hw->priv;
  1307. - struct ath_hw *ah = sc->sc_ah;
  1308. - struct ath_common *common = ath9k_hw_common(ah);
  1309. - u32 wow_status;
  1310. -
  1311. - mutex_lock(&sc->mutex);
  1312. -
  1313. - ath9k_ps_wakeup(sc);
  1314. -
  1315. - spin_lock_bh(&sc->sc_pcu_lock);
  1316. -
  1317. - ath9k_hw_disable_interrupts(ah);
  1318. - ah->imask = sc->wow_intr_before_sleep;
  1319. - ath9k_hw_set_interrupts(ah);
  1320. - ath9k_hw_enable_interrupts(ah);
  1321. -
  1322. - spin_unlock_bh(&sc->sc_pcu_lock);
  1323. -
  1324. - wow_status = ath9k_hw_wow_wakeup(ah);
  1325. -
  1326. - if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
  1327. - /*
  1328. - * some devices may not pick beacon miss
  1329. - * as the reason they woke up so we add
  1330. - * that here for that shortcoming.
  1331. - */
  1332. - wow_status |= AH_WOW_BEACON_MISS;
  1333. - atomic_dec(&sc->wow_got_bmiss_intr);
  1334. - ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
  1335. - }
  1336. -
  1337. - atomic_dec(&sc->wow_sleep_proc_intr);
  1338. -
  1339. - if (wow_status) {
  1340. - ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
  1341. - ath9k_hw_wow_event_to_string(wow_status), wow_status);
  1342. - }
  1343. -
  1344. - ath_restart_work(sc);
  1345. - ath9k_start_btcoex(sc);
  1346. -
  1347. - ath9k_ps_restore(sc);
  1348. - mutex_unlock(&sc->mutex);
  1349. -
  1350. - return 0;
  1351. -}
  1352. -
  1353. -static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  1354. -{
  1355. - struct ath_softc *sc = hw->priv;
  1356. -
  1357. - mutex_lock(&sc->mutex);
  1358. - device_init_wakeup(sc->dev, 1);
  1359. - device_set_wakeup_enable(sc->dev, enabled);
  1360. - mutex_unlock(&sc->mutex);
  1361. -}
  1362. -
  1363. -#endif
  1364. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  1365. {
  1366. struct ath_softc *sc = hw->priv;
  1367. @@ -2373,134 +2070,6 @@ static void ath9k_channel_switch_beacon(
  1368. sc->csa_vif = vif;
  1369. }
  1370. -static void ath9k_tx99_stop(struct ath_softc *sc)
  1371. -{
  1372. - struct ath_hw *ah = sc->sc_ah;
  1373. - struct ath_common *common = ath9k_hw_common(ah);
  1374. -
  1375. - ath_drain_all_txq(sc);
  1376. - ath_startrecv(sc);
  1377. -
  1378. - ath9k_hw_set_interrupts(ah);
  1379. - ath9k_hw_enable_interrupts(ah);
  1380. -
  1381. - ieee80211_wake_queues(sc->hw);
  1382. -
  1383. - kfree_skb(sc->tx99_skb);
  1384. - sc->tx99_skb = NULL;
  1385. - sc->tx99_state = false;
  1386. -
  1387. - ath9k_hw_tx99_stop(sc->sc_ah);
  1388. - ath_dbg(common, XMIT, "TX99 stopped\n");
  1389. -}
  1390. -
  1391. -static struct sk_buff *ath9k_build_tx99_skb(struct ath_softc *sc)
  1392. -{
  1393. - static u8 PN9Data[] = {0xff, 0x87, 0xb8, 0x59, 0xb7, 0xa1, 0xcc, 0x24,
  1394. - 0x57, 0x5e, 0x4b, 0x9c, 0x0e, 0xe9, 0xea, 0x50,
  1395. - 0x2a, 0xbe, 0xb4, 0x1b, 0xb6, 0xb0, 0x5d, 0xf1,
  1396. - 0xe6, 0x9a, 0xe3, 0x45, 0xfd, 0x2c, 0x53, 0x18,
  1397. - 0x0c, 0xca, 0xc9, 0xfb, 0x49, 0x37, 0xe5, 0xa8,
  1398. - 0x51, 0x3b, 0x2f, 0x61, 0xaa, 0x72, 0x18, 0x84,
  1399. - 0x02, 0x23, 0x23, 0xab, 0x63, 0x89, 0x51, 0xb3,
  1400. - 0xe7, 0x8b, 0x72, 0x90, 0x4c, 0xe8, 0xfb, 0xc0};
  1401. - u32 len = 1200;
  1402. - struct ieee80211_hw *hw = sc->hw;
  1403. - struct ieee80211_hdr *hdr;
  1404. - struct ieee80211_tx_info *tx_info;
  1405. - struct sk_buff *skb;
  1406. -
  1407. - skb = alloc_skb(len, GFP_KERNEL);
  1408. - if (!skb)
  1409. - return NULL;
  1410. -
  1411. - skb_put(skb, len);
  1412. -
  1413. - memset(skb->data, 0, len);
  1414. -
  1415. - hdr = (struct ieee80211_hdr *)skb->data;
  1416. - hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA);
  1417. - hdr->duration_id = 0;
  1418. -
  1419. - memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  1420. - memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  1421. - memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  1422. -
  1423. - hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  1424. -
  1425. - tx_info = IEEE80211_SKB_CB(skb);
  1426. - memset(tx_info, 0, sizeof(*tx_info));
  1427. - tx_info->band = hw->conf.chandef.chan->band;
  1428. - tx_info->flags = IEEE80211_TX_CTL_NO_ACK;
  1429. - tx_info->control.vif = sc->tx99_vif;
  1430. -
  1431. - memcpy(skb->data + sizeof(*hdr), PN9Data, sizeof(PN9Data));
  1432. -
  1433. - return skb;
  1434. -}
  1435. -
  1436. -void ath9k_tx99_deinit(struct ath_softc *sc)
  1437. -{
  1438. - ath_reset(sc);
  1439. -
  1440. - ath9k_ps_wakeup(sc);
  1441. - ath9k_tx99_stop(sc);
  1442. - ath9k_ps_restore(sc);
  1443. -}
  1444. -
  1445. -int ath9k_tx99_init(struct ath_softc *sc)
  1446. -{
  1447. - struct ieee80211_hw *hw = sc->hw;
  1448. - struct ath_hw *ah = sc->sc_ah;
  1449. - struct ath_common *common = ath9k_hw_common(ah);
  1450. - struct ath_tx_control txctl;
  1451. - int r;
  1452. -
  1453. - if (sc->sc_flags & SC_OP_INVALID) {
  1454. - ath_err(common,
  1455. - "driver is in invalid state unable to use TX99");
  1456. - return -EINVAL;
  1457. - }
  1458. -
  1459. - sc->tx99_skb = ath9k_build_tx99_skb(sc);
  1460. - if (!sc->tx99_skb)
  1461. - return -ENOMEM;
  1462. -
  1463. - memset(&txctl, 0, sizeof(txctl));
  1464. - txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO];
  1465. -
  1466. - ath_reset(sc);
  1467. -
  1468. - ath9k_ps_wakeup(sc);
  1469. -
  1470. - ath9k_hw_disable_interrupts(ah);
  1471. - atomic_set(&ah->intr_ref_cnt, -1);
  1472. - ath_drain_all_txq(sc);
  1473. - ath_stoprecv(sc);
  1474. -
  1475. - sc->tx99_state = true;
  1476. -
  1477. - ieee80211_stop_queues(hw);
  1478. -
  1479. - if (sc->tx99_power == MAX_RATE_POWER + 1)
  1480. - sc->tx99_power = MAX_RATE_POWER;
  1481. -
  1482. - ath9k_hw_tx99_set_txpower(ah, sc->tx99_power);
  1483. - r = ath9k_tx99_send(sc, sc->tx99_skb, &txctl);
  1484. - if (r) {
  1485. - ath_dbg(common, XMIT, "Failed to xmit TX99 skb\n");
  1486. - return r;
  1487. - }
  1488. -
  1489. - ath_dbg(common, XMIT, "TX99 xmit started using %d ( %ddBm)\n",
  1490. - sc->tx99_power,
  1491. - sc->tx99_power / 2);
  1492. -
  1493. - /* We leave the harware awake as it will be chugging on */
  1494. -
  1495. - return 0;
  1496. -}
  1497. -
  1498. struct ieee80211_ops ath9k_ops = {
  1499. .tx = ath9k_tx,
  1500. .start = ath9k_start,
  1501. @@ -2531,7 +2100,7 @@ struct ieee80211_ops ath9k_ops = {
  1502. .set_antenna = ath9k_set_antenna,
  1503. .get_antenna = ath9k_get_antenna,
  1504. -#ifdef CONFIG_PM_SLEEP
  1505. +#ifdef CONFIG_ATH9K_WOW
  1506. .suspend = ath9k_suspend,
  1507. .resume = ath9k_resume,
  1508. .set_wakeup = ath9k_set_wakeup,
  1509. --- a/drivers/net/wireless/ath/ath9k/wow.c
  1510. +++ b/drivers/net/wireless/ath/ath9k/wow.c
  1511. @@ -1,5 +1,5 @@
  1512. /*
  1513. - * Copyright (c) 2012 Qualcomm Atheros, Inc.
  1514. + * Copyright (c) 2013 Qualcomm Atheros, Inc.
  1515. *
  1516. * Permission to use, copy, modify, and/or distribute this software for any
  1517. * purpose with or without fee is hereby granted, provided that the above
  1518. @@ -14,409 +14,348 @@
  1519. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  1520. */
  1521. -#include <linux/export.h>
  1522. #include "ath9k.h"
  1523. -#include "reg.h"
  1524. -#include "hw-ops.h"
  1525. -const char *ath9k_hw_wow_event_to_string(u32 wow_event)
  1526. +static const struct wiphy_wowlan_support ath9k_wowlan_support = {
  1527. + .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
  1528. + .n_patterns = MAX_NUM_USER_PATTERN,
  1529. + .pattern_min_len = 1,
  1530. + .pattern_max_len = MAX_PATTERN_SIZE,
  1531. +};
  1532. +
  1533. +static void ath9k_wow_map_triggers(struct ath_softc *sc,
  1534. + struct cfg80211_wowlan *wowlan,
  1535. + u32 *wow_triggers)
  1536. {
  1537. - if (wow_event & AH_WOW_MAGIC_PATTERN_EN)
  1538. - return "Magic pattern";
  1539. - if (wow_event & AH_WOW_USER_PATTERN_EN)
  1540. - return "User pattern";
  1541. - if (wow_event & AH_WOW_LINK_CHANGE)
  1542. - return "Link change";
  1543. - if (wow_event & AH_WOW_BEACON_MISS)
  1544. - return "Beacon miss";
  1545. + if (wowlan->disconnect)
  1546. + *wow_triggers |= AH_WOW_LINK_CHANGE |
  1547. + AH_WOW_BEACON_MISS;
  1548. + if (wowlan->magic_pkt)
  1549. + *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
  1550. +
  1551. + if (wowlan->n_patterns)
  1552. + *wow_triggers |= AH_WOW_USER_PATTERN_EN;
  1553. +
  1554. + sc->wow_enabled = *wow_triggers;
  1555. - return "unknown reason";
  1556. }
  1557. -EXPORT_SYMBOL(ath9k_hw_wow_event_to_string);
  1558. -static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
  1559. +static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
  1560. {
  1561. + struct ath_hw *ah = sc->sc_ah;
  1562. struct ath_common *common = ath9k_hw_common(ah);
  1563. + int pattern_count = 0;
  1564. + int i, byte_cnt;
  1565. + u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
  1566. + u8 dis_deauth_mask[MAX_PATTERN_SIZE];
  1567. - REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
  1568. + memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
  1569. + memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
  1570. - /* set rx disable bit */
  1571. - REG_WRITE(ah, AR_CR, AR_CR_RXD);
  1572. + /*
  1573. + * Create Dissassociate / Deauthenticate packet filter
  1574. + *
  1575. + * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
  1576. + * +--------------+----------+---------+--------+--------+----
  1577. + * + Frame Control+ Duration + DA + SA + BSSID +
  1578. + * +--------------+----------+---------+--------+--------+----
  1579. + *
  1580. + * The above is the management frame format for disassociate/
  1581. + * deauthenticate pattern, from this we need to match the first byte
  1582. + * of 'Frame Control' and DA, SA, and BSSID fields
  1583. + * (skipping 2nd byte of FC and Duration feild.
  1584. + *
  1585. + * Disassociate pattern
  1586. + * --------------------
  1587. + * Frame control = 00 00 1010
  1588. + * DA, SA, BSSID = x:x:x:x:x:x
  1589. + * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1590. + * | x:x:x:x:x:x -- 22 bytes
  1591. + *
  1592. + * Deauthenticate pattern
  1593. + * ----------------------
  1594. + * Frame control = 00 00 1100
  1595. + * DA, SA, BSSID = x:x:x:x:x:x
  1596. + * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1597. + * | x:x:x:x:x:x -- 22 bytes
  1598. + */
  1599. - if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
  1600. - ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
  1601. - REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
  1602. - return;
  1603. - }
  1604. + /* Create Disassociate Pattern first */
  1605. - REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
  1606. -}
  1607. + byte_cnt = 0;
  1608. -static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
  1609. -{
  1610. - struct ath_common *common = ath9k_hw_common(ah);
  1611. - u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
  1612. - u32 ctl[13] = {0};
  1613. - u32 data_word[KAL_NUM_DATA_WORDS];
  1614. - u8 i;
  1615. - u32 wow_ka_data_word0;
  1616. -
  1617. - memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
  1618. - memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
  1619. -
  1620. - /* set the transmit buffer */
  1621. - ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16));
  1622. - ctl[1] = 0;
  1623. - ctl[3] = 0xb; /* OFDM_6M hardware value for this rate */
  1624. - ctl[4] = 0;
  1625. - ctl[7] = (ah->txchainmask) << 2;
  1626. - ctl[2] = 0xf << 16; /* tx_tries 0 */
  1627. -
  1628. - for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
  1629. - REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
  1630. -
  1631. - REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
  1632. -
  1633. - data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) |
  1634. - (KAL_TO_DS << 8) | (KAL_DURATION_ID << 16);
  1635. - data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
  1636. - (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
  1637. - data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
  1638. - (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
  1639. - data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
  1640. - (sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
  1641. - data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
  1642. - (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
  1643. - data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
  1644. -
  1645. - if (AR_SREV_9462_20(ah)) {
  1646. - /* AR9462 2.0 has an extra descriptor word (time based
  1647. - * discard) compared to other chips */
  1648. - REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
  1649. - wow_ka_data_word0 = AR_WOW_TXBUF(13);
  1650. - } else {
  1651. - wow_ka_data_word0 = AR_WOW_TXBUF(12);
  1652. - }
  1653. + /* Fill out the mask with all FF's */
  1654. - for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
  1655. - REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
  1656. + for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
  1657. + dis_deauth_mask[i] = 0xff;
  1658. -}
  1659. + /* copy the first byte of frame control field */
  1660. + dis_deauth_pattern[byte_cnt] = 0xa0;
  1661. + byte_cnt++;
  1662. -void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
  1663. - u8 *user_mask, int pattern_count,
  1664. - int pattern_len)
  1665. -{
  1666. - int i;
  1667. - u32 pattern_val, mask_val;
  1668. - u32 set, clr;
  1669. + /* skip 2nd byte of frame control and Duration field */
  1670. + byte_cnt += 3;
  1671. - /* FIXME: should check count by querying the hardware capability */
  1672. - if (pattern_count >= MAX_NUM_PATTERN)
  1673. - return;
  1674. + /*
  1675. + * need not match the destination mac address, it can be a broadcast
  1676. + * mac address or an unicast to this station
  1677. + */
  1678. + byte_cnt += 6;
  1679. - REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
  1680. + /* copy the source mac address */
  1681. + memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1682. - /* set the registers for pattern */
  1683. - for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
  1684. - memcpy(&pattern_val, user_pattern, 4);
  1685. - REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
  1686. - pattern_val);
  1687. - user_pattern += 4;
  1688. - }
  1689. + byte_cnt += 6;
  1690. - /* set the registers for mask */
  1691. - for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
  1692. - memcpy(&mask_val, user_mask, 4);
  1693. - REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
  1694. - user_mask += 4;
  1695. - }
  1696. + /* copy the bssid, its same as the source mac address */
  1697. - /* set the pattern length to be matched
  1698. - *
  1699. - * AR_WOW_LENGTH1_REG1
  1700. - * bit 31:24 pattern 0 length
  1701. - * bit 23:16 pattern 1 length
  1702. - * bit 15:8 pattern 2 length
  1703. - * bit 7:0 pattern 3 length
  1704. - *
  1705. - * AR_WOW_LENGTH1_REG2
  1706. - * bit 31:24 pattern 4 length
  1707. - * bit 23:16 pattern 5 length
  1708. - * bit 15:8 pattern 6 length
  1709. - * bit 7:0 pattern 7 length
  1710. - *
  1711. - * the below logic writes out the new
  1712. - * pattern length for the corresponding
  1713. - * pattern_count, while masking out the
  1714. - * other fields
  1715. - */
  1716. + memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1717. - ah->wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
  1718. + /* Create Disassociate pattern mask */
  1719. - if (pattern_count < 4) {
  1720. - /* Pattern 0-3 uses AR_WOW_LENGTH1 register */
  1721. - set = (pattern_len & AR_WOW_LENGTH_MAX) <<
  1722. - AR_WOW_LEN1_SHIFT(pattern_count);
  1723. - clr = AR_WOW_LENGTH1_MASK(pattern_count);
  1724. - REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
  1725. - } else {
  1726. - /* Pattern 4-7 uses AR_WOW_LENGTH2 register */
  1727. - set = (pattern_len & AR_WOW_LENGTH_MAX) <<
  1728. - AR_WOW_LEN2_SHIFT(pattern_count);
  1729. - clr = AR_WOW_LENGTH2_MASK(pattern_count);
  1730. - REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
  1731. - }
  1732. + dis_deauth_mask[0] = 0xfe;
  1733. + dis_deauth_mask[1] = 0x03;
  1734. + dis_deauth_mask[2] = 0xc0;
  1735. -}
  1736. -EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
  1737. + ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
  1738. -u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
  1739. -{
  1740. - u32 wow_status = 0;
  1741. - u32 val = 0, rval;
  1742. + ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1743. + pattern_count, byte_cnt);
  1744. + pattern_count++;
  1745. /*
  1746. - * read the WoW status register to know
  1747. - * the wakeup reason
  1748. + * for de-authenticate pattern, only the first byte of the frame
  1749. + * control field gets changed from 0xA0 to 0xC0
  1750. */
  1751. - rval = REG_READ(ah, AR_WOW_PATTERN);
  1752. - val = AR_WOW_STATUS(rval);
  1753. + dis_deauth_pattern[0] = 0xC0;
  1754. - /*
  1755. - * mask only the WoW events that we have enabled. Sometimes
  1756. - * we have spurious WoW events from the AR_WOW_PATTERN
  1757. - * register. This mask will clean it up.
  1758. - */
  1759. + ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1760. + pattern_count, byte_cnt);
  1761. - val &= ah->wow_event_mask;
  1762. +}
  1763. - if (val) {
  1764. - if (val & AR_WOW_MAGIC_PAT_FOUND)
  1765. - wow_status |= AH_WOW_MAGIC_PATTERN_EN;
  1766. - if (AR_WOW_PATTERN_FOUND(val))
  1767. - wow_status |= AH_WOW_USER_PATTERN_EN;
  1768. - if (val & AR_WOW_KEEP_ALIVE_FAIL)
  1769. - wow_status |= AH_WOW_LINK_CHANGE;
  1770. - if (val & AR_WOW_BEACON_FAIL)
  1771. - wow_status |= AH_WOW_BEACON_MISS;
  1772. - }
  1773. +static void ath9k_wow_add_pattern(struct ath_softc *sc,
  1774. + struct cfg80211_wowlan *wowlan)
  1775. +{
  1776. + struct ath_hw *ah = sc->sc_ah;
  1777. + struct ath9k_wow_pattern *wow_pattern = NULL;
  1778. + struct cfg80211_pkt_pattern *patterns = wowlan->patterns;
  1779. + int mask_len;
  1780. + s8 i = 0;
  1781. +
  1782. + if (!wowlan->n_patterns)
  1783. + return;
  1784. /*
  1785. - * set and clear WOW_PME_CLEAR registers for the chip to
  1786. - * generate next wow signal.
  1787. - * disable D3 before accessing other registers ?
  1788. + * Add the new user configured patterns
  1789. */
  1790. + for (i = 0; i < wowlan->n_patterns; i++) {
  1791. - /* do we need to check the bit value 0x01000000 (7-10) ?? */
  1792. - REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR,
  1793. - AR_PMCTRL_PWR_STATE_D1D3);
  1794. + wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
  1795. - /*
  1796. - * clear all events
  1797. - */
  1798. - REG_WRITE(ah, AR_WOW_PATTERN,
  1799. - AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
  1800. + if (!wow_pattern)
  1801. + return;
  1802. - /*
  1803. - * restore the beacon threshold to init value
  1804. - */
  1805. - REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
  1806. + /*
  1807. + * TODO: convert the generic user space pattern to
  1808. + * appropriate chip specific/802.11 pattern.
  1809. + */
  1810. - /*
  1811. - * Restore the way the PCI-E reset, Power-On-Reset, external
  1812. - * PCIE_POR_SHORT pins are tied to its original value.
  1813. - * Previously just before WoW sleep, we untie the PCI-E
  1814. - * reset to our Chip's Power On Reset so that any PCI-E
  1815. - * reset from the bus will not reset our chip
  1816. - */
  1817. - if (ah->is_pciexpress)
  1818. - ath9k_hw_configpcipowersave(ah, false);
  1819. + mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
  1820. + memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
  1821. + memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
  1822. + memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
  1823. + patterns[i].pattern_len);
  1824. + memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
  1825. + wow_pattern->pattern_len = patterns[i].pattern_len;
  1826. +
  1827. + /*
  1828. + * just need to take care of deauth and disssoc pattern,
  1829. + * make sure we don't overwrite them.
  1830. + */
  1831. +
  1832. + ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
  1833. + wow_pattern->mask_bytes,
  1834. + i + 2,
  1835. + wow_pattern->pattern_len);
  1836. + kfree(wow_pattern);
  1837. - ah->wow_event_mask = 0;
  1838. + }
  1839. - return wow_status;
  1840. }
  1841. -EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
  1842. -void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
  1843. +int ath9k_suspend(struct ieee80211_hw *hw,
  1844. + struct cfg80211_wowlan *wowlan)
  1845. {
  1846. - u32 wow_event_mask;
  1847. - u32 set, clr;
  1848. + struct ath_softc *sc = hw->priv;
  1849. + struct ath_hw *ah = sc->sc_ah;
  1850. + struct ath_common *common = ath9k_hw_common(ah);
  1851. + u32 wow_triggers_enabled = 0;
  1852. + int ret = 0;
  1853. - /*
  1854. - * wow_event_mask is a mask to the AR_WOW_PATTERN register to
  1855. - * indicate which WoW events we have enabled. The WoW events
  1856. - * are from the 'pattern_enable' in this function and
  1857. - * 'pattern_count' of ath9k_hw_wow_apply_pattern()
  1858. - */
  1859. - wow_event_mask = ah->wow_event_mask;
  1860. + mutex_lock(&sc->mutex);
  1861. - /*
  1862. - * Untie Power-on-Reset from the PCI-E-Reset. When we are in
  1863. - * WOW sleep, we do want the Reset from the PCI-E to disturb
  1864. - * our hw state
  1865. - */
  1866. - if (ah->is_pciexpress) {
  1867. - /*
  1868. - * we need to untie the internal POR (power-on-reset)
  1869. - * to the external PCI-E reset. We also need to tie
  1870. - * the PCI-E Phy reset to the PCI-E reset.
  1871. - */
  1872. - set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
  1873. - clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
  1874. - REG_RMW(ah, AR_WA, set, clr);
  1875. + ath_cancel_work(sc);
  1876. + ath_stop_ani(sc);
  1877. + del_timer_sync(&sc->rx_poll_timer);
  1878. +
  1879. + if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1880. + ath_dbg(common, ANY, "Device not present\n");
  1881. + ret = -EINVAL;
  1882. + goto fail_wow;
  1883. }
  1884. - /*
  1885. - * set the power states appropriately and enable PME
  1886. - */
  1887. - set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
  1888. - AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
  1889. + if (WARN_ON(!wowlan)) {
  1890. + ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
  1891. + ret = -EINVAL;
  1892. + goto fail_wow;
  1893. + }
  1894. - /*
  1895. - * set and clear WOW_PME_CLEAR registers for the chip
  1896. - * to generate next wow signal.
  1897. - */
  1898. - REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
  1899. - clr = AR_PMCTRL_WOW_PME_CLR;
  1900. - REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
  1901. + if (!device_can_wakeup(sc->dev)) {
  1902. + ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
  1903. + ret = 1;
  1904. + goto fail_wow;
  1905. + }
  1906. /*
  1907. - * Setup for:
  1908. - * - beacon misses
  1909. - * - magic pattern
  1910. - * - keep alive timeout
  1911. - * - pattern matching
  1912. + * none of the sta vifs are associated
  1913. + * and we are not currently handling multivif
  1914. + * cases, for instance we have to seperately
  1915. + * configure 'keep alive frame' for each
  1916. + * STA.
  1917. */
  1918. - /*
  1919. - * Program default values for pattern backoff, aifs/slot/KAL count,
  1920. - * beacon miss timeout, KAL timeout, etc.
  1921. - */
  1922. - set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
  1923. - REG_SET_BIT(ah, AR_WOW_PATTERN, set);
  1924. + if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1925. + ath_dbg(common, WOW, "None of the STA vifs are associated\n");
  1926. + ret = 1;
  1927. + goto fail_wow;
  1928. + }
  1929. +
  1930. + if (sc->nvifs > 1) {
  1931. + ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
  1932. + ret = 1;
  1933. + goto fail_wow;
  1934. + }
  1935. - set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
  1936. - AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
  1937. - AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
  1938. - REG_SET_BIT(ah, AR_WOW_COUNT, set);
  1939. -
  1940. - if (pattern_enable & AH_WOW_BEACON_MISS)
  1941. - set = AR_WOW_BEACON_TIMO;
  1942. - /* We are not using beacon miss, program a large value */
  1943. - else
  1944. - set = AR_WOW_BEACON_TIMO_MAX;
  1945. + ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
  1946. - REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
  1947. + ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
  1948. + wow_triggers_enabled);
  1949. - /*
  1950. - * Keep alive timo in ms except AR9280
  1951. - */
  1952. - if (!pattern_enable)
  1953. - set = AR_WOW_KEEP_ALIVE_NEVER;
  1954. - else
  1955. - set = KAL_TIMEOUT * 32;
  1956. + ath9k_ps_wakeup(sc);
  1957. - REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
  1958. + ath9k_stop_btcoex(sc);
  1959. /*
  1960. - * Keep alive delay in us. based on 'power on clock',
  1961. - * therefore in usec
  1962. + * Enable wake up on recieving disassoc/deauth
  1963. + * frame by default.
  1964. */
  1965. - set = KAL_DELAY * 1000;
  1966. - REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
  1967. + ath9k_wow_add_disassoc_deauth_pattern(sc);
  1968. - /*
  1969. - * Create keep alive pattern to respond to beacons
  1970. - */
  1971. - ath9k_wow_create_keep_alive_pattern(ah);
  1972. + if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
  1973. + ath9k_wow_add_pattern(sc, wowlan);
  1974. + spin_lock_bh(&sc->sc_pcu_lock);
  1975. /*
  1976. - * Configure MAC WoW Registers
  1977. + * To avoid false wake, we enable beacon miss interrupt only
  1978. + * when we go to sleep. We save the current interrupt mask
  1979. + * so we can restore it after the system wakes up
  1980. */
  1981. - set = 0;
  1982. - /* Send keep alive timeouts anyway */
  1983. - clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
  1984. -
  1985. - if (pattern_enable & AH_WOW_LINK_CHANGE)
  1986. - wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
  1987. - else
  1988. - set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
  1989. + sc->wow_intr_before_sleep = ah->imask;
  1990. + ah->imask &= ~ATH9K_INT_GLOBAL;
  1991. + ath9k_hw_disable_interrupts(ah);
  1992. + ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
  1993. + ath9k_hw_set_interrupts(ah);
  1994. + ath9k_hw_enable_interrupts(ah);
  1995. - set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
  1996. - REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
  1997. + spin_unlock_bh(&sc->sc_pcu_lock);
  1998. /*
  1999. - * we are relying on a bmiss failure. ensure we have
  2000. - * enough threshold to prevent false positives
  2001. + * we can now sync irq and kill any running tasklets, since we already
  2002. + * disabled interrupts and not holding a spin lock
  2003. */
  2004. - REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
  2005. - AR_WOW_BMISSTHRESHOLD);
  2006. + synchronize_irq(sc->irq);
  2007. + tasklet_kill(&sc->intr_tq);
  2008. +
  2009. + ath9k_hw_wow_enable(ah, wow_triggers_enabled);
  2010. - set = 0;
  2011. - clr = 0;
  2012. + ath9k_ps_restore(sc);
  2013. + ath_dbg(common, ANY, "WoW enabled in ath9k\n");
  2014. + atomic_inc(&sc->wow_sleep_proc_intr);
  2015. - if (pattern_enable & AH_WOW_BEACON_MISS) {
  2016. - set = AR_WOW_BEACON_FAIL_EN;
  2017. - wow_event_mask |= AR_WOW_BEACON_FAIL;
  2018. - } else {
  2019. - clr = AR_WOW_BEACON_FAIL_EN;
  2020. +fail_wow:
  2021. + mutex_unlock(&sc->mutex);
  2022. + return ret;
  2023. +}
  2024. +
  2025. +int ath9k_resume(struct ieee80211_hw *hw)
  2026. +{
  2027. + struct ath_softc *sc = hw->priv;
  2028. + struct ath_hw *ah = sc->sc_ah;
  2029. + struct ath_common *common = ath9k_hw_common(ah);
  2030. + u32 wow_status;
  2031. +
  2032. + mutex_lock(&sc->mutex);
  2033. +
  2034. + ath9k_ps_wakeup(sc);
  2035. +
  2036. + spin_lock_bh(&sc->sc_pcu_lock);
  2037. +
  2038. + ath9k_hw_disable_interrupts(ah);
  2039. + ah->imask = sc->wow_intr_before_sleep;
  2040. + ath9k_hw_set_interrupts(ah);
  2041. + ath9k_hw_enable_interrupts(ah);
  2042. +
  2043. + spin_unlock_bh(&sc->sc_pcu_lock);
  2044. +
  2045. + wow_status = ath9k_hw_wow_wakeup(ah);
  2046. +
  2047. + if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
  2048. + /*
  2049. + * some devices may not pick beacon miss
  2050. + * as the reason they woke up so we add
  2051. + * that here for that shortcoming.
  2052. + */
  2053. + wow_status |= AH_WOW_BEACON_MISS;
  2054. + atomic_dec(&sc->wow_got_bmiss_intr);
  2055. + ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
  2056. }
  2057. - REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
  2058. + atomic_dec(&sc->wow_sleep_proc_intr);
  2059. - set = 0;
  2060. - clr = 0;
  2061. - /*
  2062. - * Enable the magic packet registers
  2063. - */
  2064. - if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
  2065. - set = AR_WOW_MAGIC_EN;
  2066. - wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
  2067. - } else {
  2068. - clr = AR_WOW_MAGIC_EN;
  2069. + if (wow_status) {
  2070. + ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
  2071. + ath9k_hw_wow_event_to_string(wow_status), wow_status);
  2072. }
  2073. - set |= AR_WOW_MAC_INTR_EN;
  2074. - REG_RMW(ah, AR_WOW_PATTERN, set, clr);
  2075. - REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
  2076. - AR_WOW_PATTERN_SUPPORTED);
  2077. + ath_restart_work(sc);
  2078. + ath9k_start_btcoex(sc);
  2079. - /*
  2080. - * Set the power states appropriately and enable PME
  2081. - */
  2082. - clr = 0;
  2083. - set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
  2084. - AR_PMCTRL_PWR_PM_CTRL_ENA;
  2085. + ath9k_ps_restore(sc);
  2086. + mutex_unlock(&sc->mutex);
  2087. - clr = AR_PCIE_PM_CTRL_ENA;
  2088. - REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
  2089. + return 0;
  2090. +}
  2091. - /*
  2092. - * this is needed to prevent the chip waking up
  2093. - * the host within 3-4 seconds with certain
  2094. - * platform/BIOS. The fix is to enable
  2095. - * D1 & D3 to match original definition and
  2096. - * also match the OTP value. Anyway this
  2097. - * is more related to SW WOW.
  2098. - */
  2099. - clr = AR_PMCTRL_PWR_STATE_D1D3;
  2100. - REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
  2101. +void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  2102. +{
  2103. + struct ath_softc *sc = hw->priv;
  2104. - set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
  2105. - REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
  2106. + mutex_lock(&sc->mutex);
  2107. + device_init_wakeup(sc->dev, 1);
  2108. + device_set_wakeup_enable(sc->dev, enabled);
  2109. + mutex_unlock(&sc->mutex);
  2110. +}
  2111. - REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
  2112. +void ath9k_init_wow(struct ieee80211_hw *hw)
  2113. +{
  2114. + struct ath_softc *sc = hw->priv;
  2115. - /* to bring down WOW power low margin */
  2116. - set = BIT(13);
  2117. - REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
  2118. - /* HW WoW */
  2119. - clr = BIT(5);
  2120. - REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
  2121. + if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) &&
  2122. + (sc->driver_data & ATH9K_PCI_WOW) &&
  2123. + device_can_wakeup(sc->dev))
  2124. + hw->wiphy->wowlan = &ath9k_wowlan_support;
  2125. - ath9k_hw_set_powermode_wow_sleep(ah);
  2126. - ah->wow_event_mask = wow_event_mask;
  2127. + atomic_set(&sc->wow_sleep_proc_intr, -1);
  2128. + atomic_set(&sc->wow_got_bmiss_intr, -1);
  2129. }
  2130. -EXPORT_SYMBOL(ath9k_hw_wow_enable);
  2131. --- a/drivers/net/wireless/ath/ath9k/xmit.c
  2132. +++ b/drivers/net/wireless/ath/ath9k/xmit.c
  2133. @@ -1786,6 +1786,9 @@ bool ath_drain_all_txq(struct ath_softc
  2134. if (!ATH_TXQ_SETUP(sc, i))
  2135. continue;
  2136. + if (!sc->tx.txq[i].axq_depth)
  2137. + continue;
  2138. +
  2139. if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
  2140. npend |= BIT(i);
  2141. }
  2142. @@ -2749,6 +2752,8 @@ void ath_tx_node_cleanup(struct ath_soft
  2143. }
  2144. }
  2145. +#ifdef CONFIG_ATH9K_TX99
  2146. +
  2147. int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
  2148. struct ath_tx_control *txctl)
  2149. {
  2150. @@ -2791,3 +2796,5 @@ int ath9k_tx99_send(struct ath_softc *sc
  2151. return 0;
  2152. }
  2153. +
  2154. +#endif /* CONFIG_ATH9K_TX99 */
  2155. --- a/drivers/net/wireless/ath/regd.c
  2156. +++ b/drivers/net/wireless/ath/regd.c
  2157. @@ -37,17 +37,17 @@ static int __ath_regd_init(struct ath_re
  2158. /* We enable active scan on these a case by case basis by regulatory domain */
  2159. #define ATH9K_2GHZ_CH12_13 REG_RULE(2467-10, 2472+10, 40, 0, 20,\
  2160. - NL80211_RRF_PASSIVE_SCAN)
  2161. + NL80211_RRF_NO_IR)
  2162. #define ATH9K_2GHZ_CH14 REG_RULE(2484-10, 2484+10, 40, 0, 20,\
  2163. - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_OFDM)
  2164. + NL80211_RRF_NO_IR | NL80211_RRF_NO_OFDM)
  2165. /* We allow IBSS on these on a case by case basis by regulatory domain */
  2166. #define ATH9K_5GHZ_5150_5350 REG_RULE(5150-10, 5350+10, 80, 0, 30,\
  2167. - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
  2168. + NL80211_RRF_NO_IR)
  2169. #define ATH9K_5GHZ_5470_5850 REG_RULE(5470-10, 5850+10, 80, 0, 30,\
  2170. - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
  2171. + NL80211_RRF_NO_IR)
  2172. #define ATH9K_5GHZ_5725_5850 REG_RULE(5725-10, 5850+10, 80, 0, 30,\
  2173. - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS)
  2174. + NL80211_RRF_NO_IR)
  2175. #define ATH9K_2GHZ_ALL ATH9K_2GHZ_CH01_11, \
  2176. ATH9K_2GHZ_CH12_13, \
  2177. @@ -224,17 +224,16 @@ ath_reg_apply_beaconing_flags(struct wip
  2178. * regulatory_hint().
  2179. */
  2180. if (!(reg_rule->flags &
  2181. - NL80211_RRF_NO_IBSS))
  2182. + NL80211_RRF_NO_IR))
  2183. ch->flags &=
  2184. - ~IEEE80211_CHAN_NO_IBSS;
  2185. + ~IEEE80211_CHAN_NO_IR;
  2186. if (!(reg_rule->flags &
  2187. - NL80211_RRF_PASSIVE_SCAN))
  2188. + NL80211_RRF_NO_IR))
  2189. ch->flags &=
  2190. - ~IEEE80211_CHAN_PASSIVE_SCAN;
  2191. + ~IEEE80211_CHAN_NO_IR;
  2192. } else {
  2193. if (ch->beacon_found)
  2194. - ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
  2195. - IEEE80211_CHAN_PASSIVE_SCAN);
  2196. + ch->flags &= ~IEEE80211_CHAN_NO_IR;
  2197. }
  2198. }
  2199. }
  2200. @@ -260,11 +259,11 @@ ath_reg_apply_active_scan_flags(struct w
  2201. */
  2202. if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
  2203. ch = &sband->channels[11]; /* CH 12 */
  2204. - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
  2205. - ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
  2206. + if (ch->flags & IEEE80211_CHAN_NO_IR)
  2207. + ch->flags &= ~IEEE80211_CHAN_NO_IR;
  2208. ch = &sband->channels[12]; /* CH 13 */
  2209. - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
  2210. - ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
  2211. + if (ch->flags & IEEE80211_CHAN_NO_IR)
  2212. + ch->flags &= ~IEEE80211_CHAN_NO_IR;
  2213. return;
  2214. }
  2215. @@ -278,17 +277,17 @@ ath_reg_apply_active_scan_flags(struct w
  2216. ch = &sband->channels[11]; /* CH 12 */
  2217. reg_rule = freq_reg_info(wiphy, ch->center_freq);
  2218. if (!IS_ERR(reg_rule)) {
  2219. - if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
  2220. - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
  2221. - ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
  2222. + if (!(reg_rule->flags & NL80211_RRF_NO_IR))
  2223. + if (ch->flags & IEEE80211_CHAN_NO_IR)
  2224. + ch->flags &= ~IEEE80211_CHAN_NO_IR;
  2225. }
  2226. ch = &sband->channels[12]; /* CH 13 */
  2227. reg_rule = freq_reg_info(wiphy, ch->center_freq);
  2228. if (!IS_ERR(reg_rule)) {
  2229. - if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
  2230. - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
  2231. - ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
  2232. + if (!(reg_rule->flags & NL80211_RRF_NO_IR))
  2233. + if (ch->flags & IEEE80211_CHAN_NO_IR)
  2234. + ch->flags &= ~IEEE80211_CHAN_NO_IR;
  2235. }
  2236. }
  2237. @@ -320,8 +319,8 @@ static void ath_reg_apply_radar_flags(st
  2238. */
  2239. if (!(ch->flags & IEEE80211_CHAN_DISABLED))
  2240. ch->flags |= IEEE80211_CHAN_RADAR |
  2241. - IEEE80211_CHAN_NO_IBSS |
  2242. - IEEE80211_CHAN_PASSIVE_SCAN;
  2243. + IEEE80211_CHAN_NO_IR |
  2244. + IEEE80211_CHAN_NO_IR;
  2245. }
  2246. }
  2247. --- a/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
  2248. +++ b/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
  2249. @@ -812,7 +812,7 @@ static s32 brcmf_p2p_run_escan(struct br
  2250. struct ieee80211_channel *chan = request->channels[i];
  2251. if (chan->flags & (IEEE80211_CHAN_RADAR |
  2252. - IEEE80211_CHAN_PASSIVE_SCAN))
  2253. + IEEE80211_CHAN_NO_IR))
  2254. continue;
  2255. chanspecs[i] = channel_to_chanspec(&p2p->cfg->d11inf,
  2256. --- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
  2257. +++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
  2258. @@ -202,9 +202,9 @@ static struct ieee80211_supported_band _
  2259. /* This is to override regulatory domains defined in cfg80211 module (reg.c)
  2260. * By default world regulatory domain defined in reg.c puts the flags
  2261. - * NL80211_RRF_PASSIVE_SCAN and NL80211_RRF_NO_IBSS for 5GHz channels (for
  2262. - * 36..48 and 149..165). With respect to these flags, wpa_supplicant doesn't
  2263. - * start p2p operations on 5GHz channels. All the changes in world regulatory
  2264. + * NL80211_RRF_NO_IR for 5GHz channels (for * 36..48 and 149..165).
  2265. + * With respect to these flags, wpa_supplicant doesn't * start p2p
  2266. + * operations on 5GHz channels. All the changes in world regulatory
  2267. * domain are to be done here.
  2268. */
  2269. static const struct ieee80211_regdomain brcmf_regdom = {
  2270. @@ -5197,10 +5197,10 @@ static s32 brcmf_construct_reginfo(struc
  2271. if (channel & WL_CHAN_RADAR)
  2272. band_chan_arr[index].flags |=
  2273. (IEEE80211_CHAN_RADAR |
  2274. - IEEE80211_CHAN_NO_IBSS);
  2275. + IEEE80211_CHAN_NO_IR);
  2276. if (channel & WL_CHAN_PASSIVE)
  2277. band_chan_arr[index].flags |=
  2278. - IEEE80211_CHAN_PASSIVE_SCAN;
  2279. + IEEE80211_CHAN_NO_IR;
  2280. }
  2281. }
  2282. if (!update)
  2283. --- a/drivers/net/wireless/brcm80211/brcmsmac/channel.c
  2284. +++ b/drivers/net/wireless/brcm80211/brcmsmac/channel.c
  2285. @@ -59,23 +59,20 @@
  2286. #define BRCM_2GHZ_2412_2462 REG_RULE(2412-10, 2462+10, 40, 0, 19, 0)
  2287. #define BRCM_2GHZ_2467_2472 REG_RULE(2467-10, 2472+10, 20, 0, 19, \
  2288. - NL80211_RRF_PASSIVE_SCAN | \
  2289. - NL80211_RRF_NO_IBSS)
  2290. + NL80211_RRF_NO_IR)
  2291. #define BRCM_5GHZ_5180_5240 REG_RULE(5180-10, 5240+10, 40, 0, 21, \
  2292. - NL80211_RRF_PASSIVE_SCAN | \
  2293. - NL80211_RRF_NO_IBSS)
  2294. + NL80211_RRF_NO_IR)
  2295. #define BRCM_5GHZ_5260_5320 REG_RULE(5260-10, 5320+10, 40, 0, 21, \
  2296. - NL80211_RRF_PASSIVE_SCAN | \
  2297. + NL80211_RRF_NO_IR | \
  2298. NL80211_RRF_DFS | \
  2299. - NL80211_RRF_NO_IBSS)
  2300. + NL80211_RRF_NO_IR)
  2301. #define BRCM_5GHZ_5500_5700 REG_RULE(5500-10, 5700+10, 40, 0, 21, \
  2302. - NL80211_RRF_PASSIVE_SCAN | \
  2303. + NL80211_RRF_NO_IR | \
  2304. NL80211_RRF_DFS | \
  2305. - NL80211_RRF_NO_IBSS)
  2306. + NL80211_RRF_NO_IR)
  2307. #define BRCM_5GHZ_5745_5825 REG_RULE(5745-10, 5825+10, 40, 0, 21, \
  2308. - NL80211_RRF_PASSIVE_SCAN | \
  2309. - NL80211_RRF_NO_IBSS)
  2310. + NL80211_RRF_NO_IR)
  2311. static const struct ieee80211_regdomain brcms_regdom_x2 = {
  2312. .n_reg_rules = 6,
  2313. @@ -395,7 +392,7 @@ brcms_c_channel_set_chanspec(struct brcm
  2314. brcms_c_set_gmode(wlc, wlc->protection->gmode_user, false);
  2315. brcms_b_set_chanspec(wlc->hw, chanspec,
  2316. - !!(ch->flags & IEEE80211_CHAN_PASSIVE_SCAN),
  2317. + !!(ch->flags & IEEE80211_CHAN_NO_IR),
  2318. &txpwr);
  2319. }
  2320. @@ -657,8 +654,8 @@ static void brcms_reg_apply_radar_flags(
  2321. */
  2322. if (!(ch->flags & IEEE80211_CHAN_DISABLED))
  2323. ch->flags |= IEEE80211_CHAN_RADAR |
  2324. - IEEE80211_CHAN_NO_IBSS |
  2325. - IEEE80211_CHAN_PASSIVE_SCAN;
  2326. + IEEE80211_CHAN_NO_IR |
  2327. + IEEE80211_CHAN_NO_IR;
  2328. }
  2329. }
  2330. @@ -688,14 +685,13 @@ brcms_reg_apply_beaconing_flags(struct w
  2331. if (IS_ERR(rule))
  2332. continue;
  2333. - if (!(rule->flags & NL80211_RRF_NO_IBSS))
  2334. - ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
  2335. - if (!(rule->flags & NL80211_RRF_PASSIVE_SCAN))
  2336. + if (!(rule->flags & NL80211_RRF_NO_IR))
  2337. + ch->flags &= ~IEEE80211_CHAN_NO_IR;
  2338. + if (!(rule->flags & NL80211_RRF_NO_IR))
  2339. ch->flags &=
  2340. - ~IEEE80211_CHAN_PASSIVE_SCAN;
  2341. + ~IEEE80211_CHAN_NO_IR;
  2342. } else if (ch->beacon_found) {
  2343. - ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
  2344. - IEEE80211_CHAN_PASSIVE_SCAN);
  2345. + ch->flags &= ~IEEE80211_CHAN_NO_IR;
  2346. }
  2347. }
  2348. }
  2349. --- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
  2350. +++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
  2351. @@ -125,13 +125,13 @@ static struct ieee80211_channel brcms_2g
  2352. CHAN2GHZ(10, 2457, IEEE80211_CHAN_NO_HT40PLUS),
  2353. CHAN2GHZ(11, 2462, IEEE80211_CHAN_NO_HT40PLUS),
  2354. CHAN2GHZ(12, 2467,
  2355. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
  2356. + IEEE80211_CHAN_NO_IR |
  2357. IEEE80211_CHAN_NO_HT40PLUS),
  2358. CHAN2GHZ(13, 2472,
  2359. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
  2360. + IEEE80211_CHAN_NO_IR |
  2361. IEEE80211_CHAN_NO_HT40PLUS),
  2362. CHAN2GHZ(14, 2484,
  2363. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
  2364. + IEEE80211_CHAN_NO_IR |
  2365. IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS |
  2366. IEEE80211_CHAN_NO_OFDM)
  2367. };
  2368. @@ -144,51 +144,51 @@ static struct ieee80211_channel brcms_5g
  2369. CHAN5GHZ(48, IEEE80211_CHAN_NO_HT40PLUS),
  2370. /* UNII-2 */
  2371. CHAN5GHZ(52,
  2372. - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
  2373. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
  2374. + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
  2375. + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
  2376. CHAN5GHZ(56,
  2377. - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
  2378. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
  2379. + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
  2380. + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
  2381. CHAN5GHZ(60,
  2382. - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
  2383. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
  2384. + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
  2385. + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
  2386. CHAN5GHZ(64,
  2387. - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
  2388. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
  2389. + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
  2390. + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
  2391. /* MID */
  2392. CHAN5GHZ(100,
  2393. - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
  2394. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
  2395. + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
  2396. + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
  2397. CHAN5GHZ(104,
  2398. - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
  2399. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
  2400. + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
  2401. + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
  2402. CHAN5GHZ(108,
  2403. - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
  2404. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
  2405. + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
  2406. + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
  2407. CHAN5GHZ(112,
  2408. - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
  2409. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
  2410. + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
  2411. + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
  2412. CHAN5GHZ(116,
  2413. - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
  2414. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
  2415. + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
  2416. + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
  2417. CHAN5GHZ(120,
  2418. - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
  2419. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
  2420. + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
  2421. + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
  2422. CHAN5GHZ(124,
  2423. - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
  2424. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
  2425. + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
  2426. + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
  2427. CHAN5GHZ(128,
  2428. - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
  2429. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
  2430. + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
  2431. + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
  2432. CHAN5GHZ(132,
  2433. - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
  2434. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
  2435. + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
  2436. + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40MINUS),
  2437. CHAN5GHZ(136,
  2438. - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
  2439. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
  2440. + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
  2441. + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS),
  2442. CHAN5GHZ(140,
  2443. - IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
  2444. - IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS |
  2445. + IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IR |
  2446. + IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_NO_HT40PLUS |
  2447. IEEE80211_CHAN_NO_HT40MINUS),
  2448. /* UNII-3 */
  2449. CHAN5GHZ(149, IEEE80211_CHAN_NO_HT40MINUS),
  2450. --- a/drivers/net/wireless/cw1200/scan.c
  2451. +++ b/drivers/net/wireless/cw1200/scan.c
  2452. @@ -197,9 +197,9 @@ void cw1200_scan_work(struct work_struct
  2453. if ((*it)->band != first->band)
  2454. break;
  2455. if (((*it)->flags ^ first->flags) &
  2456. - IEEE80211_CHAN_PASSIVE_SCAN)
  2457. + IEEE80211_CHAN_NO_IR)
  2458. break;
  2459. - if (!(first->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
  2460. + if (!(first->flags & IEEE80211_CHAN_NO_IR) &&
  2461. (*it)->max_power != first->max_power)
  2462. break;
  2463. }
  2464. @@ -210,7 +210,7 @@ void cw1200_scan_work(struct work_struct
  2465. else
  2466. scan.max_tx_rate = WSM_TRANSMIT_RATE_1;
  2467. scan.num_probes =
  2468. - (first->flags & IEEE80211_CHAN_PASSIVE_SCAN) ? 0 : 2;
  2469. + (first->flags & IEEE80211_CHAN_NO_IR) ? 0 : 2;
  2470. scan.num_ssids = priv->scan.n_ssids;
  2471. scan.ssids = &priv->scan.ssids[0];
  2472. scan.num_channels = it - priv->scan.curr;
  2473. @@ -233,7 +233,7 @@ void cw1200_scan_work(struct work_struct
  2474. }
  2475. for (i = 0; i < scan.num_channels; ++i) {
  2476. scan.ch[i].number = priv->scan.curr[i]->hw_value;
  2477. - if (priv->scan.curr[i]->flags & IEEE80211_CHAN_PASSIVE_SCAN) {
  2478. + if (priv->scan.curr[i]->flags & IEEE80211_CHAN_NO_IR) {
  2479. scan.ch[i].min_chan_time = 50;
  2480. scan.ch[i].max_chan_time = 100;
  2481. } else {
  2482. @@ -241,7 +241,7 @@ void cw1200_scan_work(struct work_struct
  2483. scan.ch[i].max_chan_time = 25;
  2484. }
  2485. }
  2486. - if (!(first->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
  2487. + if (!(first->flags & IEEE80211_CHAN_NO_IR) &&
  2488. priv->scan.output_power != first->max_power) {
  2489. priv->scan.output_power = first->max_power;
  2490. wsm_set_output_power(priv,
  2491. --- a/drivers/net/wireless/ipw2x00/ipw2100.c
  2492. +++ b/drivers/net/wireless/ipw2x00/ipw2100.c
  2493. @@ -1934,10 +1934,10 @@ static int ipw2100_wdev_init(struct net_
  2494. bg_band->channels[i].max_power = geo->bg[i].max_power;
  2495. if (geo->bg[i].flags & LIBIPW_CH_PASSIVE_ONLY)
  2496. bg_band->channels[i].flags |=
  2497. - IEEE80211_CHAN_PASSIVE_SCAN;
  2498. + IEEE80211_CHAN_NO_IR;
  2499. if (geo->bg[i].flags & LIBIPW_CH_NO_IBSS)
  2500. bg_band->channels[i].flags |=
  2501. - IEEE80211_CHAN_NO_IBSS;
  2502. + IEEE80211_CHAN_NO_IR;
  2503. if (geo->bg[i].flags & LIBIPW_CH_RADAR_DETECT)
  2504. bg_band->channels[i].flags |=
  2505. IEEE80211_CHAN_RADAR;
  2506. --- a/drivers/net/wireless/ipw2x00/ipw2200.c
  2507. +++ b/drivers/net/wireless/ipw2x00/ipw2200.c
  2508. @@ -11472,10 +11472,10 @@ static int ipw_wdev_init(struct net_devi
  2509. bg_band->channels[i].max_power = geo->bg[i].max_power;
  2510. if (geo->bg[i].flags & LIBIPW_CH_PASSIVE_ONLY)
  2511. bg_band->channels[i].flags |=
  2512. - IEEE80211_CHAN_PASSIVE_SCAN;
  2513. + IEEE80211_CHAN_NO_IR;
  2514. if (geo->bg[i].flags & LIBIPW_CH_NO_IBSS)
  2515. bg_band->channels[i].flags |=
  2516. - IEEE80211_CHAN_NO_IBSS;
  2517. + IEEE80211_CHAN_NO_IR;
  2518. if (geo->bg[i].flags & LIBIPW_CH_RADAR_DETECT)
  2519. bg_band->channels[i].flags |=
  2520. IEEE80211_CHAN_RADAR;
  2521. @@ -11511,10 +11511,10 @@ static int ipw_wdev_init(struct net_devi
  2522. a_band->channels[i].max_power = geo->a[i].max_power;
  2523. if (geo->a[i].flags & LIBIPW_CH_PASSIVE_ONLY)
  2524. a_band->channels[i].flags |=
  2525. - IEEE80211_CHAN_PASSIVE_SCAN;
  2526. + IEEE80211_CHAN_NO_IR;
  2527. if (geo->a[i].flags & LIBIPW_CH_NO_IBSS)
  2528. a_band->channels[i].flags |=
  2529. - IEEE80211_CHAN_NO_IBSS;
  2530. + IEEE80211_CHAN_NO_IR;
  2531. if (geo->a[i].flags & LIBIPW_CH_RADAR_DETECT)
  2532. a_band->channels[i].flags |=
  2533. IEEE80211_CHAN_RADAR;
  2534. --- a/drivers/net/wireless/iwlegacy/3945-mac.c
  2535. +++ b/drivers/net/wireless/iwlegacy/3945-mac.c
  2536. @@ -1595,7 +1595,7 @@ il3945_get_channels_for_scan(struct il_p
  2537. * and use long active_dwell time.
  2538. */
  2539. if (!is_active || il_is_channel_passive(ch_info) ||
  2540. - (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  2541. + (chan->flags & IEEE80211_CHAN_NO_IR)) {
  2542. scan_ch->type = 0; /* passive */
  2543. if (IL_UCODE_API(il->ucode_ver) == 1)
  2544. scan_ch->active_dwell =
  2545. --- a/drivers/net/wireless/iwlegacy/4965-mac.c
  2546. +++ b/drivers/net/wireless/iwlegacy/4965-mac.c
  2547. @@ -805,7 +805,7 @@ il4965_get_channels_for_scan(struct il_p
  2548. }
  2549. if (!is_active || il_is_channel_passive(ch_info) ||
  2550. - (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
  2551. + (chan->flags & IEEE80211_CHAN_NO_IR))
  2552. scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
  2553. else
  2554. scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
  2555. --- a/drivers/net/wireless/iwlegacy/common.c
  2556. +++ b/drivers/net/wireless/iwlegacy/common.c
  2557. @@ -3447,10 +3447,10 @@ il_init_geos(struct il_priv *il)
  2558. if (il_is_channel_valid(ch)) {
  2559. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  2560. - geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  2561. + geo_ch->flags |= IEEE80211_CHAN_NO_IR;
  2562. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  2563. - geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  2564. + geo_ch->flags |= IEEE80211_CHAN_NO_IR;
  2565. if (ch->flags & EEPROM_CHANNEL_RADAR)
  2566. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  2567. --- a/drivers/net/wireless/iwlegacy/debug.c
  2568. +++ b/drivers/net/wireless/iwlegacy/debug.c
  2569. @@ -567,12 +567,12 @@ il_dbgfs_channels_read(struct file *file
  2570. flags & IEEE80211_CHAN_RADAR ?
  2571. " (IEEE 802.11h required)" : "",
  2572. ((channels[i].
  2573. - flags & IEEE80211_CHAN_NO_IBSS) ||
  2574. + flags & IEEE80211_CHAN_NO_IR) ||
  2575. (channels[i].
  2576. flags & IEEE80211_CHAN_RADAR)) ? "" :
  2577. ", IBSS",
  2578. channels[i].
  2579. - flags & IEEE80211_CHAN_PASSIVE_SCAN ?
  2580. + flags & IEEE80211_CHAN_NO_IR ?
  2581. "passive only" : "active/passive");
  2582. }
  2583. supp_band = il_get_hw_mode(il, IEEE80211_BAND_5GHZ);
  2584. @@ -594,12 +594,12 @@ il_dbgfs_channels_read(struct file *file
  2585. flags & IEEE80211_CHAN_RADAR ?
  2586. " (IEEE 802.11h required)" : "",
  2587. ((channels[i].
  2588. - flags & IEEE80211_CHAN_NO_IBSS) ||
  2589. + flags & IEEE80211_CHAN_NO_IR) ||
  2590. (channels[i].
  2591. flags & IEEE80211_CHAN_RADAR)) ? "" :
  2592. ", IBSS",
  2593. channels[i].
  2594. - flags & IEEE80211_CHAN_PASSIVE_SCAN ?
  2595. + flags & IEEE80211_CHAN_NO_IR ?
  2596. "passive only" : "active/passive");
  2597. }
  2598. ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
  2599. --- a/drivers/net/wireless/iwlwifi/dvm/debugfs.c
  2600. +++ b/drivers/net/wireless/iwlwifi/dvm/debugfs.c
  2601. @@ -352,12 +352,12 @@ static ssize_t iwl_dbgfs_channels_read(s
  2602. channels[i].max_power,
  2603. channels[i].flags & IEEE80211_CHAN_RADAR ?
  2604. " (IEEE 802.11h required)" : "",
  2605. - ((channels[i].flags & IEEE80211_CHAN_NO_IBSS)
  2606. + ((channels[i].flags & IEEE80211_CHAN_NO_IR)
  2607. || (channels[i].flags &
  2608. IEEE80211_CHAN_RADAR)) ? "" :
  2609. ", IBSS",
  2610. channels[i].flags &
  2611. - IEEE80211_CHAN_PASSIVE_SCAN ?
  2612. + IEEE80211_CHAN_NO_IR ?
  2613. "passive only" : "active/passive");
  2614. }
  2615. supp_band = iwl_get_hw_mode(priv, IEEE80211_BAND_5GHZ);
  2616. @@ -375,12 +375,12 @@ static ssize_t iwl_dbgfs_channels_read(s
  2617. channels[i].max_power,
  2618. channels[i].flags & IEEE80211_CHAN_RADAR ?
  2619. " (IEEE 802.11h required)" : "",
  2620. - ((channels[i].flags & IEEE80211_CHAN_NO_IBSS)
  2621. + ((channels[i].flags & IEEE80211_CHAN_NO_IR)
  2622. || (channels[i].flags &
  2623. IEEE80211_CHAN_RADAR)) ? "" :
  2624. ", IBSS",
  2625. channels[i].flags &
  2626. - IEEE80211_CHAN_PASSIVE_SCAN ?
  2627. + IEEE80211_CHAN_NO_IR ?
  2628. "passive only" : "active/passive");
  2629. }
  2630. ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
  2631. --- a/drivers/net/wireless/iwlwifi/dvm/scan.c
  2632. +++ b/drivers/net/wireless/iwlwifi/dvm/scan.c
  2633. @@ -544,7 +544,7 @@ static int iwl_get_channels_for_scan(str
  2634. channel = chan->hw_value;
  2635. scan_ch->channel = cpu_to_le16(channel);
  2636. - if (!is_active || (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
  2637. + if (!is_active || (chan->flags & IEEE80211_CHAN_NO_IR))
  2638. scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
  2639. else
  2640. scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
  2641. --- a/drivers/net/wireless/iwlwifi/iwl-eeprom-parse.c
  2642. +++ b/drivers/net/wireless/iwlwifi/iwl-eeprom-parse.c
  2643. @@ -614,10 +614,10 @@ static int iwl_init_channel_map(struct d
  2644. channel->flags = IEEE80211_CHAN_NO_HT40;
  2645. if (!(eeprom_ch->flags & EEPROM_CHANNEL_IBSS))
  2646. - channel->flags |= IEEE80211_CHAN_NO_IBSS;
  2647. + channel->flags |= IEEE80211_CHAN_NO_IR;
  2648. if (!(eeprom_ch->flags & EEPROM_CHANNEL_ACTIVE))
  2649. - channel->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  2650. + channel->flags |= IEEE80211_CHAN_NO_IR;
  2651. if (eeprom_ch->flags & EEPROM_CHANNEL_RADAR)
  2652. channel->flags |= IEEE80211_CHAN_RADAR;
  2653. --- a/drivers/net/wireless/iwlwifi/iwl-nvm-parse.c
  2654. +++ b/drivers/net/wireless/iwlwifi/iwl-nvm-parse.c
  2655. @@ -223,10 +223,10 @@ static int iwl_init_channel_map(struct d
  2656. channel->flags |= IEEE80211_CHAN_NO_160MHZ;
  2657. if (!(ch_flags & NVM_CHANNEL_IBSS))
  2658. - channel->flags |= IEEE80211_CHAN_NO_IBSS;
  2659. + channel->flags |= IEEE80211_CHAN_NO_IR;
  2660. if (!(ch_flags & NVM_CHANNEL_ACTIVE))
  2661. - channel->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  2662. + channel->flags |= IEEE80211_CHAN_NO_IR;
  2663. if (ch_flags & NVM_CHANNEL_RADAR)
  2664. channel->flags |= IEEE80211_CHAN_RADAR;
  2665. --- a/drivers/net/wireless/iwlwifi/mvm/scan.c
  2666. +++ b/drivers/net/wireless/iwlwifi/mvm/scan.c
  2667. @@ -192,7 +192,7 @@ static void iwl_mvm_scan_fill_channels(s
  2668. for (i = 0; i < cmd->channel_count; i++) {
  2669. chan->channel = cpu_to_le16(req->channels[i]->hw_value);
  2670. chan->type = cpu_to_le32(type);
  2671. - if (req->channels[i]->flags & IEEE80211_CHAN_PASSIVE_SCAN)
  2672. + if (req->channels[i]->flags & IEEE80211_CHAN_NO_IR)
  2673. chan->type &= cpu_to_le32(~SCAN_CHANNEL_TYPE_ACTIVE);
  2674. chan->active_dwell = cpu_to_le16(active_dwell);
  2675. chan->passive_dwell = cpu_to_le16(passive_dwell);
  2676. @@ -642,7 +642,7 @@ static void iwl_build_channel_cfg(struct
  2677. channels->iter_count[index] = cpu_to_le16(1);
  2678. channels->iter_interval[index] = 0;
  2679. - if (!(s_band->channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
  2680. + if (!(s_band->channels[i].flags & IEEE80211_CHAN_NO_IR))
  2681. channels->type[index] |=
  2682. cpu_to_le32(IWL_SCAN_OFFLOAD_CHANNEL_ACTIVE);
  2683. --- a/drivers/net/wireless/mac80211_hwsim.c
  2684. +++ b/drivers/net/wireless/mac80211_hwsim.c
  2685. @@ -159,7 +159,7 @@ static const struct ieee80211_regdomain
  2686. .reg_rules = {
  2687. REG_RULE(2412-10, 2462+10, 40, 0, 20, 0),
  2688. REG_RULE(5725-10, 5850+10, 40, 0, 30,
  2689. - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
  2690. + NL80211_RRF_NO_IR),
  2691. }
  2692. };
  2693. @@ -1485,7 +1485,7 @@ static void hw_scan_work(struct work_str
  2694. req->channels[hwsim->scan_chan_idx]->center_freq);
  2695. hwsim->tmp_chan = req->channels[hwsim->scan_chan_idx];
  2696. - if (hwsim->tmp_chan->flags & IEEE80211_CHAN_PASSIVE_SCAN ||
  2697. + if (hwsim->tmp_chan->flags & IEEE80211_CHAN_NO_IR ||
  2698. !req->n_ssids) {
  2699. dwell = 120;
  2700. } else {
  2701. --- a/drivers/net/wireless/mwifiex/cfg80211.c
  2702. +++ b/drivers/net/wireless/mwifiex/cfg80211.c
  2703. @@ -50,24 +50,24 @@ static const struct ieee80211_regdomain
  2704. REG_RULE(2412-10, 2462+10, 40, 3, 20, 0),
  2705. /* Channel 12 - 13 */
  2706. REG_RULE(2467-10, 2472+10, 20, 3, 20,
  2707. - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
  2708. + NL80211_RRF_NO_IR),
  2709. /* Channel 14 */
  2710. REG_RULE(2484-10, 2484+10, 20, 3, 20,
  2711. - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS |
  2712. + NL80211_RRF_NO_IR |
  2713. NL80211_RRF_NO_OFDM),
  2714. /* Channel 36 - 48 */
  2715. REG_RULE(5180-10, 5240+10, 40, 3, 20,
  2716. - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
  2717. + NL80211_RRF_NO_IR),
  2718. /* Channel 149 - 165 */
  2719. REG_RULE(5745-10, 5825+10, 40, 3, 20,
  2720. - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS),
  2721. + NL80211_RRF_NO_IR),
  2722. /* Channel 52 - 64 */
  2723. REG_RULE(5260-10, 5320+10, 40, 3, 30,
  2724. - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS |
  2725. + NL80211_RRF_NO_IR |
  2726. NL80211_RRF_DFS),
  2727. /* Channel 100 - 140 */
  2728. REG_RULE(5500-10, 5700+10, 40, 3, 30,
  2729. - NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS |
  2730. + NL80211_RRF_NO_IR |
  2731. NL80211_RRF_DFS),
  2732. }
  2733. };
  2734. @@ -1968,7 +1968,7 @@ mwifiex_cfg80211_scan(struct wiphy *wiph
  2735. user_scan_cfg->chan_list[i].chan_number = chan->hw_value;
  2736. user_scan_cfg->chan_list[i].radio_type = chan->band;
  2737. - if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)
  2738. + if (chan->flags & IEEE80211_CHAN_NO_IR)
  2739. user_scan_cfg->chan_list[i].scan_type =
  2740. MWIFIEX_SCAN_TYPE_PASSIVE;
  2741. else
  2742. --- a/drivers/net/wireless/mwifiex/scan.c
  2743. +++ b/drivers/net/wireless/mwifiex/scan.c
  2744. @@ -515,14 +515,14 @@ mwifiex_scan_create_channel_list(struct
  2745. scan_chan_list[chan_idx].max_scan_time =
  2746. cpu_to_le16((u16) user_scan_in->
  2747. chan_list[0].scan_time);
  2748. - else if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
  2749. + else if (ch->flags & IEEE80211_CHAN_NO_IR)
  2750. scan_chan_list[chan_idx].max_scan_time =
  2751. cpu_to_le16(adapter->passive_scan_time);
  2752. else
  2753. scan_chan_list[chan_idx].max_scan_time =
  2754. cpu_to_le16(adapter->active_scan_time);
  2755. - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
  2756. + if (ch->flags & IEEE80211_CHAN_NO_IR)
  2757. scan_chan_list[chan_idx].chan_scan_mode_bitmap
  2758. |= MWIFIEX_PASSIVE_SCAN;
  2759. else
  2760. --- a/drivers/net/wireless/rt2x00/rt2x00lib.h
  2761. +++ b/drivers/net/wireless/rt2x00/rt2x00lib.h
  2762. @@ -146,7 +146,7 @@ void rt2x00queue_remove_l2pad(struct sk_
  2763. * @local: frame is not from mac80211
  2764. */
  2765. int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
  2766. - bool local);
  2767. + struct ieee80211_sta *sta, bool local);
  2768. /**
  2769. * rt2x00queue_update_beacon - Send new beacon from mac80211
  2770. --- a/drivers/net/wireless/rt2x00/rt2x00mac.c
  2771. +++ b/drivers/net/wireless/rt2x00/rt2x00mac.c
  2772. @@ -90,7 +90,7 @@ static int rt2x00mac_tx_rts_cts(struct r
  2773. frag_skb->data, data_length, tx_info,
  2774. (struct ieee80211_rts *)(skb->data));
  2775. - retval = rt2x00queue_write_tx_frame(queue, skb, true);
  2776. + retval = rt2x00queue_write_tx_frame(queue, skb, NULL, true);
  2777. if (retval) {
  2778. dev_kfree_skb_any(skb);
  2779. rt2x00_warn(rt2x00dev, "Failed to send RTS/CTS frame\n");
  2780. @@ -151,7 +151,7 @@ void rt2x00mac_tx(struct ieee80211_hw *h
  2781. goto exit_fail;
  2782. }
  2783. - if (unlikely(rt2x00queue_write_tx_frame(queue, skb, false)))
  2784. + if (unlikely(rt2x00queue_write_tx_frame(queue, skb, control->sta, false)))
  2785. goto exit_fail;
  2786. /*
  2787. --- a/drivers/net/wireless/rt2x00/rt2x00queue.c
  2788. +++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
  2789. @@ -635,7 +635,7 @@ static void rt2x00queue_bar_check(struct
  2790. }
  2791. int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
  2792. - bool local)
  2793. + struct ieee80211_sta *sta, bool local)
  2794. {
  2795. struct ieee80211_tx_info *tx_info;
  2796. struct queue_entry *entry;
  2797. @@ -649,7 +649,7 @@ int rt2x00queue_write_tx_frame(struct da
  2798. * after that we are free to use the skb->cb array
  2799. * for our information.
  2800. */
  2801. - rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc, NULL);
  2802. + rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc, sta);
  2803. /*
  2804. * All information is retrieved from the skb->cb array,
  2805. --- a/drivers/net/wireless/rtl818x/rtl8187/dev.c
  2806. +++ b/drivers/net/wireless/rtl818x/rtl8187/dev.c
  2807. @@ -416,7 +416,7 @@ static int rtl8187_init_urbs(struct ieee
  2808. struct rtl8187_rx_info *info;
  2809. int ret = 0;
  2810. - while (skb_queue_len(&priv->rx_queue) < 16) {
  2811. + while (skb_queue_len(&priv->rx_queue) < 32) {
  2812. skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
  2813. if (!skb) {
  2814. ret = -ENOMEM;
  2815. --- a/drivers/net/wireless/rtlwifi/base.c
  2816. +++ b/drivers/net/wireless/rtlwifi/base.c
  2817. @@ -1078,8 +1078,8 @@ u8 rtl_is_special_data(struct ieee80211_
  2818. ip = (struct iphdr *)((u8 *) skb->data + mac_hdr_len +
  2819. SNAP_SIZE + PROTOC_TYPE_SIZE);
  2820. - ether_type = *(u16 *) ((u8 *) skb->data + mac_hdr_len + SNAP_SIZE);
  2821. - /* ether_type = ntohs(ether_type); */
  2822. + ether_type = be16_to_cpu(*(__be16 *)((u8 *)skb->data + mac_hdr_len +
  2823. + SNAP_SIZE));
  2824. if (ETH_P_IP == ether_type) {
  2825. if (IPPROTO_UDP == ip->protocol) {
  2826. --- a/drivers/net/wireless/rtlwifi/regd.c
  2827. +++ b/drivers/net/wireless/rtlwifi/regd.c
  2828. @@ -59,30 +59,27 @@ static struct country_code_to_enum_rd al
  2829. */
  2830. #define RTL819x_2GHZ_CH12_13 \
  2831. REG_RULE(2467-10, 2472+10, 40, 0, 20,\
  2832. - NL80211_RRF_PASSIVE_SCAN)
  2833. + NL80211_RRF_NO_IR)
  2834. #define RTL819x_2GHZ_CH14 \
  2835. REG_RULE(2484-10, 2484+10, 40, 0, 20, \
  2836. - NL80211_RRF_PASSIVE_SCAN | \
  2837. + NL80211_RRF_NO_IR | \
  2838. NL80211_RRF_NO_OFDM)
  2839. /* 5G chan 36 - chan 64*/
  2840. #define RTL819x_5GHZ_5150_5350 \
  2841. REG_RULE(5150-10, 5350+10, 40, 0, 30, \
  2842. - NL80211_RRF_PASSIVE_SCAN | \
  2843. - NL80211_RRF_NO_IBSS)
  2844. + NL80211_RRF_NO_IR)
  2845. /* 5G chan 100 - chan 165*/
  2846. #define RTL819x_5GHZ_5470_5850 \
  2847. REG_RULE(5470-10, 5850+10, 40, 0, 30, \
  2848. - NL80211_RRF_PASSIVE_SCAN | \
  2849. - NL80211_RRF_NO_IBSS)
  2850. + NL80211_RRF_NO_IR)
  2851. /* 5G chan 149 - chan 165*/
  2852. #define RTL819x_5GHZ_5725_5850 \
  2853. REG_RULE(5725-10, 5850+10, 40, 0, 30, \
  2854. - NL80211_RRF_PASSIVE_SCAN | \
  2855. - NL80211_RRF_NO_IBSS)
  2856. + NL80211_RRF_NO_IR)
  2857. #define RTL819x_5GHZ_ALL \
  2858. (RTL819x_5GHZ_5150_5350, RTL819x_5GHZ_5470_5850)
  2859. @@ -185,16 +182,15 @@ static void _rtl_reg_apply_beaconing_fla
  2860. *regulatory_hint().
  2861. */
  2862. - if (!(reg_rule->flags & NL80211_RRF_NO_IBSS))
  2863. - ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
  2864. + if (!(reg_rule->flags & NL80211_RRF_NO_IR))
  2865. + ch->flags &= ~IEEE80211_CHAN_NO_IR;
  2866. if (!(reg_rule->
  2867. - flags & NL80211_RRF_PASSIVE_SCAN))
  2868. + flags & NL80211_RRF_NO_IR))
  2869. ch->flags &=
  2870. - ~IEEE80211_CHAN_PASSIVE_SCAN;
  2871. + ~IEEE80211_CHAN_NO_IR;
  2872. } else {
  2873. if (ch->beacon_found)
  2874. - ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
  2875. - IEEE80211_CHAN_PASSIVE_SCAN);
  2876. + ch->flags &= ~IEEE80211_CHAN_NO_IR;
  2877. }
  2878. }
  2879. }
  2880. @@ -219,11 +215,11 @@ static void _rtl_reg_apply_active_scan_f
  2881. */
  2882. if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
  2883. ch = &sband->channels[11]; /* CH 12 */
  2884. - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
  2885. - ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
  2886. + if (ch->flags & IEEE80211_CHAN_NO_IR)
  2887. + ch->flags &= ~IEEE80211_CHAN_NO_IR;
  2888. ch = &sband->channels[12]; /* CH 13 */
  2889. - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
  2890. - ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
  2891. + if (ch->flags & IEEE80211_CHAN_NO_IR)
  2892. + ch->flags &= ~IEEE80211_CHAN_NO_IR;
  2893. return;
  2894. }
  2895. @@ -237,17 +233,17 @@ static void _rtl_reg_apply_active_scan_f
  2896. ch = &sband->channels[11]; /* CH 12 */
  2897. reg_rule = freq_reg_info(wiphy, ch->center_freq);
  2898. if (!IS_ERR(reg_rule)) {
  2899. - if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
  2900. - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
  2901. - ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
  2902. + if (!(reg_rule->flags & NL80211_RRF_NO_IR))
  2903. + if (ch->flags & IEEE80211_CHAN_NO_IR)
  2904. + ch->flags &= ~IEEE80211_CHAN_NO_IR;
  2905. }
  2906. ch = &sband->channels[12]; /* CH 13 */
  2907. reg_rule = freq_reg_info(wiphy, ch->center_freq);
  2908. if (!IS_ERR(reg_rule)) {
  2909. - if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
  2910. - if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
  2911. - ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
  2912. + if (!(reg_rule->flags & NL80211_RRF_NO_IR))
  2913. + if (ch->flags & IEEE80211_CHAN_NO_IR)
  2914. + ch->flags &= ~IEEE80211_CHAN_NO_IR;
  2915. }
  2916. }
  2917. @@ -284,8 +280,8 @@ static void _rtl_reg_apply_radar_flags(s
  2918. */
  2919. if (!(ch->flags & IEEE80211_CHAN_DISABLED))
  2920. ch->flags |= IEEE80211_CHAN_RADAR |
  2921. - IEEE80211_CHAN_NO_IBSS |
  2922. - IEEE80211_CHAN_PASSIVE_SCAN;
  2923. + IEEE80211_CHAN_NO_IR |
  2924. + IEEE80211_CHAN_NO_IR;
  2925. }
  2926. }
  2927. --- a/drivers/net/wireless/ti/wl12xx/scan.c
  2928. +++ b/drivers/net/wireless/ti/wl12xx/scan.c
  2929. @@ -47,7 +47,7 @@ static int wl1271_get_scan_channels(stru
  2930. * In active scans, we only scan channels not
  2931. * marked as passive.
  2932. */
  2933. - (passive || !(flags & IEEE80211_CHAN_PASSIVE_SCAN))) {
  2934. + (passive || !(flags & IEEE80211_CHAN_NO_IR))) {
  2935. wl1271_debug(DEBUG_SCAN, "band %d, center_freq %d ",
  2936. req->channels[i]->band,
  2937. req->channels[i]->center_freq);
  2938. --- a/drivers/net/wireless/ti/wlcore/cmd.c
  2939. +++ b/drivers/net/wireless/ti/wlcore/cmd.c
  2940. @@ -1688,7 +1688,7 @@ int wlcore_cmd_regdomain_config_locked(s
  2941. if (channel->flags & (IEEE80211_CHAN_DISABLED |
  2942. IEEE80211_CHAN_RADAR |
  2943. - IEEE80211_CHAN_PASSIVE_SCAN))
  2944. + IEEE80211_CHAN_NO_IR))
  2945. continue;
  2946. ch_bit_idx = wlcore_get_reg_conf_ch_idx(b, ch);
  2947. --- a/drivers/net/wireless/ti/wlcore/main.c
  2948. +++ b/drivers/net/wireless/ti/wlcore/main.c
  2949. @@ -91,8 +91,7 @@ static void wl1271_reg_notify(struct wip
  2950. continue;
  2951. if (ch->flags & IEEE80211_CHAN_RADAR)
  2952. - ch->flags |= IEEE80211_CHAN_NO_IBSS |
  2953. - IEEE80211_CHAN_PASSIVE_SCAN;
  2954. + ch->flags |= IEEE80211_CHAN_NO_IR;
  2955. }
  2956. --- a/drivers/net/wireless/ti/wlcore/scan.c
  2957. +++ b/drivers/net/wireless/ti/wlcore/scan.c
  2958. @@ -189,14 +189,14 @@ wlcore_scan_get_channels(struct wl1271 *
  2959. flags = req_channels[i]->flags;
  2960. if (force_passive)
  2961. - flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  2962. + flags |= IEEE80211_CHAN_NO_IR;
  2963. if ((req_channels[i]->band == band) &&
  2964. !(flags & IEEE80211_CHAN_DISABLED) &&
  2965. (!!(flags & IEEE80211_CHAN_RADAR) == radar) &&
  2966. /* if radar is set, we ignore the passive flag */
  2967. (radar ||
  2968. - !!(flags & IEEE80211_CHAN_PASSIVE_SCAN) == passive)) {
  2969. + !!(flags & IEEE80211_CHAN_NO_IR) == passive)) {
  2970. if (flags & IEEE80211_CHAN_RADAR) {
  2971. @@ -221,7 +221,7 @@ wlcore_scan_get_channels(struct wl1271 *
  2972. (band == IEEE80211_BAND_2GHZ) &&
  2973. (channels[j].channel >= 12) &&
  2974. (channels[j].channel <= 14) &&
  2975. - (flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
  2976. + (flags & IEEE80211_CHAN_NO_IR) &&
  2977. !force_passive) {
  2978. /* pactive channels treated as DFS */
  2979. channels[j].flags = SCAN_CHANNEL_FLAGS_DFS;
  2980. @@ -244,7 +244,7 @@ wlcore_scan_get_channels(struct wl1271 *
  2981. max_dwell_time_active,
  2982. flags & IEEE80211_CHAN_RADAR ?
  2983. ", DFS" : "",
  2984. - flags & IEEE80211_CHAN_PASSIVE_SCAN ?
  2985. + flags & IEEE80211_CHAN_NO_IR ?
  2986. ", PASSIVE" : "");
  2987. j++;
  2988. }
  2989. --- a/include/net/cfg80211.h
  2990. +++ b/include/net/cfg80211.h
  2991. @@ -91,9 +91,8 @@ enum ieee80211_band {
  2992. * Channel flags set by the regulatory control code.
  2993. *
  2994. * @IEEE80211_CHAN_DISABLED: This channel is disabled.
  2995. - * @IEEE80211_CHAN_PASSIVE_SCAN: Only passive scanning is permitted
  2996. - * on this channel.
  2997. - * @IEEE80211_CHAN_NO_IBSS: IBSS is not allowed on this channel.
  2998. + * @IEEE80211_CHAN_NO_IR: do not initiate radiation, this includes
  2999. + * sending probe requests or beaconing.
  3000. * @IEEE80211_CHAN_RADAR: Radar detection is required on this channel.
  3001. * @IEEE80211_CHAN_NO_HT40PLUS: extension channel above this channel
  3002. * is not permitted.
  3003. @@ -113,8 +112,8 @@ enum ieee80211_band {
  3004. */
  3005. enum ieee80211_channel_flags {
  3006. IEEE80211_CHAN_DISABLED = 1<<0,
  3007. - IEEE80211_CHAN_PASSIVE_SCAN = 1<<1,
  3008. - IEEE80211_CHAN_NO_IBSS = 1<<2,
  3009. + IEEE80211_CHAN_NO_IR = 1<<1,
  3010. + /* hole at 1<<2 */
  3011. IEEE80211_CHAN_RADAR = 1<<3,
  3012. IEEE80211_CHAN_NO_HT40PLUS = 1<<4,
  3013. IEEE80211_CHAN_NO_HT40MINUS = 1<<5,
  3014. @@ -4149,6 +4148,7 @@ void cfg80211_radar_event(struct wiphy *
  3015. /**
  3016. * cfg80211_cac_event - Channel availability check (CAC) event
  3017. * @netdev: network device
  3018. + * @chandef: chandef for the current channel
  3019. * @event: type of event
  3020. * @gfp: context flags
  3021. *
  3022. @@ -4157,6 +4157,7 @@ void cfg80211_radar_event(struct wiphy *
  3023. * also by full-MAC drivers.
  3024. */
  3025. void cfg80211_cac_event(struct net_device *netdev,
  3026. + const struct cfg80211_chan_def *chandef,
  3027. enum nl80211_radar_event event, gfp_t gfp);
  3028. @@ -4282,7 +4283,8 @@ bool cfg80211_reg_can_beacon(struct wiph
  3029. * @dev: the device which switched channels
  3030. * @chandef: the new channel definition
  3031. *
  3032. - * Acquires wdev_lock, so must only be called from sleepable driver context!
  3033. + * Caller must acquire wdev_lock, therefore must only be called from sleepable
  3034. + * driver context!
  3035. */
  3036. void cfg80211_ch_switch_notify(struct net_device *dev,
  3037. struct cfg80211_chan_def *chandef);
  3038. --- a/include/uapi/linux/nl80211.h
  3039. +++ b/include/uapi/linux/nl80211.h
  3040. @@ -1508,6 +1508,12 @@ enum nl80211_commands {
  3041. * to react to radar events, e.g. initiate a channel switch or leave the
  3042. * IBSS network.
  3043. *
  3044. + * @NL80211_ATTR_SUPPORT_5_MHZ: A flag indicating that the device supports
  3045. + * 5 MHz channel bandwidth.
  3046. + *
  3047. + * @NL80211_ATTR_SUPPORT_10_MHZ: A flag indicating that the device supports
  3048. + * 10 MHz channel bandwidth.
  3049. + *
  3050. * @NL80211_ATTR_MAX: highest attribute number currently defined
  3051. * @__NL80211_ATTR_AFTER_LAST: internal use
  3052. */
  3053. @@ -1824,6 +1830,9 @@ enum nl80211_attrs {
  3054. NL80211_ATTR_HANDLE_DFS,
  3055. + NL80211_ATTR_SUPPORT_5_MHZ,
  3056. + NL80211_ATTR_SUPPORT_10_MHZ,
  3057. +
  3058. /* add attributes here, update the policy in nl80211.c */
  3059. __NL80211_ATTR_AFTER_LAST,
  3060. @@ -2224,10 +2233,9 @@ enum nl80211_band_attr {
  3061. * @NL80211_FREQUENCY_ATTR_FREQ: Frequency in MHz
  3062. * @NL80211_FREQUENCY_ATTR_DISABLED: Channel is disabled in current
  3063. * regulatory domain.
  3064. - * @NL80211_FREQUENCY_ATTR_PASSIVE_SCAN: Only passive scanning is
  3065. - * permitted on this channel in current regulatory domain.
  3066. - * @NL80211_FREQUENCY_ATTR_NO_IBSS: IBSS networks are not permitted
  3067. - * on this channel in current regulatory domain.
  3068. + * @NL80211_FREQUENCY_ATTR_NO_IR: no mechanisms that initiate radiation
  3069. + * are permitted on this channel, this includes sending probe
  3070. + * requests, or modes of operation that require beaconing.
  3071. * @NL80211_FREQUENCY_ATTR_RADAR: Radar detection is mandatory
  3072. * on this channel in current regulatory domain.
  3073. * @NL80211_FREQUENCY_ATTR_MAX_TX_POWER: Maximum transmission power in mBm
  3074. @@ -2254,8 +2262,8 @@ enum nl80211_frequency_attr {
  3075. __NL80211_FREQUENCY_ATTR_INVALID,
  3076. NL80211_FREQUENCY_ATTR_FREQ,
  3077. NL80211_FREQUENCY_ATTR_DISABLED,
  3078. - NL80211_FREQUENCY_ATTR_PASSIVE_SCAN,
  3079. - NL80211_FREQUENCY_ATTR_NO_IBSS,
  3080. + NL80211_FREQUENCY_ATTR_NO_IR,
  3081. + __NL80211_FREQUENCY_ATTR_NO_IBSS,
  3082. NL80211_FREQUENCY_ATTR_RADAR,
  3083. NL80211_FREQUENCY_ATTR_MAX_TX_POWER,
  3084. NL80211_FREQUENCY_ATTR_DFS_STATE,
  3085. @@ -2271,6 +2279,9 @@ enum nl80211_frequency_attr {
  3086. };
  3087. #define NL80211_FREQUENCY_ATTR_MAX_TX_POWER NL80211_FREQUENCY_ATTR_MAX_TX_POWER
  3088. +#define NL80211_FREQUENCY_ATTR_PASSIVE_SCAN NL80211_FREQUENCY_ATTR_NO_IR
  3089. +#define NL80211_FREQUENCY_ATTR_NO_IBSS NL80211_FREQUENCY_ATTR_NO_IR
  3090. +#define NL80211_FREQUENCY_ATTR_NO_IR NL80211_FREQUENCY_ATTR_NO_IR
  3091. /**
  3092. * enum nl80211_bitrate_attr - bitrate attributes
  3093. @@ -2413,8 +2424,9 @@ enum nl80211_sched_scan_match_attr {
  3094. * @NL80211_RRF_DFS: DFS support is required to be used
  3095. * @NL80211_RRF_PTP_ONLY: this is only for Point To Point links
  3096. * @NL80211_RRF_PTMP_ONLY: this is only for Point To Multi Point links
  3097. - * @NL80211_RRF_PASSIVE_SCAN: passive scan is required
  3098. - * @NL80211_RRF_NO_IBSS: no IBSS is allowed
  3099. + * @NL80211_RRF_NO_IR: no mechanisms that initiate radiation are allowed,
  3100. + * this includes probe requests or modes of operation that require
  3101. + * beaconing.
  3102. */
  3103. enum nl80211_reg_rule_flags {
  3104. NL80211_RRF_NO_OFDM = 1<<0,
  3105. @@ -2424,10 +2436,17 @@ enum nl80211_reg_rule_flags {
  3106. NL80211_RRF_DFS = 1<<4,
  3107. NL80211_RRF_PTP_ONLY = 1<<5,
  3108. NL80211_RRF_PTMP_ONLY = 1<<6,
  3109. - NL80211_RRF_PASSIVE_SCAN = 1<<7,
  3110. - NL80211_RRF_NO_IBSS = 1<<8,
  3111. + NL80211_RRF_NO_IR = 1<<7,
  3112. + __NL80211_RRF_NO_IBSS = 1<<8,
  3113. };
  3114. +#define NL80211_RRF_PASSIVE_SCAN NL80211_RRF_NO_IR
  3115. +#define NL80211_RRF_NO_IBSS NL80211_RRF_NO_IR
  3116. +#define NL80211_RRF_NO_IR NL80211_RRF_NO_IR
  3117. +
  3118. +/* For backport compatibility with older userspace */
  3119. +#define NL80211_RRF_NO_IR_ALL (NL80211_RRF_NO_IR | __NL80211_RRF_NO_IBSS)
  3120. +
  3121. /**
  3122. * enum nl80211_dfs_regions - regulatory DFS regions
  3123. *
  3124. --- a/net/mac80211/cfg.c
  3125. +++ b/net/mac80211/cfg.c
  3126. @@ -846,7 +846,7 @@ static int ieee80211_set_probe_resp(stru
  3127. if (!resp || !resp_len)
  3128. return 1;
  3129. - old = rtnl_dereference(sdata->u.ap.probe_resp);
  3130. + old = sdata_dereference(sdata->u.ap.probe_resp, sdata);
  3131. new = kzalloc(sizeof(struct probe_resp) + resp_len, GFP_KERNEL);
  3132. if (!new)
  3133. @@ -870,7 +870,8 @@ int ieee80211_assign_beacon(struct ieee8
  3134. int size, err;
  3135. u32 changed = BSS_CHANGED_BEACON;
  3136. - old = rtnl_dereference(sdata->u.ap.beacon);
  3137. + old = sdata_dereference(sdata->u.ap.beacon, sdata);
  3138. +
  3139. /* Need to have a beacon head if we don't have one yet */
  3140. if (!params->head && !old)
  3141. @@ -947,7 +948,7 @@ static int ieee80211_start_ap(struct wip
  3142. BSS_CHANGED_P2P_PS;
  3143. int err;
  3144. - old = rtnl_dereference(sdata->u.ap.beacon);
  3145. + old = sdata_dereference(sdata->u.ap.beacon, sdata);
  3146. if (old)
  3147. return -EALREADY;
  3148. @@ -1001,7 +1002,8 @@ static int ieee80211_start_ap(struct wip
  3149. err = drv_start_ap(sdata->local, sdata);
  3150. if (err) {
  3151. - old = rtnl_dereference(sdata->u.ap.beacon);
  3152. + old = sdata_dereference(sdata->u.ap.beacon, sdata);
  3153. +
  3154. if (old)
  3155. kfree_rcu(old, rcu_head);
  3156. RCU_INIT_POINTER(sdata->u.ap.beacon, NULL);
  3157. @@ -1032,7 +1034,7 @@ static int ieee80211_change_beacon(struc
  3158. if (sdata->vif.csa_active)
  3159. return -EBUSY;
  3160. - old = rtnl_dereference(sdata->u.ap.beacon);
  3161. + old = sdata_dereference(sdata->u.ap.beacon, sdata);
  3162. if (!old)
  3163. return -ENOENT;
  3164. @@ -1050,15 +1052,18 @@ static int ieee80211_stop_ap(struct wiph
  3165. struct ieee80211_local *local = sdata->local;
  3166. struct beacon_data *old_beacon;
  3167. struct probe_resp *old_probe_resp;
  3168. + struct cfg80211_chan_def chandef;
  3169. - old_beacon = rtnl_dereference(sdata->u.ap.beacon);
  3170. + old_beacon = sdata_dereference(sdata->u.ap.beacon, sdata);
  3171. if (!old_beacon)
  3172. return -ENOENT;
  3173. - old_probe_resp = rtnl_dereference(sdata->u.ap.probe_resp);
  3174. + old_probe_resp = sdata_dereference(sdata->u.ap.probe_resp, sdata);
  3175. /* abort any running channel switch */
  3176. sdata->vif.csa_active = false;
  3177. - cancel_work_sync(&sdata->csa_finalize_work);
  3178. + kfree(sdata->u.ap.next_beacon);
  3179. + sdata->u.ap.next_beacon = NULL;
  3180. +
  3181. cancel_work_sync(&sdata->u.ap.request_smps_work);
  3182. /* turn off carrier for this interface and dependent VLANs */
  3183. @@ -1091,8 +1096,10 @@ static int ieee80211_stop_ap(struct wiph
  3184. ieee80211_bss_info_change_notify(sdata, BSS_CHANGED_BEACON_ENABLED);
  3185. if (sdata->wdev.cac_started) {
  3186. + chandef = sdata->vif.bss_conf.chandef;
  3187. cancel_delayed_work_sync(&sdata->dfs_cac_timer_work);
  3188. - cfg80211_cac_event(sdata->dev, NL80211_RADAR_CAC_ABORTED,
  3189. + cfg80211_cac_event(sdata->dev, &chandef,
  3190. + NL80211_RADAR_CAC_ABORTED,
  3191. GFP_KERNEL);
  3192. }
  3193. @@ -1368,7 +1375,7 @@ static int sta_apply_parameters(struct i
  3194. changed |=
  3195. ieee80211_mps_set_sta_local_pm(sta,
  3196. params->local_pm);
  3197. - ieee80211_bss_info_change_notify(sdata, changed);
  3198. + ieee80211_mbss_info_change_notify(sdata, changed);
  3199. #endif
  3200. }
  3201. @@ -1953,7 +1960,7 @@ static int ieee80211_change_bss(struct w
  3202. enum ieee80211_band band;
  3203. u32 changed = 0;
  3204. - if (!rtnl_dereference(sdata->u.ap.beacon))
  3205. + if (!sdata_dereference(sdata->u.ap.beacon, sdata))
  3206. return -ENOENT;
  3207. band = ieee80211_get_sdata_band(sdata);
  3208. @@ -2964,27 +2971,33 @@ void ieee80211_csa_finalize_work(struct
  3209. struct ieee80211_local *local = sdata->local;
  3210. int err, changed = 0;
  3211. + sdata_lock(sdata);
  3212. + /* AP might have been stopped while waiting for the lock. */
  3213. + if (!sdata->vif.csa_active)
  3214. + goto unlock;
  3215. +
  3216. if (!ieee80211_sdata_running(sdata))
  3217. - return;
  3218. + goto unlock;
  3219. sdata->radar_required = sdata->csa_radar_required;
  3220. - err = ieee80211_vif_change_channel(sdata, &local->csa_chandef,
  3221. - &changed);
  3222. + err = ieee80211_vif_change_channel(sdata, &changed);
  3223. if (WARN_ON(err < 0))
  3224. - return;
  3225. + goto unlock;
  3226. if (!local->use_chanctx) {
  3227. - local->_oper_chandef = local->csa_chandef;
  3228. + local->_oper_chandef = sdata->csa_chandef;
  3229. ieee80211_hw_config(local, 0);
  3230. }
  3231. ieee80211_bss_info_change_notify(sdata, changed);
  3232. + sdata->vif.csa_active = false;
  3233. switch (sdata->vif.type) {
  3234. case NL80211_IFTYPE_AP:
  3235. err = ieee80211_assign_beacon(sdata, sdata->u.ap.next_beacon);
  3236. if (err < 0)
  3237. - return;
  3238. + goto unlock;
  3239. +
  3240. changed |= err;
  3241. kfree(sdata->u.ap.next_beacon);
  3242. sdata->u.ap.next_beacon = NULL;
  3243. @@ -2998,20 +3011,22 @@ void ieee80211_csa_finalize_work(struct
  3244. case NL80211_IFTYPE_MESH_POINT:
  3245. err = ieee80211_mesh_finish_csa(sdata);
  3246. if (err < 0)
  3247. - return;
  3248. + goto unlock;
  3249. break;
  3250. #endif
  3251. default:
  3252. WARN_ON(1);
  3253. - return;
  3254. + goto unlock;
  3255. }
  3256. - sdata->vif.csa_active = false;
  3257. ieee80211_wake_queues_by_reason(&sdata->local->hw,
  3258. IEEE80211_MAX_QUEUE_MAP,
  3259. IEEE80211_QUEUE_STOP_REASON_CSA);
  3260. - cfg80211_ch_switch_notify(sdata->dev, &local->csa_chandef);
  3261. + cfg80211_ch_switch_notify(sdata->dev, &sdata->csa_chandef);
  3262. +
  3263. +unlock:
  3264. + sdata_unlock(sdata);
  3265. }
  3266. static int ieee80211_channel_switch(struct wiphy *wiphy, struct net_device *dev,
  3267. @@ -3024,6 +3039,8 @@ static int ieee80211_channel_switch(stru
  3268. struct ieee80211_if_mesh __maybe_unused *ifmsh;
  3269. int err, num_chanctx;
  3270. + lockdep_assert_held(&sdata->wdev.mtx);
  3271. +
  3272. if (!list_empty(&local->roc_list) || local->scanning)
  3273. return -EBUSY;
  3274. @@ -3120,9 +3137,17 @@ static int ieee80211_channel_switch(stru
  3275. params->chandef.chan->band)
  3276. return -EINVAL;
  3277. + ifmsh->chsw_init = true;
  3278. + if (!ifmsh->pre_value)
  3279. + ifmsh->pre_value = 1;
  3280. + else
  3281. + ifmsh->pre_value++;
  3282. +
  3283. err = ieee80211_mesh_csa_beacon(sdata, params, true);
  3284. - if (err < 0)
  3285. + if (err < 0) {
  3286. + ifmsh->chsw_init = false;
  3287. return err;
  3288. + }
  3289. break;
  3290. #endif
  3291. default:
  3292. @@ -3136,7 +3161,7 @@ static int ieee80211_channel_switch(stru
  3293. IEEE80211_MAX_QUEUE_MAP,
  3294. IEEE80211_QUEUE_STOP_REASON_CSA);
  3295. - local->csa_chandef = params->chandef;
  3296. + sdata->csa_chandef = params->chandef;
  3297. sdata->vif.csa_active = true;
  3298. ieee80211_bss_info_change_notify(sdata, err);
  3299. --- a/net/mac80211/iface.c
  3300. +++ b/net/mac80211/iface.c
  3301. @@ -749,6 +749,7 @@ static void ieee80211_do_stop(struct iee
  3302. u32 hw_reconf_flags = 0;
  3303. int i, flushed;
  3304. struct ps_data *ps;
  3305. + struct cfg80211_chan_def chandef;
  3306. clear_bit(SDATA_STATE_RUNNING, &sdata->state);
  3307. @@ -828,11 +829,13 @@ static void ieee80211_do_stop(struct iee
  3308. cancel_delayed_work_sync(&sdata->dfs_cac_timer_work);
  3309. if (sdata->wdev.cac_started) {
  3310. + chandef = sdata->vif.bss_conf.chandef;
  3311. WARN_ON(local->suspended);
  3312. mutex_lock(&local->iflist_mtx);
  3313. ieee80211_vif_release_channel(sdata);
  3314. mutex_unlock(&local->iflist_mtx);
  3315. - cfg80211_cac_event(sdata->dev, NL80211_RADAR_CAC_ABORTED,
  3316. + cfg80211_cac_event(sdata->dev, &chandef,
  3317. + NL80211_RADAR_CAC_ABORTED,
  3318. GFP_KERNEL);
  3319. }
  3320. @@ -1340,7 +1343,6 @@ static void ieee80211_setup_sdata(struct
  3321. sdata->vif.bss_conf.bssid = NULL;
  3322. break;
  3323. case NL80211_IFTYPE_AP_VLAN:
  3324. - break;
  3325. case NL80211_IFTYPE_P2P_DEVICE:
  3326. sdata->vif.bss_conf.bssid = sdata->vif.addr;
  3327. break;
  3328. --- a/net/mac80211/mlme.c
  3329. +++ b/net/mac80211/mlme.c
  3330. @@ -886,8 +886,7 @@ static void ieee80211_chswitch_work(stru
  3331. if (!ifmgd->associated)
  3332. goto out;
  3333. - ret = ieee80211_vif_change_channel(sdata, &local->csa_chandef,
  3334. - &changed);
  3335. + ret = ieee80211_vif_change_channel(sdata, &changed);
  3336. if (ret) {
  3337. sdata_info(sdata,
  3338. "vif channel switch failed, disconnecting\n");
  3339. @@ -897,7 +896,7 @@ static void ieee80211_chswitch_work(stru
  3340. }
  3341. if (!local->use_chanctx) {
  3342. - local->_oper_chandef = local->csa_chandef;
  3343. + local->_oper_chandef = sdata->csa_chandef;
  3344. /* Call "hw_config" only if doing sw channel switch.
  3345. * Otherwise update the channel directly
  3346. */
  3347. @@ -908,7 +907,7 @@ static void ieee80211_chswitch_work(stru
  3348. }
  3349. /* XXX: shouldn't really modify cfg80211-owned data! */
  3350. - ifmgd->associated->channel = local->csa_chandef.chan;
  3351. + ifmgd->associated->channel = sdata->csa_chandef.chan;
  3352. /* XXX: wait for a beacon first? */
  3353. ieee80211_wake_queues_by_reason(&local->hw,
  3354. @@ -1035,7 +1034,7 @@ ieee80211_sta_process_chanswitch(struct
  3355. }
  3356. mutex_unlock(&local->chanctx_mtx);
  3357. - local->csa_chandef = csa_ie.chandef;
  3358. + sdata->csa_chandef = csa_ie.chandef;
  3359. if (csa_ie.mode)
  3360. ieee80211_stop_queues_by_reason(&local->hw,
  3361. @@ -1398,10 +1397,12 @@ void ieee80211_dfs_cac_timer_work(struct
  3362. struct ieee80211_sub_if_data *sdata =
  3363. container_of(delayed_work, struct ieee80211_sub_if_data,
  3364. dfs_cac_timer_work);
  3365. + struct cfg80211_chan_def chandef = sdata->vif.bss_conf.chandef;
  3366. ieee80211_vif_release_channel(sdata);
  3367. -
  3368. - cfg80211_cac_event(sdata->dev, NL80211_RADAR_CAC_FINISHED, GFP_KERNEL);
  3369. + cfg80211_cac_event(sdata->dev, &chandef,
  3370. + NL80211_RADAR_CAC_FINISHED,
  3371. + GFP_KERNEL);
  3372. }
  3373. /* MLME */
  3374. --- a/net/mac80211/rx.c
  3375. +++ b/net/mac80211/rx.c
  3376. @@ -729,9 +729,7 @@ static void ieee80211_release_reorder_fr
  3377. lockdep_assert_held(&tid_agg_rx->reorder_lock);
  3378. while (ieee80211_sn_less(tid_agg_rx->head_seq_num, head_seq_num)) {
  3379. - index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
  3380. - tid_agg_rx->ssn) %
  3381. - tid_agg_rx->buf_size;
  3382. + index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
  3383. ieee80211_release_reorder_frame(sdata, tid_agg_rx, index,
  3384. frames);
  3385. }
  3386. @@ -757,8 +755,7 @@ static void ieee80211_sta_reorder_releas
  3387. lockdep_assert_held(&tid_agg_rx->reorder_lock);
  3388. /* release the buffer until next missing frame */
  3389. - index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
  3390. - tid_agg_rx->ssn) % tid_agg_rx->buf_size;
  3391. + index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
  3392. if (!tid_agg_rx->reorder_buf[index] &&
  3393. tid_agg_rx->stored_mpdu_num) {
  3394. /*
  3395. @@ -793,15 +790,11 @@ static void ieee80211_sta_reorder_releas
  3396. } else while (tid_agg_rx->reorder_buf[index]) {
  3397. ieee80211_release_reorder_frame(sdata, tid_agg_rx, index,
  3398. frames);
  3399. - index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
  3400. - tid_agg_rx->ssn) %
  3401. - tid_agg_rx->buf_size;
  3402. + index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
  3403. }
  3404. if (tid_agg_rx->stored_mpdu_num) {
  3405. - j = index = ieee80211_sn_sub(tid_agg_rx->head_seq_num,
  3406. - tid_agg_rx->ssn) %
  3407. - tid_agg_rx->buf_size;
  3408. + j = index = tid_agg_rx->head_seq_num % tid_agg_rx->buf_size;
  3409. for (; j != (index - 1) % tid_agg_rx->buf_size;
  3410. j = (j + 1) % tid_agg_rx->buf_size) {
  3411. @@ -861,8 +854,7 @@ static bool ieee80211_sta_manage_reorder
  3412. /* Now the new frame is always in the range of the reordering buffer */
  3413. - index = ieee80211_sn_sub(mpdu_seq_num,
  3414. - tid_agg_rx->ssn) % tid_agg_rx->buf_size;
  3415. + index = mpdu_seq_num % tid_agg_rx->buf_size;
  3416. /* check if we already stored this frame */
  3417. if (tid_agg_rx->reorder_buf[index]) {
  3418. @@ -911,7 +903,8 @@ static void ieee80211_rx_reorder_ampdu(s
  3419. u16 sc;
  3420. u8 tid, ack_policy;
  3421. - if (!ieee80211_is_data_qos(hdr->frame_control))
  3422. + if (!ieee80211_is_data_qos(hdr->frame_control) ||
  3423. + is_multicast_ether_addr(hdr->addr1))
  3424. goto dont_reorder;
  3425. /*
  3426. --- a/net/mac80211/scan.c
  3427. +++ b/net/mac80211/scan.c
  3428. @@ -526,7 +526,7 @@ static int __ieee80211_start_scan(struct
  3429. ieee80211_hw_config(local, 0);
  3430. if ((req->channels[0]->flags &
  3431. - IEEE80211_CHAN_PASSIVE_SCAN) ||
  3432. + IEEE80211_CHAN_NO_IR) ||
  3433. !local->scan_req->n_ssids) {
  3434. next_delay = IEEE80211_PASSIVE_CHANNEL_TIME;
  3435. } else {
  3436. @@ -572,7 +572,7 @@ ieee80211_scan_get_channel_time(struct i
  3437. * TODO: channel switching also consumes quite some time,
  3438. * add that delay as well to get a better estimation
  3439. */
  3440. - if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)
  3441. + if (chan->flags & IEEE80211_CHAN_NO_IR)
  3442. return IEEE80211_PASSIVE_CHANNEL_TIME;
  3443. return IEEE80211_PROBE_DELAY + IEEE80211_CHANNEL_TIME;
  3444. }
  3445. @@ -696,7 +696,7 @@ static void ieee80211_scan_state_set_cha
  3446. *
  3447. * In any case, it is not necessary for a passive scan.
  3448. */
  3449. - if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN ||
  3450. + if (chan->flags & IEEE80211_CHAN_NO_IR ||
  3451. !local->scan_req->n_ssids) {
  3452. *next_delay = IEEE80211_PASSIVE_CHANNEL_TIME;
  3453. local->next_scan_state = SCAN_DECISION;
  3454. @@ -881,7 +881,7 @@ int ieee80211_request_ibss_scan(struct i
  3455. struct ieee80211_channel *tmp_ch =
  3456. &local->hw.wiphy->bands[band]->channels[i];
  3457. - if (tmp_ch->flags & (IEEE80211_CHAN_NO_IBSS |
  3458. + if (tmp_ch->flags & (IEEE80211_CHAN_NO_IR |
  3459. IEEE80211_CHAN_DISABLED))
  3460. continue;
  3461. @@ -895,7 +895,7 @@ int ieee80211_request_ibss_scan(struct i
  3462. local->int_scan_req->n_channels = n_ch;
  3463. } else {
  3464. - if (WARN_ON_ONCE(chan->flags & (IEEE80211_CHAN_NO_IBSS |
  3465. + if (WARN_ON_ONCE(chan->flags & (IEEE80211_CHAN_NO_IR |
  3466. IEEE80211_CHAN_DISABLED)))
  3467. goto unlock;
  3468. --- a/net/mac80211/tx.c
  3469. +++ b/net/mac80211/tx.c
  3470. @@ -1728,8 +1728,7 @@ netdev_tx_t ieee80211_monitor_start_xmit
  3471. * radar detection by itself. We can do that later by adding a
  3472. * monitor flag interfaces used for AP support.
  3473. */
  3474. - if ((chan->flags & (IEEE80211_CHAN_NO_IBSS | IEEE80211_CHAN_RADAR |
  3475. - IEEE80211_CHAN_PASSIVE_SCAN)))
  3476. + if ((chan->flags & (IEEE80211_CHAN_NO_IR | IEEE80211_CHAN_RADAR)))
  3477. goto fail_rcu;
  3478. ieee80211_xmit(sdata, skb, chan->band);
  3479. --- a/net/mac80211/util.c
  3480. +++ b/net/mac80211/util.c
  3481. @@ -2259,14 +2259,17 @@ u64 ieee80211_calculate_rx_timestamp(str
  3482. void ieee80211_dfs_cac_cancel(struct ieee80211_local *local)
  3483. {
  3484. struct ieee80211_sub_if_data *sdata;
  3485. + struct cfg80211_chan_def chandef;
  3486. mutex_lock(&local->iflist_mtx);
  3487. list_for_each_entry(sdata, &local->interfaces, list) {
  3488. cancel_delayed_work_sync(&sdata->dfs_cac_timer_work);
  3489. if (sdata->wdev.cac_started) {
  3490. + chandef = sdata->vif.bss_conf.chandef;
  3491. ieee80211_vif_release_channel(sdata);
  3492. cfg80211_cac_event(sdata->dev,
  3493. + &chandef,
  3494. NL80211_RADAR_CAC_ABORTED,
  3495. GFP_KERNEL);
  3496. }
  3497. @@ -2459,14 +2462,9 @@ int ieee80211_send_action_csa(struct iee
  3498. WLAN_EID_CHAN_SWITCH_PARAM_TX_RESTRICT : 0x00;
  3499. put_unaligned_le16(WLAN_REASON_MESH_CHAN, pos); /* Reason Cd */
  3500. pos += 2;
  3501. - if (!ifmsh->pre_value)
  3502. - ifmsh->pre_value = 1;
  3503. - else
  3504. - ifmsh->pre_value++;
  3505. pre_value = cpu_to_le16(ifmsh->pre_value);
  3506. memcpy(pos, &pre_value, 2); /* Precedence Value */
  3507. pos += 2;
  3508. - ifmsh->chsw_init = true;
  3509. }
  3510. ieee80211_tx_skb(sdata, skb);
  3511. --- a/net/wireless/chan.c
  3512. +++ b/net/wireless/chan.c
  3513. @@ -277,6 +277,32 @@ void cfg80211_set_dfs_state(struct wiphy
  3514. width, dfs_state);
  3515. }
  3516. +static u32 cfg80211_get_start_freq(u32 center_freq,
  3517. + u32 bandwidth)
  3518. +{
  3519. + u32 start_freq;
  3520. +
  3521. + if (bandwidth <= 20)
  3522. + start_freq = center_freq;
  3523. + else
  3524. + start_freq = center_freq - bandwidth/2 + 10;
  3525. +
  3526. + return start_freq;
  3527. +}
  3528. +
  3529. +static u32 cfg80211_get_end_freq(u32 center_freq,
  3530. + u32 bandwidth)
  3531. +{
  3532. + u32 end_freq;
  3533. +
  3534. + if (bandwidth <= 20)
  3535. + end_freq = center_freq;
  3536. + else
  3537. + end_freq = center_freq + bandwidth/2 - 10;
  3538. +
  3539. + return end_freq;
  3540. +}
  3541. +
  3542. static int cfg80211_get_chans_dfs_required(struct wiphy *wiphy,
  3543. u32 center_freq,
  3544. u32 bandwidth)
  3545. @@ -284,13 +310,8 @@ static int cfg80211_get_chans_dfs_requir
  3546. struct ieee80211_channel *c;
  3547. u32 freq, start_freq, end_freq;
  3548. - if (bandwidth <= 20) {
  3549. - start_freq = center_freq;
  3550. - end_freq = center_freq;
  3551. - } else {
  3552. - start_freq = center_freq - bandwidth/2 + 10;
  3553. - end_freq = center_freq + bandwidth/2 - 10;
  3554. - }
  3555. + start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
  3556. + end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
  3557. for (freq = start_freq; freq <= end_freq; freq += 20) {
  3558. c = ieee80211_get_channel(wiphy, freq);
  3559. @@ -330,33 +351,159 @@ int cfg80211_chandef_dfs_required(struct
  3560. }
  3561. EXPORT_SYMBOL(cfg80211_chandef_dfs_required);
  3562. -static bool cfg80211_secondary_chans_ok(struct wiphy *wiphy,
  3563. - u32 center_freq, u32 bandwidth,
  3564. - u32 prohibited_flags)
  3565. +static int cfg80211_get_chans_dfs_usable(struct wiphy *wiphy,
  3566. + u32 center_freq,
  3567. + u32 bandwidth)
  3568. {
  3569. struct ieee80211_channel *c;
  3570. u32 freq, start_freq, end_freq;
  3571. + int count = 0;
  3572. - if (bandwidth <= 20) {
  3573. - start_freq = center_freq;
  3574. - end_freq = center_freq;
  3575. - } else {
  3576. - start_freq = center_freq - bandwidth/2 + 10;
  3577. - end_freq = center_freq + bandwidth/2 - 10;
  3578. + start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
  3579. + end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
  3580. +
  3581. + /*
  3582. + * Check entire range of channels for the bandwidth.
  3583. + * Check all channels are DFS channels (DFS_USABLE or
  3584. + * DFS_AVAILABLE). Return number of usable channels
  3585. + * (require CAC). Allow DFS and non-DFS channel mix.
  3586. + */
  3587. + for (freq = start_freq; freq <= end_freq; freq += 20) {
  3588. + c = ieee80211_get_channel(wiphy, freq);
  3589. + if (!c)
  3590. + return -EINVAL;
  3591. +
  3592. + if (c->flags & IEEE80211_CHAN_DISABLED)
  3593. + return -EINVAL;
  3594. +
  3595. + if (c->flags & IEEE80211_CHAN_RADAR) {
  3596. + if (c->dfs_state == NL80211_DFS_UNAVAILABLE)
  3597. + return -EINVAL;
  3598. +
  3599. + if (c->dfs_state == NL80211_DFS_USABLE)
  3600. + count++;
  3601. + }
  3602. + }
  3603. +
  3604. + return count;
  3605. +}
  3606. +
  3607. +bool cfg80211_chandef_dfs_usable(struct wiphy *wiphy,
  3608. + const struct cfg80211_chan_def *chandef)
  3609. +{
  3610. + int width;
  3611. + int r1, r2 = 0;
  3612. +
  3613. + if (WARN_ON(!cfg80211_chandef_valid(chandef)))
  3614. + return false;
  3615. +
  3616. + width = cfg80211_chandef_get_width(chandef);
  3617. + if (width < 0)
  3618. + return false;
  3619. +
  3620. + r1 = cfg80211_get_chans_dfs_usable(wiphy, chandef->center_freq1,
  3621. + width);
  3622. +
  3623. + if (r1 < 0)
  3624. + return false;
  3625. +
  3626. + switch (chandef->width) {
  3627. + case NL80211_CHAN_WIDTH_80P80:
  3628. + WARN_ON(!chandef->center_freq2);
  3629. + r2 = cfg80211_get_chans_dfs_usable(wiphy,
  3630. + chandef->center_freq2,
  3631. + width);
  3632. + if (r2 < 0)
  3633. + return false;
  3634. + break;
  3635. + default:
  3636. + WARN_ON(chandef->center_freq2);
  3637. + break;
  3638. }
  3639. + return (r1 + r2 > 0);
  3640. +}
  3641. +
  3642. +
  3643. +static bool cfg80211_get_chans_dfs_available(struct wiphy *wiphy,
  3644. + u32 center_freq,
  3645. + u32 bandwidth)
  3646. +{
  3647. + struct ieee80211_channel *c;
  3648. + u32 freq, start_freq, end_freq;
  3649. +
  3650. + start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
  3651. + end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
  3652. +
  3653. + /*
  3654. + * Check entire range of channels for the bandwidth.
  3655. + * If any channel in between is disabled or has not
  3656. + * had gone through CAC return false
  3657. + */
  3658. for (freq = start_freq; freq <= end_freq; freq += 20) {
  3659. c = ieee80211_get_channel(wiphy, freq);
  3660. if (!c)
  3661. return false;
  3662. - /* check for radar flags */
  3663. - if ((prohibited_flags & c->flags & IEEE80211_CHAN_RADAR) &&
  3664. + if (c->flags & IEEE80211_CHAN_DISABLED)
  3665. + return false;
  3666. +
  3667. + if ((c->flags & IEEE80211_CHAN_RADAR) &&
  3668. (c->dfs_state != NL80211_DFS_AVAILABLE))
  3669. return false;
  3670. + }
  3671. +
  3672. + return true;
  3673. +}
  3674. +
  3675. +static bool cfg80211_chandef_dfs_available(struct wiphy *wiphy,
  3676. + const struct cfg80211_chan_def *chandef)
  3677. +{
  3678. + int width;
  3679. + int r;
  3680. +
  3681. + if (WARN_ON(!cfg80211_chandef_valid(chandef)))
  3682. + return false;
  3683. - /* check for the other flags */
  3684. - if (c->flags & prohibited_flags & ~IEEE80211_CHAN_RADAR)
  3685. + width = cfg80211_chandef_get_width(chandef);
  3686. + if (width < 0)
  3687. + return false;
  3688. +
  3689. + r = cfg80211_get_chans_dfs_available(wiphy, chandef->center_freq1,
  3690. + width);
  3691. +
  3692. + /* If any of channels unavailable for cf1 just return */
  3693. + if (!r)
  3694. + return r;
  3695. +
  3696. + switch (chandef->width) {
  3697. + case NL80211_CHAN_WIDTH_80P80:
  3698. + WARN_ON(!chandef->center_freq2);
  3699. + r = cfg80211_get_chans_dfs_available(wiphy,
  3700. + chandef->center_freq2,
  3701. + width);
  3702. + default:
  3703. + WARN_ON(chandef->center_freq2);
  3704. + break;
  3705. + }
  3706. +
  3707. + return r;
  3708. +}
  3709. +
  3710. +
  3711. +static bool cfg80211_secondary_chans_ok(struct wiphy *wiphy,
  3712. + u32 center_freq, u32 bandwidth,
  3713. + u32 prohibited_flags)
  3714. +{
  3715. + struct ieee80211_channel *c;
  3716. + u32 freq, start_freq, end_freq;
  3717. +
  3718. + start_freq = cfg80211_get_start_freq(center_freq, bandwidth);
  3719. + end_freq = cfg80211_get_end_freq(center_freq, bandwidth);
  3720. +
  3721. + for (freq = start_freq; freq <= end_freq; freq += 20) {
  3722. + c = ieee80211_get_channel(wiphy, freq);
  3723. + if (!c || c->flags & prohibited_flags)
  3724. return false;
  3725. }
  3726. @@ -462,14 +609,19 @@ bool cfg80211_reg_can_beacon(struct wiph
  3727. struct cfg80211_chan_def *chandef)
  3728. {
  3729. bool res;
  3730. + u32 prohibited_flags = IEEE80211_CHAN_DISABLED |
  3731. + IEEE80211_CHAN_NO_IR |
  3732. + IEEE80211_CHAN_RADAR;
  3733. trace_cfg80211_reg_can_beacon(wiphy, chandef);
  3734. - res = cfg80211_chandef_usable(wiphy, chandef,
  3735. - IEEE80211_CHAN_DISABLED |
  3736. - IEEE80211_CHAN_PASSIVE_SCAN |
  3737. - IEEE80211_CHAN_NO_IBSS |
  3738. - IEEE80211_CHAN_RADAR);
  3739. + if (cfg80211_chandef_dfs_required(wiphy, chandef) > 0 &&
  3740. + cfg80211_chandef_dfs_available(wiphy, chandef)) {
  3741. + /* We can skip IEEE80211_CHAN_NO_IR if chandef dfs available */
  3742. + prohibited_flags = IEEE80211_CHAN_DISABLED;
  3743. + }
  3744. +
  3745. + res = cfg80211_chandef_usable(wiphy, chandef, prohibited_flags);
  3746. trace_cfg80211_return_bool(res);
  3747. return res;
  3748. --- a/net/wireless/core.h
  3749. +++ b/net/wireless/core.h
  3750. @@ -382,6 +382,19 @@ int cfg80211_can_use_iftype_chan(struct
  3751. enum cfg80211_chan_mode chanmode,
  3752. u8 radar_detect);
  3753. +/**
  3754. + * cfg80211_chandef_dfs_usable - checks if chandef is DFS usable
  3755. + * @wiphy: the wiphy to validate against
  3756. + * @chandef: the channel definition to check
  3757. + *
  3758. + * Checks if chandef is usable and we can/need start CAC on such channel.
  3759. + *
  3760. + * Return: Return true if all channels available and at least
  3761. + * one channel require CAC (NL80211_DFS_USABLE)
  3762. + */
  3763. +bool cfg80211_chandef_dfs_usable(struct wiphy *wiphy,
  3764. + const struct cfg80211_chan_def *chandef);
  3765. +
  3766. void cfg80211_set_dfs_state(struct wiphy *wiphy,
  3767. const struct cfg80211_chan_def *chandef,
  3768. enum nl80211_dfs_state dfs_state);
  3769. --- a/net/wireless/genregdb.awk
  3770. +++ b/net/wireless/genregdb.awk
  3771. @@ -107,10 +107,13 @@ active && /^[ \t]*\(/ {
  3772. } else if (flagarray[arg] == "PTMP-ONLY") {
  3773. flags = flags "\n\t\t\tNL80211_RRF_PTMP_ONLY | "
  3774. } else if (flagarray[arg] == "PASSIVE-SCAN") {
  3775. - flags = flags "\n\t\t\tNL80211_RRF_PASSIVE_SCAN | "
  3776. + flags = flags "\n\t\t\tNL80211_RRF_NO_IR | "
  3777. } else if (flagarray[arg] == "NO-IBSS") {
  3778. - flags = flags "\n\t\t\tNL80211_RRF_NO_IBSS | "
  3779. + flags = flags "\n\t\t\tNL80211_RRF_NO_IR | "
  3780. + } else if (flagarray[arg] == "NO-IR") {
  3781. + flags = flags "\n\t\t\tNL80211_RRF_NO_IR | "
  3782. }
  3783. +
  3784. }
  3785. flags = flags "0"
  3786. printf "\t\tREG_RULE(%d, %d, %d, %d, %d, %s),\n", start, end, bw, gain, power, flags
  3787. --- a/net/wireless/ibss.c
  3788. +++ b/net/wireless/ibss.c
  3789. @@ -274,7 +274,7 @@ int cfg80211_ibss_wext_join(struct cfg80
  3790. for (i = 0; i < sband->n_channels; i++) {
  3791. chan = &sband->channels[i];
  3792. - if (chan->flags & IEEE80211_CHAN_NO_IBSS)
  3793. + if (chan->flags & IEEE80211_CHAN_NO_IR)
  3794. continue;
  3795. if (chan->flags & IEEE80211_CHAN_DISABLED)
  3796. continue;
  3797. @@ -345,7 +345,7 @@ int cfg80211_ibss_wext_siwfreq(struct ne
  3798. chan = ieee80211_get_channel(wdev->wiphy, freq);
  3799. if (!chan)
  3800. return -EINVAL;
  3801. - if (chan->flags & IEEE80211_CHAN_NO_IBSS ||
  3802. + if (chan->flags & IEEE80211_CHAN_NO_IR ||
  3803. chan->flags & IEEE80211_CHAN_DISABLED)
  3804. return -EINVAL;
  3805. }
  3806. --- a/net/wireless/mesh.c
  3807. +++ b/net/wireless/mesh.c
  3808. @@ -141,8 +141,7 @@ int __cfg80211_join_mesh(struct cfg80211
  3809. for (i = 0; i < sband->n_channels; i++) {
  3810. chan = &sband->channels[i];
  3811. - if (chan->flags & (IEEE80211_CHAN_NO_IBSS |
  3812. - IEEE80211_CHAN_PASSIVE_SCAN |
  3813. + if (chan->flags & (IEEE80211_CHAN_NO_IR |
  3814. IEEE80211_CHAN_DISABLED |
  3815. IEEE80211_CHAN_RADAR))
  3816. continue;
  3817. --- a/net/wireless/mlme.c
  3818. +++ b/net/wireless/mlme.c
  3819. @@ -763,12 +763,12 @@ void cfg80211_radar_event(struct wiphy *
  3820. EXPORT_SYMBOL(cfg80211_radar_event);
  3821. void cfg80211_cac_event(struct net_device *netdev,
  3822. + const struct cfg80211_chan_def *chandef,
  3823. enum nl80211_radar_event event, gfp_t gfp)
  3824. {
  3825. struct wireless_dev *wdev = netdev->ieee80211_ptr;
  3826. struct wiphy *wiphy = wdev->wiphy;
  3827. struct cfg80211_registered_device *rdev = wiphy_to_dev(wiphy);
  3828. - struct cfg80211_chan_def chandef;
  3829. unsigned long timeout;
  3830. trace_cfg80211_cac_event(netdev, event);
  3831. @@ -779,14 +779,12 @@ void cfg80211_cac_event(struct net_devic
  3832. if (WARN_ON(!wdev->channel))
  3833. return;
  3834. - cfg80211_chandef_create(&chandef, wdev->channel, NL80211_CHAN_NO_HT);
  3835. -
  3836. switch (event) {
  3837. case NL80211_RADAR_CAC_FINISHED:
  3838. timeout = wdev->cac_start_time +
  3839. msecs_to_jiffies(IEEE80211_DFS_MIN_CAC_TIME_MS);
  3840. WARN_ON(!time_after_eq(jiffies, timeout));
  3841. - cfg80211_set_dfs_state(wiphy, &chandef, NL80211_DFS_AVAILABLE);
  3842. + cfg80211_set_dfs_state(wiphy, chandef, NL80211_DFS_AVAILABLE);
  3843. break;
  3844. case NL80211_RADAR_CAC_ABORTED:
  3845. break;
  3846. @@ -796,6 +794,6 @@ void cfg80211_cac_event(struct net_devic
  3847. }
  3848. wdev->cac_started = false;
  3849. - nl80211_radar_notify(rdev, &chandef, event, netdev, gfp);
  3850. + nl80211_radar_notify(rdev, chandef, event, netdev, gfp);
  3851. }
  3852. EXPORT_SYMBOL(cfg80211_cac_event);
  3853. --- a/net/wireless/nl80211.c
  3854. +++ b/net/wireless/nl80211.c
  3855. @@ -545,12 +545,12 @@ static int nl80211_msg_put_channel(struc
  3856. if ((chan->flags & IEEE80211_CHAN_DISABLED) &&
  3857. nla_put_flag(msg, NL80211_FREQUENCY_ATTR_DISABLED))
  3858. goto nla_put_failure;
  3859. - if ((chan->flags & IEEE80211_CHAN_PASSIVE_SCAN) &&
  3860. - nla_put_flag(msg, NL80211_FREQUENCY_ATTR_PASSIVE_SCAN))
  3861. - goto nla_put_failure;
  3862. - if ((chan->flags & IEEE80211_CHAN_NO_IBSS) &&
  3863. - nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_IBSS))
  3864. - goto nla_put_failure;
  3865. + if (chan->flags & IEEE80211_CHAN_NO_IR) {
  3866. + if (nla_put_flag(msg, NL80211_FREQUENCY_ATTR_NO_IR))
  3867. + goto nla_put_failure;
  3868. + if (nla_put_flag(msg, __NL80211_FREQUENCY_ATTR_NO_IBSS))
  3869. + goto nla_put_failure;
  3870. + }
  3871. if (chan->flags & IEEE80211_CHAN_RADAR) {
  3872. if (nla_put_flag(msg, NL80211_FREQUENCY_ATTR_RADAR))
  3873. goto nla_put_failure;
  3874. @@ -1229,7 +1229,8 @@ static int nl80211_send_wiphy(struct cfg
  3875. nla_put_flag(msg, NL80211_ATTR_TDLS_EXTERNAL_SETUP))
  3876. goto nla_put_failure;
  3877. if ((dev->wiphy.flags & WIPHY_FLAG_SUPPORTS_5_10_MHZ) &&
  3878. - nla_put_flag(msg, WIPHY_FLAG_SUPPORTS_5_10_MHZ))
  3879. + (nla_put_flag(msg, NL80211_ATTR_SUPPORT_5_MHZ) ||
  3880. + nla_put_flag(msg, NL80211_ATTR_SUPPORT_10_MHZ)))
  3881. goto nla_put_failure;
  3882. state->split_start++;
  3883. @@ -2170,7 +2171,7 @@ static inline u64 wdev_id(struct wireles
  3884. }
  3885. static int nl80211_send_chandef(struct sk_buff *msg,
  3886. - struct cfg80211_chan_def *chandef)
  3887. + const struct cfg80211_chan_def *chandef)
  3888. {
  3889. WARN_ON(!cfg80211_chandef_valid(chandef));
  3890. @@ -3219,6 +3220,7 @@ static int nl80211_start_ap(struct sk_bu
  3891. return PTR_ERR(params.acl);
  3892. }
  3893. + wdev_lock(wdev);
  3894. err = rdev_start_ap(rdev, dev, &params);
  3895. if (!err) {
  3896. wdev->preset_chandef = params.chandef;
  3897. @@ -3227,6 +3229,7 @@ static int nl80211_start_ap(struct sk_bu
  3898. wdev->ssid_len = params.ssid_len;
  3899. memcpy(wdev->ssid, params.ssid, wdev->ssid_len);
  3900. }
  3901. + wdev_unlock(wdev);
  3902. kfree(params.acl);
  3903. @@ -3255,7 +3258,11 @@ static int nl80211_set_beacon(struct sk_
  3904. if (err)
  3905. return err;
  3906. - return rdev_change_beacon(rdev, dev, &params);
  3907. + wdev_lock(wdev);
  3908. + err = rdev_change_beacon(rdev, dev, &params);
  3909. + wdev_unlock(wdev);
  3910. +
  3911. + return err;
  3912. }
  3913. static int nl80211_stop_ap(struct sk_buff *skb, struct genl_info *info)
  3914. @@ -4461,7 +4468,9 @@ static int nl80211_set_bss(struct sk_buf
  3915. {
  3916. struct cfg80211_registered_device *rdev = info->user_ptr[0];
  3917. struct net_device *dev = info->user_ptr[1];
  3918. + struct wireless_dev *wdev = dev->ieee80211_ptr;
  3919. struct bss_parameters params;
  3920. + int err;
  3921. memset(&params, 0, sizeof(params));
  3922. /* default to not changing parameters */
  3923. @@ -4527,7 +4536,11 @@ static int nl80211_set_bss(struct sk_buf
  3924. dev->ieee80211_ptr->iftype != NL80211_IFTYPE_P2P_GO)
  3925. return -EOPNOTSUPP;
  3926. - return rdev_change_bss(rdev, dev, &params);
  3927. + wdev_lock(wdev);
  3928. + err = rdev_change_bss(rdev, dev, &params);
  3929. + wdev_unlock(wdev);
  3930. +
  3931. + return err;
  3932. }
  3933. static const struct nla_policy reg_rule_policy[NL80211_REG_RULE_ATTR_MAX + 1] = {
  3934. @@ -5653,7 +5666,7 @@ static int nl80211_start_radar_detection
  3935. if (err == 0)
  3936. return -EINVAL;
  3937. - if (chandef.chan->dfs_state != NL80211_DFS_USABLE)
  3938. + if (!cfg80211_chandef_dfs_usable(wdev->wiphy, &chandef))
  3939. return -EINVAL;
  3940. if (!rdev->ops->start_radar_detection)
  3941. @@ -5793,7 +5806,11 @@ skip_beacons:
  3942. if (info->attrs[NL80211_ATTR_CH_SWITCH_BLOCK_TX])
  3943. params.block_tx = true;
  3944. - return rdev_channel_switch(rdev, dev, &params);
  3945. + wdev_lock(wdev);
  3946. + err = rdev_channel_switch(rdev, dev, &params);
  3947. + wdev_unlock(wdev);
  3948. +
  3949. + return err;
  3950. }
  3951. static int nl80211_send_bss(struct sk_buff *msg, struct netlink_callback *cb,
  3952. @@ -10809,21 +10826,18 @@ void cfg80211_ch_switch_notify(struct ne
  3953. struct wiphy *wiphy = wdev->wiphy;
  3954. struct cfg80211_registered_device *rdev = wiphy_to_dev(wiphy);
  3955. - trace_cfg80211_ch_switch_notify(dev, chandef);
  3956. + ASSERT_WDEV_LOCK(wdev);
  3957. - wdev_lock(wdev);
  3958. + trace_cfg80211_ch_switch_notify(dev, chandef);
  3959. if (WARN_ON(wdev->iftype != NL80211_IFTYPE_AP &&
  3960. wdev->iftype != NL80211_IFTYPE_P2P_GO &&
  3961. wdev->iftype != NL80211_IFTYPE_ADHOC &&
  3962. wdev->iftype != NL80211_IFTYPE_MESH_POINT))
  3963. - goto out;
  3964. + return;
  3965. wdev->channel = chandef->chan;
  3966. nl80211_ch_switch_notify(rdev, dev, chandef, GFP_KERNEL);
  3967. -out:
  3968. - wdev_unlock(wdev);
  3969. - return;
  3970. }
  3971. EXPORT_SYMBOL(cfg80211_ch_switch_notify);
  3972. @@ -10882,7 +10896,7 @@ EXPORT_SYMBOL(cfg80211_cqm_txe_notify);
  3973. void
  3974. nl80211_radar_notify(struct cfg80211_registered_device *rdev,
  3975. - struct cfg80211_chan_def *chandef,
  3976. + const struct cfg80211_chan_def *chandef,
  3977. enum nl80211_radar_event event,
  3978. struct net_device *netdev, gfp_t gfp)
  3979. {
  3980. --- a/net/wireless/nl80211.h
  3981. +++ b/net/wireless/nl80211.h
  3982. @@ -70,7 +70,7 @@ int nl80211_send_mgmt(struct cfg80211_re
  3983. void
  3984. nl80211_radar_notify(struct cfg80211_registered_device *rdev,
  3985. - struct cfg80211_chan_def *chandef,
  3986. + const struct cfg80211_chan_def *chandef,
  3987. enum nl80211_radar_event event,
  3988. struct net_device *netdev, gfp_t gfp);
  3989. --- a/net/wireless/reg.c
  3990. +++ b/net/wireless/reg.c
  3991. @@ -163,35 +163,29 @@ static const struct ieee80211_regdomain
  3992. REG_RULE(2412-10, 2462+10, 40, 6, 20, 0),
  3993. /* IEEE 802.11b/g, channels 12..13. */
  3994. REG_RULE(2467-10, 2472+10, 40, 6, 20,
  3995. - NL80211_RRF_PASSIVE_SCAN |
  3996. - NL80211_RRF_NO_IBSS),
  3997. + NL80211_RRF_NO_IR),
  3998. /* IEEE 802.11 channel 14 - Only JP enables
  3999. * this and for 802.11b only */
  4000. REG_RULE(2484-10, 2484+10, 20, 6, 20,
  4001. - NL80211_RRF_PASSIVE_SCAN |
  4002. - NL80211_RRF_NO_IBSS |
  4003. + NL80211_RRF_NO_IR |
  4004. NL80211_RRF_NO_OFDM),
  4005. /* IEEE 802.11a, channel 36..48 */
  4006. REG_RULE(5180-10, 5240+10, 160, 6, 20,
  4007. - NL80211_RRF_PASSIVE_SCAN |
  4008. - NL80211_RRF_NO_IBSS),
  4009. + NL80211_RRF_NO_IR),
  4010. /* IEEE 802.11a, channel 52..64 - DFS required */
  4011. REG_RULE(5260-10, 5320+10, 160, 6, 20,
  4012. - NL80211_RRF_PASSIVE_SCAN |
  4013. - NL80211_RRF_NO_IBSS |
  4014. + NL80211_RRF_NO_IR |
  4015. NL80211_RRF_DFS),
  4016. /* IEEE 802.11a, channel 100..144 - DFS required */
  4017. REG_RULE(5500-10, 5720+10, 160, 6, 20,
  4018. - NL80211_RRF_PASSIVE_SCAN |
  4019. - NL80211_RRF_NO_IBSS |
  4020. + NL80211_RRF_NO_IR |
  4021. NL80211_RRF_DFS),
  4022. /* IEEE 802.11a, channel 149..165 */
  4023. REG_RULE(5745-10, 5825+10, 80, 6, 20,
  4024. - NL80211_RRF_PASSIVE_SCAN |
  4025. - NL80211_RRF_NO_IBSS),
  4026. + NL80211_RRF_NO_IR),
  4027. /* IEEE 802.11ad (60gHz), channels 1..3 */
  4028. REG_RULE(56160+2160*1-1080, 56160+2160*3+1080, 2160, 0, 0, 0),
  4029. @@ -698,10 +692,8 @@ regdom_intersect(const struct ieee80211_
  4030. static u32 map_regdom_flags(u32 rd_flags)
  4031. {
  4032. u32 channel_flags = 0;
  4033. - if (rd_flags & NL80211_RRF_PASSIVE_SCAN)
  4034. - channel_flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4035. - if (rd_flags & NL80211_RRF_NO_IBSS)
  4036. - channel_flags |= IEEE80211_CHAN_NO_IBSS;
  4037. + if (rd_flags & NL80211_RRF_NO_IR_ALL)
  4038. + channel_flags |= IEEE80211_CHAN_NO_IR;
  4039. if (rd_flags & NL80211_RRF_DFS)
  4040. channel_flags |= IEEE80211_CHAN_RADAR;
  4041. if (rd_flags & NL80211_RRF_NO_OFDM)
  4042. @@ -1066,13 +1058,8 @@ static void handle_reg_beacon(struct wip
  4043. chan_before.center_freq = chan->center_freq;
  4044. chan_before.flags = chan->flags;
  4045. - if (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN) {
  4046. - chan->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
  4047. - channel_changed = true;
  4048. - }
  4049. -
  4050. - if (chan->flags & IEEE80211_CHAN_NO_IBSS) {
  4051. - chan->flags &= ~IEEE80211_CHAN_NO_IBSS;
  4052. + if (chan->flags & IEEE80211_CHAN_NO_IR) {
  4053. + chan->flags &= ~IEEE80211_CHAN_NO_IR;
  4054. channel_changed = true;
  4055. }
  4056. --- /dev/null
  4057. +++ b/drivers/net/wireless/ath/ath9k/ar9003_wow.c
  4058. @@ -0,0 +1,422 @@
  4059. +/*
  4060. + * Copyright (c) 2012 Qualcomm Atheros, Inc.
  4061. + *
  4062. + * Permission to use, copy, modify, and/or distribute this software for any
  4063. + * purpose with or without fee is hereby granted, provided that the above
  4064. + * copyright notice and this permission notice appear in all copies.
  4065. + *
  4066. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  4067. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  4068. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  4069. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  4070. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  4071. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  4072. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  4073. + */
  4074. +
  4075. +#include <linux/export.h>
  4076. +#include "ath9k.h"
  4077. +#include "reg.h"
  4078. +#include "hw-ops.h"
  4079. +
  4080. +const char *ath9k_hw_wow_event_to_string(u32 wow_event)
  4081. +{
  4082. + if (wow_event & AH_WOW_MAGIC_PATTERN_EN)
  4083. + return "Magic pattern";
  4084. + if (wow_event & AH_WOW_USER_PATTERN_EN)
  4085. + return "User pattern";
  4086. + if (wow_event & AH_WOW_LINK_CHANGE)
  4087. + return "Link change";
  4088. + if (wow_event & AH_WOW_BEACON_MISS)
  4089. + return "Beacon miss";
  4090. +
  4091. + return "unknown reason";
  4092. +}
  4093. +EXPORT_SYMBOL(ath9k_hw_wow_event_to_string);
  4094. +
  4095. +static void ath9k_hw_set_powermode_wow_sleep(struct ath_hw *ah)
  4096. +{
  4097. + struct ath_common *common = ath9k_hw_common(ah);
  4098. +
  4099. + REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
  4100. +
  4101. + /* set rx disable bit */
  4102. + REG_WRITE(ah, AR_CR, AR_CR_RXD);
  4103. +
  4104. + if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
  4105. + ath_err(common, "Failed to stop Rx DMA in 10ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
  4106. + REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
  4107. + return;
  4108. + }
  4109. +
  4110. + REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
  4111. +}
  4112. +
  4113. +static void ath9k_wow_create_keep_alive_pattern(struct ath_hw *ah)
  4114. +{
  4115. + struct ath_common *common = ath9k_hw_common(ah);
  4116. + u8 sta_mac_addr[ETH_ALEN], ap_mac_addr[ETH_ALEN];
  4117. + u32 ctl[13] = {0};
  4118. + u32 data_word[KAL_NUM_DATA_WORDS];
  4119. + u8 i;
  4120. + u32 wow_ka_data_word0;
  4121. +
  4122. + memcpy(sta_mac_addr, common->macaddr, ETH_ALEN);
  4123. + memcpy(ap_mac_addr, common->curbssid, ETH_ALEN);
  4124. +
  4125. + /* set the transmit buffer */
  4126. + ctl[0] = (KAL_FRAME_LEN | (MAX_RATE_POWER << 16));
  4127. + ctl[1] = 0;
  4128. + ctl[3] = 0xb; /* OFDM_6M hardware value for this rate */
  4129. + ctl[4] = 0;
  4130. + ctl[7] = (ah->txchainmask) << 2;
  4131. + ctl[2] = 0xf << 16; /* tx_tries 0 */
  4132. +
  4133. + for (i = 0; i < KAL_NUM_DESC_WORDS; i++)
  4134. + REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
  4135. +
  4136. + REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
  4137. +
  4138. + data_word[0] = (KAL_FRAME_TYPE << 2) | (KAL_FRAME_SUB_TYPE << 4) |
  4139. + (KAL_TO_DS << 8) | (KAL_DURATION_ID << 16);
  4140. + data_word[1] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
  4141. + (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
  4142. + data_word[2] = (sta_mac_addr[1] << 24) | (sta_mac_addr[0] << 16) |
  4143. + (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
  4144. + data_word[3] = (sta_mac_addr[5] << 24) | (sta_mac_addr[4] << 16) |
  4145. + (sta_mac_addr[3] << 8) | (sta_mac_addr[2]);
  4146. + data_word[4] = (ap_mac_addr[3] << 24) | (ap_mac_addr[2] << 16) |
  4147. + (ap_mac_addr[1] << 8) | (ap_mac_addr[0]);
  4148. + data_word[5] = (ap_mac_addr[5] << 8) | (ap_mac_addr[4]);
  4149. +
  4150. + if (AR_SREV_9462_20(ah)) {
  4151. + /* AR9462 2.0 has an extra descriptor word (time based
  4152. + * discard) compared to other chips */
  4153. + REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0);
  4154. + wow_ka_data_word0 = AR_WOW_TXBUF(13);
  4155. + } else {
  4156. + wow_ka_data_word0 = AR_WOW_TXBUF(12);
  4157. + }
  4158. +
  4159. + for (i = 0; i < KAL_NUM_DATA_WORDS; i++)
  4160. + REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]);
  4161. +
  4162. +}
  4163. +
  4164. +void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
  4165. + u8 *user_mask, int pattern_count,
  4166. + int pattern_len)
  4167. +{
  4168. + int i;
  4169. + u32 pattern_val, mask_val;
  4170. + u32 set, clr;
  4171. +
  4172. + /* FIXME: should check count by querying the hardware capability */
  4173. + if (pattern_count >= MAX_NUM_PATTERN)
  4174. + return;
  4175. +
  4176. + REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
  4177. +
  4178. + /* set the registers for pattern */
  4179. + for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
  4180. + memcpy(&pattern_val, user_pattern, 4);
  4181. + REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
  4182. + pattern_val);
  4183. + user_pattern += 4;
  4184. + }
  4185. +
  4186. + /* set the registers for mask */
  4187. + for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
  4188. + memcpy(&mask_val, user_mask, 4);
  4189. + REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
  4190. + user_mask += 4;
  4191. + }
  4192. +
  4193. + /* set the pattern length to be matched
  4194. + *
  4195. + * AR_WOW_LENGTH1_REG1
  4196. + * bit 31:24 pattern 0 length
  4197. + * bit 23:16 pattern 1 length
  4198. + * bit 15:8 pattern 2 length
  4199. + * bit 7:0 pattern 3 length
  4200. + *
  4201. + * AR_WOW_LENGTH1_REG2
  4202. + * bit 31:24 pattern 4 length
  4203. + * bit 23:16 pattern 5 length
  4204. + * bit 15:8 pattern 6 length
  4205. + * bit 7:0 pattern 7 length
  4206. + *
  4207. + * the below logic writes out the new
  4208. + * pattern length for the corresponding
  4209. + * pattern_count, while masking out the
  4210. + * other fields
  4211. + */
  4212. +
  4213. + ah->wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
  4214. +
  4215. + if (pattern_count < 4) {
  4216. + /* Pattern 0-3 uses AR_WOW_LENGTH1 register */
  4217. + set = (pattern_len & AR_WOW_LENGTH_MAX) <<
  4218. + AR_WOW_LEN1_SHIFT(pattern_count);
  4219. + clr = AR_WOW_LENGTH1_MASK(pattern_count);
  4220. + REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
  4221. + } else {
  4222. + /* Pattern 4-7 uses AR_WOW_LENGTH2 register */
  4223. + set = (pattern_len & AR_WOW_LENGTH_MAX) <<
  4224. + AR_WOW_LEN2_SHIFT(pattern_count);
  4225. + clr = AR_WOW_LENGTH2_MASK(pattern_count);
  4226. + REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
  4227. + }
  4228. +
  4229. +}
  4230. +EXPORT_SYMBOL(ath9k_hw_wow_apply_pattern);
  4231. +
  4232. +u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
  4233. +{
  4234. + u32 wow_status = 0;
  4235. + u32 val = 0, rval;
  4236. +
  4237. + /*
  4238. + * read the WoW status register to know
  4239. + * the wakeup reason
  4240. + */
  4241. + rval = REG_READ(ah, AR_WOW_PATTERN);
  4242. + val = AR_WOW_STATUS(rval);
  4243. +
  4244. + /*
  4245. + * mask only the WoW events that we have enabled. Sometimes
  4246. + * we have spurious WoW events from the AR_WOW_PATTERN
  4247. + * register. This mask will clean it up.
  4248. + */
  4249. +
  4250. + val &= ah->wow_event_mask;
  4251. +
  4252. + if (val) {
  4253. + if (val & AR_WOW_MAGIC_PAT_FOUND)
  4254. + wow_status |= AH_WOW_MAGIC_PATTERN_EN;
  4255. + if (AR_WOW_PATTERN_FOUND(val))
  4256. + wow_status |= AH_WOW_USER_PATTERN_EN;
  4257. + if (val & AR_WOW_KEEP_ALIVE_FAIL)
  4258. + wow_status |= AH_WOW_LINK_CHANGE;
  4259. + if (val & AR_WOW_BEACON_FAIL)
  4260. + wow_status |= AH_WOW_BEACON_MISS;
  4261. + }
  4262. +
  4263. + /*
  4264. + * set and clear WOW_PME_CLEAR registers for the chip to
  4265. + * generate next wow signal.
  4266. + * disable D3 before accessing other registers ?
  4267. + */
  4268. +
  4269. + /* do we need to check the bit value 0x01000000 (7-10) ?? */
  4270. + REG_RMW(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR,
  4271. + AR_PMCTRL_PWR_STATE_D1D3);
  4272. +
  4273. + /*
  4274. + * clear all events
  4275. + */
  4276. + REG_WRITE(ah, AR_WOW_PATTERN,
  4277. + AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN)));
  4278. +
  4279. + /*
  4280. + * restore the beacon threshold to init value
  4281. + */
  4282. + REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
  4283. +
  4284. + /*
  4285. + * Restore the way the PCI-E reset, Power-On-Reset, external
  4286. + * PCIE_POR_SHORT pins are tied to its original value.
  4287. + * Previously just before WoW sleep, we untie the PCI-E
  4288. + * reset to our Chip's Power On Reset so that any PCI-E
  4289. + * reset from the bus will not reset our chip
  4290. + */
  4291. + if (ah->is_pciexpress)
  4292. + ath9k_hw_configpcipowersave(ah, false);
  4293. +
  4294. + ah->wow_event_mask = 0;
  4295. +
  4296. + return wow_status;
  4297. +}
  4298. +EXPORT_SYMBOL(ath9k_hw_wow_wakeup);
  4299. +
  4300. +void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
  4301. +{
  4302. + u32 wow_event_mask;
  4303. + u32 set, clr;
  4304. +
  4305. + /*
  4306. + * wow_event_mask is a mask to the AR_WOW_PATTERN register to
  4307. + * indicate which WoW events we have enabled. The WoW events
  4308. + * are from the 'pattern_enable' in this function and
  4309. + * 'pattern_count' of ath9k_hw_wow_apply_pattern()
  4310. + */
  4311. + wow_event_mask = ah->wow_event_mask;
  4312. +
  4313. + /*
  4314. + * Untie Power-on-Reset from the PCI-E-Reset. When we are in
  4315. + * WOW sleep, we do want the Reset from the PCI-E to disturb
  4316. + * our hw state
  4317. + */
  4318. + if (ah->is_pciexpress) {
  4319. + /*
  4320. + * we need to untie the internal POR (power-on-reset)
  4321. + * to the external PCI-E reset. We also need to tie
  4322. + * the PCI-E Phy reset to the PCI-E reset.
  4323. + */
  4324. + set = AR_WA_RESET_EN | AR_WA_POR_SHORT;
  4325. + clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE;
  4326. + REG_RMW(ah, AR_WA, set, clr);
  4327. + }
  4328. +
  4329. + /*
  4330. + * set the power states appropriately and enable PME
  4331. + */
  4332. + set = AR_PMCTRL_HOST_PME_EN | AR_PMCTRL_PWR_PM_CTRL_ENA |
  4333. + AR_PMCTRL_AUX_PWR_DET | AR_PMCTRL_WOW_PME_CLR;
  4334. +
  4335. + /*
  4336. + * set and clear WOW_PME_CLEAR registers for the chip
  4337. + * to generate next wow signal.
  4338. + */
  4339. + REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
  4340. + clr = AR_PMCTRL_WOW_PME_CLR;
  4341. + REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
  4342. +
  4343. + /*
  4344. + * Setup for:
  4345. + * - beacon misses
  4346. + * - magic pattern
  4347. + * - keep alive timeout
  4348. + * - pattern matching
  4349. + */
  4350. +
  4351. + /*
  4352. + * Program default values for pattern backoff, aifs/slot/KAL count,
  4353. + * beacon miss timeout, KAL timeout, etc.
  4354. + */
  4355. + set = AR_WOW_BACK_OFF_SHIFT(AR_WOW_PAT_BACKOFF);
  4356. + REG_SET_BIT(ah, AR_WOW_PATTERN, set);
  4357. +
  4358. + set = AR_WOW_AIFS_CNT(AR_WOW_CNT_AIFS_CNT) |
  4359. + AR_WOW_SLOT_CNT(AR_WOW_CNT_SLOT_CNT) |
  4360. + AR_WOW_KEEP_ALIVE_CNT(AR_WOW_CNT_KA_CNT);
  4361. + REG_SET_BIT(ah, AR_WOW_COUNT, set);
  4362. +
  4363. + if (pattern_enable & AH_WOW_BEACON_MISS)
  4364. + set = AR_WOW_BEACON_TIMO;
  4365. + /* We are not using beacon miss, program a large value */
  4366. + else
  4367. + set = AR_WOW_BEACON_TIMO_MAX;
  4368. +
  4369. + REG_WRITE(ah, AR_WOW_BCN_TIMO, set);
  4370. +
  4371. + /*
  4372. + * Keep alive timo in ms except AR9280
  4373. + */
  4374. + if (!pattern_enable)
  4375. + set = AR_WOW_KEEP_ALIVE_NEVER;
  4376. + else
  4377. + set = KAL_TIMEOUT * 32;
  4378. +
  4379. + REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO, set);
  4380. +
  4381. + /*
  4382. + * Keep alive delay in us. based on 'power on clock',
  4383. + * therefore in usec
  4384. + */
  4385. + set = KAL_DELAY * 1000;
  4386. + REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY, set);
  4387. +
  4388. + /*
  4389. + * Create keep alive pattern to respond to beacons
  4390. + */
  4391. + ath9k_wow_create_keep_alive_pattern(ah);
  4392. +
  4393. + /*
  4394. + * Configure MAC WoW Registers
  4395. + */
  4396. + set = 0;
  4397. + /* Send keep alive timeouts anyway */
  4398. + clr = AR_WOW_KEEP_ALIVE_AUTO_DIS;
  4399. +
  4400. + if (pattern_enable & AH_WOW_LINK_CHANGE)
  4401. + wow_event_mask |= AR_WOW_KEEP_ALIVE_FAIL;
  4402. + else
  4403. + set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
  4404. +
  4405. + set = AR_WOW_KEEP_ALIVE_FAIL_DIS;
  4406. + REG_RMW(ah, AR_WOW_KEEP_ALIVE, set, clr);
  4407. +
  4408. + /*
  4409. + * we are relying on a bmiss failure. ensure we have
  4410. + * enough threshold to prevent false positives
  4411. + */
  4412. + REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
  4413. + AR_WOW_BMISSTHRESHOLD);
  4414. +
  4415. + set = 0;
  4416. + clr = 0;
  4417. +
  4418. + if (pattern_enable & AH_WOW_BEACON_MISS) {
  4419. + set = AR_WOW_BEACON_FAIL_EN;
  4420. + wow_event_mask |= AR_WOW_BEACON_FAIL;
  4421. + } else {
  4422. + clr = AR_WOW_BEACON_FAIL_EN;
  4423. + }
  4424. +
  4425. + REG_RMW(ah, AR_WOW_BCN_EN, set, clr);
  4426. +
  4427. + set = 0;
  4428. + clr = 0;
  4429. + /*
  4430. + * Enable the magic packet registers
  4431. + */
  4432. + if (pattern_enable & AH_WOW_MAGIC_PATTERN_EN) {
  4433. + set = AR_WOW_MAGIC_EN;
  4434. + wow_event_mask |= AR_WOW_MAGIC_PAT_FOUND;
  4435. + } else {
  4436. + clr = AR_WOW_MAGIC_EN;
  4437. + }
  4438. + set |= AR_WOW_MAC_INTR_EN;
  4439. + REG_RMW(ah, AR_WOW_PATTERN, set, clr);
  4440. +
  4441. + REG_WRITE(ah, AR_WOW_PATTERN_MATCH_LT_256B,
  4442. + AR_WOW_PATTERN_SUPPORTED);
  4443. +
  4444. + /*
  4445. + * Set the power states appropriately and enable PME
  4446. + */
  4447. + clr = 0;
  4448. + set = AR_PMCTRL_PWR_STATE_D1D3 | AR_PMCTRL_HOST_PME_EN |
  4449. + AR_PMCTRL_PWR_PM_CTRL_ENA;
  4450. +
  4451. + clr = AR_PCIE_PM_CTRL_ENA;
  4452. + REG_RMW(ah, AR_PCIE_PM_CTRL, set, clr);
  4453. +
  4454. + /*
  4455. + * this is needed to prevent the chip waking up
  4456. + * the host within 3-4 seconds with certain
  4457. + * platform/BIOS. The fix is to enable
  4458. + * D1 & D3 to match original definition and
  4459. + * also match the OTP value. Anyway this
  4460. + * is more related to SW WOW.
  4461. + */
  4462. + clr = AR_PMCTRL_PWR_STATE_D1D3;
  4463. + REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, clr);
  4464. +
  4465. + set = AR_PMCTRL_PWR_STATE_D1D3_REAL;
  4466. + REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set);
  4467. +
  4468. + REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
  4469. +
  4470. + /* to bring down WOW power low margin */
  4471. + set = BIT(13);
  4472. + REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set);
  4473. + /* HW WoW */
  4474. + clr = BIT(5);
  4475. + REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, clr);
  4476. +
  4477. + ath9k_hw_set_powermode_wow_sleep(ah);
  4478. + ah->wow_event_mask = wow_event_mask;
  4479. +}
  4480. +EXPORT_SYMBOL(ath9k_hw_wow_enable);
  4481. --- /dev/null
  4482. +++ b/drivers/net/wireless/ath/ath9k/tx99.c
  4483. @@ -0,0 +1,263 @@
  4484. +/*
  4485. + * Copyright (c) 2013 Qualcomm Atheros, Inc.
  4486. + *
  4487. + * Permission to use, copy, modify, and/or distribute this software for any
  4488. + * purpose with or without fee is hereby granted, provided that the above
  4489. + * copyright notice and this permission notice appear in all copies.
  4490. + *
  4491. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  4492. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  4493. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  4494. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  4495. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  4496. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  4497. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  4498. + */
  4499. +
  4500. +#include "ath9k.h"
  4501. +
  4502. +static void ath9k_tx99_stop(struct ath_softc *sc)
  4503. +{
  4504. + struct ath_hw *ah = sc->sc_ah;
  4505. + struct ath_common *common = ath9k_hw_common(ah);
  4506. +
  4507. + ath_drain_all_txq(sc);
  4508. + ath_startrecv(sc);
  4509. +
  4510. + ath9k_hw_set_interrupts(ah);
  4511. + ath9k_hw_enable_interrupts(ah);
  4512. +
  4513. + ieee80211_wake_queues(sc->hw);
  4514. +
  4515. + kfree_skb(sc->tx99_skb);
  4516. + sc->tx99_skb = NULL;
  4517. + sc->tx99_state = false;
  4518. +
  4519. + ath9k_hw_tx99_stop(sc->sc_ah);
  4520. + ath_dbg(common, XMIT, "TX99 stopped\n");
  4521. +}
  4522. +
  4523. +static struct sk_buff *ath9k_build_tx99_skb(struct ath_softc *sc)
  4524. +{
  4525. + static u8 PN9Data[] = {0xff, 0x87, 0xb8, 0x59, 0xb7, 0xa1, 0xcc, 0x24,
  4526. + 0x57, 0x5e, 0x4b, 0x9c, 0x0e, 0xe9, 0xea, 0x50,
  4527. + 0x2a, 0xbe, 0xb4, 0x1b, 0xb6, 0xb0, 0x5d, 0xf1,
  4528. + 0xe6, 0x9a, 0xe3, 0x45, 0xfd, 0x2c, 0x53, 0x18,
  4529. + 0x0c, 0xca, 0xc9, 0xfb, 0x49, 0x37, 0xe5, 0xa8,
  4530. + 0x51, 0x3b, 0x2f, 0x61, 0xaa, 0x72, 0x18, 0x84,
  4531. + 0x02, 0x23, 0x23, 0xab, 0x63, 0x89, 0x51, 0xb3,
  4532. + 0xe7, 0x8b, 0x72, 0x90, 0x4c, 0xe8, 0xfb, 0xc0};
  4533. + u32 len = 1200;
  4534. + struct ieee80211_hw *hw = sc->hw;
  4535. + struct ieee80211_hdr *hdr;
  4536. + struct ieee80211_tx_info *tx_info;
  4537. + struct sk_buff *skb;
  4538. +
  4539. + skb = alloc_skb(len, GFP_KERNEL);
  4540. + if (!skb)
  4541. + return NULL;
  4542. +
  4543. + skb_put(skb, len);
  4544. +
  4545. + memset(skb->data, 0, len);
  4546. +
  4547. + hdr = (struct ieee80211_hdr *)skb->data;
  4548. + hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA);
  4549. + hdr->duration_id = 0;
  4550. +
  4551. + memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  4552. + memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  4553. + memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  4554. +
  4555. + hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  4556. +
  4557. + tx_info = IEEE80211_SKB_CB(skb);
  4558. + memset(tx_info, 0, sizeof(*tx_info));
  4559. + tx_info->band = hw->conf.chandef.chan->band;
  4560. + tx_info->flags = IEEE80211_TX_CTL_NO_ACK;
  4561. + tx_info->control.vif = sc->tx99_vif;
  4562. +
  4563. + memcpy(skb->data + sizeof(*hdr), PN9Data, sizeof(PN9Data));
  4564. +
  4565. + return skb;
  4566. +}
  4567. +
  4568. +static void ath9k_tx99_deinit(struct ath_softc *sc)
  4569. +{
  4570. + ath_reset(sc);
  4571. +
  4572. + ath9k_ps_wakeup(sc);
  4573. + ath9k_tx99_stop(sc);
  4574. + ath9k_ps_restore(sc);
  4575. +}
  4576. +
  4577. +static int ath9k_tx99_init(struct ath_softc *sc)
  4578. +{
  4579. + struct ieee80211_hw *hw = sc->hw;
  4580. + struct ath_hw *ah = sc->sc_ah;
  4581. + struct ath_common *common = ath9k_hw_common(ah);
  4582. + struct ath_tx_control txctl;
  4583. + int r;
  4584. +
  4585. + if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  4586. + ath_err(common,
  4587. + "driver is in invalid state unable to use TX99");
  4588. + return -EINVAL;
  4589. + }
  4590. +
  4591. + sc->tx99_skb = ath9k_build_tx99_skb(sc);
  4592. + if (!sc->tx99_skb)
  4593. + return -ENOMEM;
  4594. +
  4595. + memset(&txctl, 0, sizeof(txctl));
  4596. + txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO];
  4597. +
  4598. + ath_reset(sc);
  4599. +
  4600. + ath9k_ps_wakeup(sc);
  4601. +
  4602. + ath9k_hw_disable_interrupts(ah);
  4603. + atomic_set(&ah->intr_ref_cnt, -1);
  4604. + ath_drain_all_txq(sc);
  4605. + ath_stoprecv(sc);
  4606. +
  4607. + sc->tx99_state = true;
  4608. +
  4609. + ieee80211_stop_queues(hw);
  4610. +
  4611. + if (sc->tx99_power == MAX_RATE_POWER + 1)
  4612. + sc->tx99_power = MAX_RATE_POWER;
  4613. +
  4614. + ath9k_hw_tx99_set_txpower(ah, sc->tx99_power);
  4615. + r = ath9k_tx99_send(sc, sc->tx99_skb, &txctl);
  4616. + if (r) {
  4617. + ath_dbg(common, XMIT, "Failed to xmit TX99 skb\n");
  4618. + return r;
  4619. + }
  4620. +
  4621. + ath_dbg(common, XMIT, "TX99 xmit started using %d ( %ddBm)\n",
  4622. + sc->tx99_power,
  4623. + sc->tx99_power / 2);
  4624. +
  4625. + /* We leave the harware awake as it will be chugging on */
  4626. +
  4627. + return 0;
  4628. +}
  4629. +
  4630. +static ssize_t read_file_tx99(struct file *file, char __user *user_buf,
  4631. + size_t count, loff_t *ppos)
  4632. +{
  4633. + struct ath_softc *sc = file->private_data;
  4634. + char buf[3];
  4635. + unsigned int len;
  4636. +
  4637. + len = sprintf(buf, "%d\n", sc->tx99_state);
  4638. + return simple_read_from_buffer(user_buf, count, ppos, buf, len);
  4639. +}
  4640. +
  4641. +static ssize_t write_file_tx99(struct file *file, const char __user *user_buf,
  4642. + size_t count, loff_t *ppos)
  4643. +{
  4644. + struct ath_softc *sc = file->private_data;
  4645. + struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  4646. + char buf[32];
  4647. + bool start;
  4648. + ssize_t len;
  4649. + int r;
  4650. +
  4651. + if (sc->nvifs > 1)
  4652. + return -EOPNOTSUPP;
  4653. +
  4654. + len = min(count, sizeof(buf) - 1);
  4655. + if (copy_from_user(buf, user_buf, len))
  4656. + return -EFAULT;
  4657. +
  4658. + if (strtobool(buf, &start))
  4659. + return -EINVAL;
  4660. +
  4661. + if (start == sc->tx99_state) {
  4662. + if (!start)
  4663. + return count;
  4664. + ath_dbg(common, XMIT, "Resetting TX99\n");
  4665. + ath9k_tx99_deinit(sc);
  4666. + }
  4667. +
  4668. + if (!start) {
  4669. + ath9k_tx99_deinit(sc);
  4670. + return count;
  4671. + }
  4672. +
  4673. + r = ath9k_tx99_init(sc);
  4674. + if (r)
  4675. + return r;
  4676. +
  4677. + return count;
  4678. +}
  4679. +
  4680. +static const struct file_operations fops_tx99 = {
  4681. + .read = read_file_tx99,
  4682. + .write = write_file_tx99,
  4683. + .open = simple_open,
  4684. + .owner = THIS_MODULE,
  4685. + .llseek = default_llseek,
  4686. +};
  4687. +
  4688. +static ssize_t read_file_tx99_power(struct file *file,
  4689. + char __user *user_buf,
  4690. + size_t count, loff_t *ppos)
  4691. +{
  4692. + struct ath_softc *sc = file->private_data;
  4693. + char buf[32];
  4694. + unsigned int len;
  4695. +
  4696. + len = sprintf(buf, "%d (%d dBm)\n",
  4697. + sc->tx99_power,
  4698. + sc->tx99_power / 2);
  4699. +
  4700. + return simple_read_from_buffer(user_buf, count, ppos, buf, len);
  4701. +}
  4702. +
  4703. +static ssize_t write_file_tx99_power(struct file *file,
  4704. + const char __user *user_buf,
  4705. + size_t count, loff_t *ppos)
  4706. +{
  4707. + struct ath_softc *sc = file->private_data;
  4708. + int r;
  4709. + u8 tx_power;
  4710. +
  4711. + r = kstrtou8_from_user(user_buf, count, 0, &tx_power);
  4712. + if (r)
  4713. + return r;
  4714. +
  4715. + if (tx_power > MAX_RATE_POWER)
  4716. + return -EINVAL;
  4717. +
  4718. + sc->tx99_power = tx_power;
  4719. +
  4720. + ath9k_ps_wakeup(sc);
  4721. + ath9k_hw_tx99_set_txpower(sc->sc_ah, sc->tx99_power);
  4722. + ath9k_ps_restore(sc);
  4723. +
  4724. + return count;
  4725. +}
  4726. +
  4727. +static const struct file_operations fops_tx99_power = {
  4728. + .read = read_file_tx99_power,
  4729. + .write = write_file_tx99_power,
  4730. + .open = simple_open,
  4731. + .owner = THIS_MODULE,
  4732. + .llseek = default_llseek,
  4733. +};
  4734. +
  4735. +void ath9k_tx99_init_debug(struct ath_softc *sc)
  4736. +{
  4737. + if (!AR_SREV_9300_20_OR_LATER(sc->sc_ah))
  4738. + return;
  4739. +
  4740. + debugfs_create_file("tx99", S_IRUSR | S_IWUSR,
  4741. + sc->debug.debugfs_phy, sc,
  4742. + &fops_tx99);
  4743. + debugfs_create_file("tx99_power", S_IRUSR | S_IWUSR,
  4744. + sc->debug.debugfs_phy, sc,
  4745. + &fops_tx99_power);
  4746. +}
  4747. --- a/drivers/net/wireless/ath/ath9k/dfs_debug.c
  4748. +++ b/drivers/net/wireless/ath/ath9k/dfs_debug.c
  4749. @@ -44,14 +44,20 @@ static ssize_t read_file_dfs(struct file
  4750. if (buf == NULL)
  4751. return -ENOMEM;
  4752. - if (sc->dfs_detector)
  4753. - dfs_pool_stats = sc->dfs_detector->get_stats(sc->dfs_detector);
  4754. -
  4755. len += scnprintf(buf + len, size - len, "DFS support for "
  4756. "macVersion = 0x%x, macRev = 0x%x: %s\n",
  4757. hw_ver->macVersion, hw_ver->macRev,
  4758. (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_DFS) ?
  4759. "enabled" : "disabled");
  4760. +
  4761. + if (!sc->dfs_detector) {
  4762. + len += scnprintf(buf + len, size - len,
  4763. + "DFS detector not enabled\n");
  4764. + goto exit;
  4765. + }
  4766. +
  4767. + dfs_pool_stats = sc->dfs_detector->get_stats(sc->dfs_detector);
  4768. +
  4769. len += scnprintf(buf + len, size - len, "Pulse detector statistics:\n");
  4770. ATH9K_DFS_STAT("pulse events reported ", pulses_total);
  4771. ATH9K_DFS_STAT("invalid pulse events ", pulses_no_dfs);
  4772. @@ -76,6 +82,7 @@ static ssize_t read_file_dfs(struct file
  4773. ATH9K_DFS_POOL_STAT("Seqs. alloc error ", pseq_alloc_error);
  4774. ATH9K_DFS_POOL_STAT("Seqs. in use ", pseq_used);
  4775. +exit:
  4776. if (len > size)
  4777. len = size;
  4778. --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
  4779. +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
  4780. @@ -641,11 +641,12 @@ static void ar9003_hw_override_ini(struc
  4781. else
  4782. ah->enabled_cals &= ~TX_IQ_CAL;
  4783. - if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
  4784. - ah->enabled_cals |= TX_CL_CAL;
  4785. - else
  4786. - ah->enabled_cals &= ~TX_CL_CAL;
  4787. }
  4788. +
  4789. + if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
  4790. + ah->enabled_cals |= TX_CL_CAL;
  4791. + else
  4792. + ah->enabled_cals &= ~TX_CL_CAL;
  4793. }
  4794. static void ar9003_hw_prog_ini(struct ath_hw *ah,
  4795. @@ -701,6 +702,54 @@ static int ar9550_hw_get_modes_txgain_in
  4796. return ret;
  4797. }
  4798. +static void ar9003_doubler_fix(struct ath_hw *ah)
  4799. +{
  4800. + if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
  4801. + REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
  4802. + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
  4803. + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
  4804. + REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
  4805. + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
  4806. + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
  4807. + REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
  4808. + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
  4809. + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
  4810. +
  4811. + udelay(200);
  4812. +
  4813. + REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
  4814. + AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
  4815. + REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
  4816. + AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
  4817. + REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
  4818. + AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
  4819. +
  4820. + udelay(1);
  4821. +
  4822. + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
  4823. + AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
  4824. + REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
  4825. + AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
  4826. + REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
  4827. + AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
  4828. +
  4829. + udelay(200);
  4830. +
  4831. + REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
  4832. + AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
  4833. +
  4834. + REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
  4835. + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
  4836. + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
  4837. + REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
  4838. + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
  4839. + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
  4840. + REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
  4841. + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
  4842. + 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
  4843. + }
  4844. +}
  4845. +
  4846. static int ar9003_hw_process_ini(struct ath_hw *ah,
  4847. struct ath9k_channel *chan)
  4848. {
  4849. @@ -726,6 +775,8 @@ static int ar9003_hw_process_ini(struct
  4850. modesIndex);
  4851. }
  4852. + ar9003_doubler_fix(ah);
  4853. +
  4854. /*
  4855. * RXGAIN initvals.
  4856. */
  4857. --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
  4858. +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
  4859. @@ -656,13 +656,24 @@
  4860. #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00000001 : 0x00000002)
  4861. #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0 : 1)
  4862. #define AR_PHY_65NM_CH0_SYNTH7 0x16098
  4863. +#define AR_PHY_65NM_CH0_SYNTH12 0x160ac
  4864. #define AR_PHY_65NM_CH0_BIAS1 0x160c0
  4865. #define AR_PHY_65NM_CH0_BIAS2 0x160c4
  4866. #define AR_PHY_65NM_CH0_BIAS4 0x160cc
  4867. +#define AR_PHY_65NM_CH0_RXTX2 0x16104
  4868. +#define AR_PHY_65NM_CH1_RXTX2 0x16504
  4869. +#define AR_PHY_65NM_CH2_RXTX2 0x16904
  4870. #define AR_PHY_65NM_CH0_RXTX4 0x1610c
  4871. #define AR_PHY_65NM_CH1_RXTX4 0x1650c
  4872. #define AR_PHY_65NM_CH2_RXTX4 0x1690c
  4873. +#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3 0x00780000
  4874. +#define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3_S 19
  4875. +#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK 0x00000004
  4876. +#define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S 2
  4877. +#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK 0x00000008
  4878. +#define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S 3
  4879. +
  4880. #define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
  4881. (((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x1628c : 0x16280)))
  4882. #define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300)
  4883. --- a/drivers/net/wireless/rt2x00/rt2x00dev.c
  4884. +++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
  4885. @@ -181,6 +181,7 @@ static void rt2x00lib_autowakeup(struct
  4886. static void rt2x00lib_bc_buffer_iter(void *data, u8 *mac,
  4887. struct ieee80211_vif *vif)
  4888. {
  4889. + struct ieee80211_tx_control control = {};
  4890. struct rt2x00_dev *rt2x00dev = data;
  4891. struct sk_buff *skb;
  4892. @@ -195,7 +196,7 @@ static void rt2x00lib_bc_buffer_iter(voi
  4893. */
  4894. skb = ieee80211_get_buffered_bc(rt2x00dev->hw, vif);
  4895. while (skb) {
  4896. - rt2x00mac_tx(rt2x00dev->hw, NULL, skb);
  4897. + rt2x00mac_tx(rt2x00dev->hw, &control, skb);
  4898. skb = ieee80211_get_buffered_bc(rt2x00dev->hw, vif);
  4899. }
  4900. }
  4901. --- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
  4902. +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
  4903. @@ -1040,14 +1040,14 @@ static void ar9003_hw_cl_cal_post_proc(s
  4904. }
  4905. }
  4906. -static bool ar9003_hw_init_cal(struct ath_hw *ah,
  4907. - struct ath9k_channel *chan)
  4908. +static bool ar9003_hw_init_cal_pcoem(struct ath_hw *ah,
  4909. + struct ath9k_channel *chan)
  4910. {
  4911. struct ath_common *common = ath9k_hw_common(ah);
  4912. struct ath9k_hw_cal_data *caldata = ah->caldata;
  4913. bool txiqcal_done = false;
  4914. bool is_reusable = true, status = true;
  4915. - bool run_rtt_cal = false, run_agc_cal, sep_iq_cal = false;
  4916. + bool run_rtt_cal = false, run_agc_cal;
  4917. bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
  4918. u32 rx_delay = 0;
  4919. u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
  4920. @@ -1119,22 +1119,12 @@ static bool ar9003_hw_init_cal(struct at
  4921. REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
  4922. AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
  4923. txiqcal_done = run_agc_cal = true;
  4924. - } else if (caldata && !test_bit(TXIQCAL_DONE, &caldata->cal_flags)) {
  4925. - run_agc_cal = true;
  4926. - sep_iq_cal = true;
  4927. }
  4928. skip_tx_iqcal:
  4929. if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal)
  4930. ar9003_mci_init_cal_req(ah, &is_reusable);
  4931. - if (sep_iq_cal) {
  4932. - txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
  4933. - REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
  4934. - udelay(5);
  4935. - REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
  4936. - }
  4937. -
  4938. if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
  4939. rx_delay = REG_READ(ah, AR_PHY_RX_DELAY);
  4940. /* Disable BB_active */
  4941. @@ -1228,13 +1218,109 @@ skip_tx_iqcal:
  4942. return true;
  4943. }
  4944. +static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
  4945. + struct ath9k_channel *chan)
  4946. +{
  4947. + struct ath_common *common = ath9k_hw_common(ah);
  4948. + struct ath9k_hw_cal_data *caldata = ah->caldata;
  4949. + bool txiqcal_done = false;
  4950. + bool is_reusable = true, status = true;
  4951. + bool run_agc_cal = false, sep_iq_cal = false;
  4952. +
  4953. + /* Use chip chainmask only for calibration */
  4954. + ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
  4955. +
  4956. + if (ah->enabled_cals & TX_CL_CAL) {
  4957. + REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
  4958. + run_agc_cal = true;
  4959. + }
  4960. +
  4961. + if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
  4962. + goto skip_tx_iqcal;
  4963. +
  4964. + /* Do Tx IQ Calibration */
  4965. + REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
  4966. + AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
  4967. + DELPT);
  4968. +
  4969. + /*
  4970. + * For AR9485 or later chips, TxIQ cal runs as part of
  4971. + * AGC calibration. Specifically, AR9550 in SoC chips.
  4972. + */
  4973. + if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
  4974. + txiqcal_done = true;
  4975. + run_agc_cal = true;
  4976. + } else {
  4977. + sep_iq_cal = true;
  4978. + run_agc_cal = true;
  4979. + }
  4980. +
  4981. + /*
  4982. + * In the SoC family, this will run for AR9300, AR9331 and AR9340.
  4983. + */
  4984. + if (sep_iq_cal) {
  4985. + txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
  4986. + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
  4987. + udelay(5);
  4988. + REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
  4989. + }
  4990. +
  4991. +skip_tx_iqcal:
  4992. + if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
  4993. + /* Calibrate the AGC */
  4994. + REG_WRITE(ah, AR_PHY_AGC_CONTROL,
  4995. + REG_READ(ah, AR_PHY_AGC_CONTROL) |
  4996. + AR_PHY_AGC_CONTROL_CAL);
  4997. +
  4998. + /* Poll for offset calibration complete */
  4999. + status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
  5000. + AR_PHY_AGC_CONTROL_CAL,
  5001. + 0, AH_WAIT_TIMEOUT);
  5002. + }
  5003. +
  5004. + if (!status) {
  5005. + ath_dbg(common, CALIBRATE,
  5006. + "offset calibration failed to complete in %d ms; noisy environment?\n",
  5007. + AH_WAIT_TIMEOUT / 1000);
  5008. + return false;
  5009. + }
  5010. +
  5011. + if (txiqcal_done)
  5012. + ar9003_hw_tx_iq_cal_post_proc(ah, is_reusable);
  5013. +
  5014. + /* Revert chainmask to runtime parameters */
  5015. + ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
  5016. +
  5017. + /* Initialize list pointers */
  5018. + ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
  5019. +
  5020. + INIT_CAL(&ah->iq_caldata);
  5021. + INSERT_CAL(ah, &ah->iq_caldata);
  5022. + ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n");
  5023. +
  5024. + /* Initialize current pointer to first element in list */
  5025. + ah->cal_list_curr = ah->cal_list;
  5026. +
  5027. + if (ah->cal_list_curr)
  5028. + ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
  5029. +
  5030. + if (caldata)
  5031. + caldata->CalValid = 0;
  5032. +
  5033. + return true;
  5034. +}
  5035. +
  5036. void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
  5037. {
  5038. struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  5039. struct ath_hw_ops *ops = ath9k_hw_ops(ah);
  5040. + if (AR_SREV_9485(ah) || AR_SREV_9462(ah) || AR_SREV_9565(ah))
  5041. + priv_ops->init_cal = ar9003_hw_init_cal_pcoem;
  5042. + else
  5043. + priv_ops->init_cal = ar9003_hw_init_cal_soc;
  5044. +
  5045. priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
  5046. - priv_ops->init_cal = ar9003_hw_init_cal;
  5047. priv_ops->setup_calibration = ar9003_hw_setup_calibration;
  5048. ops->calibrate = ar9003_hw_calibrate;
  5049. --- a/drivers/net/wireless/ath/ath9k/common.c
  5050. +++ b/drivers/net/wireless/ath/ath9k/common.c
  5051. @@ -98,10 +98,8 @@ struct ath9k_channel *ath9k_cmn_get_chan
  5052. {
  5053. struct ieee80211_channel *curchan = chandef->chan;
  5054. struct ath9k_channel *channel;
  5055. - u8 chan_idx;
  5056. - chan_idx = curchan->hw_value;
  5057. - channel = &ah->channels[chan_idx];
  5058. + channel = &ah->channels[curchan->hw_value];
  5059. ath9k_cmn_update_ichannel(channel, chandef);
  5060. return channel;
  5061. --- a/net/mac80211/rc80211_minstrel_ht.c
  5062. +++ b/net/mac80211/rc80211_minstrel_ht.c
  5063. @@ -226,7 +226,7 @@ minstrel_ht_calc_tp(struct minstrel_ht_s
  5064. nsecs = 1000 * mi->overhead / MINSTREL_TRUNC(mi->avg_ampdu_len);
  5065. nsecs += minstrel_mcs_groups[group].duration[rate];
  5066. - tp = 1000000 * ((mr->probability * 1000) / nsecs);
  5067. + tp = 1000000 * ((prob * 1000) / nsecs);
  5068. mr->cur_tp = MINSTREL_TRUNC(tp);
  5069. }
  5070. --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
  5071. +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
  5072. @@ -3984,18 +3984,20 @@ static void ar9003_hw_quick_drop_apply(s
  5073. int quick_drop;
  5074. s32 t[3], f[3] = {5180, 5500, 5785};
  5075. - if (!(pBase->miscConfiguration & BIT(1)))
  5076. + if (!(pBase->miscConfiguration & BIT(4)))
  5077. return;
  5078. - if (freq < 4000)
  5079. - quick_drop = eep->modalHeader2G.quick_drop;
  5080. - else {
  5081. - t[0] = eep->base_ext1.quick_drop_low;
  5082. - t[1] = eep->modalHeader5G.quick_drop;
  5083. - t[2] = eep->base_ext1.quick_drop_high;
  5084. - quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
  5085. + if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9340(ah)) {
  5086. + if (freq < 4000) {
  5087. + quick_drop = eep->modalHeader2G.quick_drop;
  5088. + } else {
  5089. + t[0] = eep->base_ext1.quick_drop_low;
  5090. + t[1] = eep->modalHeader5G.quick_drop;
  5091. + t[2] = eep->base_ext1.quick_drop_high;
  5092. + quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
  5093. + }
  5094. + REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
  5095. }
  5096. - REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
  5097. }
  5098. static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
  5099. @@ -4035,7 +4037,7 @@ static void ar9003_hw_xlna_bias_strength
  5100. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  5101. u8 bias;
  5102. - if (!(eep->baseEepHeader.featureEnable & 0x40))
  5103. + if (!(eep->baseEepHeader.miscConfiguration & 0x40))
  5104. return;
  5105. if (!AR_SREV_9300(ah))
  5106. --- a/net/mac80211/ieee80211_i.h
  5107. +++ b/net/mac80211/ieee80211_i.h
  5108. @@ -735,6 +735,7 @@ struct ieee80211_sub_if_data {
  5109. int csa_counter_offset_beacon;
  5110. int csa_counter_offset_presp;
  5111. bool csa_radar_required;
  5112. + struct cfg80211_chan_def csa_chandef;
  5113. /* used to reconfigure hardware SM PS */
  5114. struct work_struct recalc_smps;
  5115. @@ -811,6 +812,9 @@ static inline void sdata_unlock(struct i
  5116. __release(&sdata->wdev.mtx);
  5117. }
  5118. +#define sdata_dereference(p, sdata) \
  5119. + rcu_dereference_protected(p, lockdep_is_held(&sdata->wdev.mtx))
  5120. +
  5121. static inline void
  5122. sdata_assert_lock(struct ieee80211_sub_if_data *sdata)
  5123. {
  5124. @@ -1098,7 +1102,6 @@ struct ieee80211_local {
  5125. enum mac80211_scan_state next_scan_state;
  5126. struct delayed_work scan_work;
  5127. struct ieee80211_sub_if_data __rcu *scan_sdata;
  5128. - struct cfg80211_chan_def csa_chandef;
  5129. /* For backward compatibility only -- do not use */
  5130. struct cfg80211_chan_def _oper_chandef;
  5131. @@ -1236,6 +1239,7 @@ struct ieee80211_csa_ie {
  5132. u8 mode;
  5133. u8 count;
  5134. u8 ttl;
  5135. + u16 pre_value;
  5136. };
  5137. /* Parsed Information Elements */
  5138. @@ -1738,7 +1742,6 @@ ieee80211_vif_change_bandwidth(struct ie
  5139. /* NOTE: only use ieee80211_vif_change_channel() for channel switch */
  5140. int __must_check
  5141. ieee80211_vif_change_channel(struct ieee80211_sub_if_data *sdata,
  5142. - const struct cfg80211_chan_def *chandef,
  5143. u32 *changed);
  5144. void ieee80211_vif_release_channel(struct ieee80211_sub_if_data *sdata);
  5145. void ieee80211_vif_vlan_copy_chanctx(struct ieee80211_sub_if_data *sdata);
  5146. --- a/net/mac80211/chan.c
  5147. +++ b/net/mac80211/chan.c
  5148. @@ -411,12 +411,12 @@ int ieee80211_vif_use_channel(struct iee
  5149. }
  5150. int ieee80211_vif_change_channel(struct ieee80211_sub_if_data *sdata,
  5151. - const struct cfg80211_chan_def *chandef,
  5152. u32 *changed)
  5153. {
  5154. struct ieee80211_local *local = sdata->local;
  5155. struct ieee80211_chanctx_conf *conf;
  5156. struct ieee80211_chanctx *ctx;
  5157. + const struct cfg80211_chan_def *chandef = &sdata->csa_chandef;
  5158. int ret;
  5159. u32 chanctx_changed = 0;
  5160. --- a/net/mac80211/ibss.c
  5161. +++ b/net/mac80211/ibss.c
  5162. @@ -550,12 +550,12 @@ int ieee80211_ibss_finish_csa(struct iee
  5163. capability);
  5164. /* XXX: should not really modify cfg80211 data */
  5165. if (cbss) {
  5166. - cbss->channel = sdata->local->csa_chandef.chan;
  5167. + cbss->channel = sdata->csa_chandef.chan;
  5168. cfg80211_put_bss(sdata->local->hw.wiphy, cbss);
  5169. }
  5170. }
  5171. - ifibss->chandef = sdata->local->csa_chandef;
  5172. + ifibss->chandef = sdata->csa_chandef;
  5173. /* generate the beacon */
  5174. err = ieee80211_ibss_csa_beacon(sdata, NULL);
  5175. @@ -922,7 +922,7 @@ ieee80211_ibss_process_chanswitch(struct
  5176. IEEE80211_MAX_QUEUE_MAP,
  5177. IEEE80211_QUEUE_STOP_REASON_CSA);
  5178. - sdata->local->csa_chandef = params.chandef;
  5179. + sdata->csa_chandef = params.chandef;
  5180. sdata->vif.csa_active = true;
  5181. ieee80211_bss_info_change_notify(sdata, err);
  5182. --- a/net/mac80211/mesh.c
  5183. +++ b/net/mac80211/mesh.c
  5184. @@ -943,14 +943,19 @@ ieee80211_mesh_process_chnswitch(struct
  5185. params.chandef.chan->center_freq);
  5186. params.block_tx = csa_ie.mode & WLAN_EID_CHAN_SWITCH_PARAM_TX_RESTRICT;
  5187. - if (beacon)
  5188. + if (beacon) {
  5189. ifmsh->chsw_ttl = csa_ie.ttl - 1;
  5190. - else
  5191. - ifmsh->chsw_ttl = 0;
  5192. + if (ifmsh->pre_value >= csa_ie.pre_value)
  5193. + return false;
  5194. + ifmsh->pre_value = csa_ie.pre_value;
  5195. + }
  5196. - if (ifmsh->chsw_ttl > 0)
  5197. + if (ifmsh->chsw_ttl < ifmsh->mshcfg.dot11MeshTTL) {
  5198. if (ieee80211_mesh_csa_beacon(sdata, &params, false) < 0)
  5199. return false;
  5200. + } else {
  5201. + return false;
  5202. + }
  5203. sdata->csa_radar_required = params.radar_required;
  5204. @@ -959,7 +964,7 @@ ieee80211_mesh_process_chnswitch(struct
  5205. IEEE80211_MAX_QUEUE_MAP,
  5206. IEEE80211_QUEUE_STOP_REASON_CSA);
  5207. - sdata->local->csa_chandef = params.chandef;
  5208. + sdata->csa_chandef = params.chandef;
  5209. sdata->vif.csa_active = true;
  5210. ieee80211_bss_info_change_notify(sdata, err);
  5211. @@ -1163,7 +1168,6 @@ static int mesh_fwd_csa_frame(struct iee
  5212. offset_ttl = (len < 42) ? 7 : 10;
  5213. *(pos + offset_ttl) -= 1;
  5214. *(pos + offset_ttl + 1) &= ~WLAN_EID_CHAN_SWITCH_PARAM_INITIATOR;
  5215. - sdata->u.mesh.chsw_ttl = *(pos + offset_ttl);
  5216. memcpy(mgmt_fwd, mgmt, len);
  5217. eth_broadcast_addr(mgmt_fwd->da);
  5218. @@ -1182,7 +1186,7 @@ static void mesh_rx_csa_frame(struct iee
  5219. u16 pre_value;
  5220. bool fwd_csa = true;
  5221. size_t baselen;
  5222. - u8 *pos, ttl;
  5223. + u8 *pos;
  5224. if (mgmt->u.action.u.measurement.action_code !=
  5225. WLAN_ACTION_SPCT_CHL_SWITCH)
  5226. @@ -1193,8 +1197,8 @@ static void mesh_rx_csa_frame(struct iee
  5227. u.action.u.chan_switch.variable);
  5228. ieee802_11_parse_elems(pos, len - baselen, false, &elems);
  5229. - ttl = elems.mesh_chansw_params_ie->mesh_ttl;
  5230. - if (!--ttl)
  5231. + ifmsh->chsw_ttl = elems.mesh_chansw_params_ie->mesh_ttl;
  5232. + if (!--ifmsh->chsw_ttl)
  5233. fwd_csa = false;
  5234. pre_value = le16_to_cpu(elems.mesh_chansw_params_ie->mesh_pre_value);
  5235. --- a/net/mac80211/spectmgmt.c
  5236. +++ b/net/mac80211/spectmgmt.c
  5237. @@ -78,6 +78,8 @@ int ieee80211_parse_ch_switch_ie(struct
  5238. if (elems->mesh_chansw_params_ie) {
  5239. csa_ie->ttl = elems->mesh_chansw_params_ie->mesh_ttl;
  5240. csa_ie->mode = elems->mesh_chansw_params_ie->mesh_flags;
  5241. + csa_ie->pre_value = le16_to_cpu(
  5242. + elems->mesh_chansw_params_ie->mesh_pre_value);
  5243. }
  5244. new_freq = ieee80211_channel_to_frequency(new_chan_no, new_band);
  5245. --- a/drivers/net/wireless/ath/ath6kl/cfg80211.c
  5246. +++ b/drivers/net/wireless/ath/ath6kl/cfg80211.c
  5247. @@ -1109,7 +1109,9 @@ void ath6kl_cfg80211_ch_switch_notify(st
  5248. (mode == WMI_11G_HT20) ?
  5249. NL80211_CHAN_HT20 : NL80211_CHAN_NO_HT);
  5250. + mutex_lock(vif->wdev->mtx);
  5251. cfg80211_ch_switch_notify(vif->ndev, &chandef);
  5252. + mutex_unlock(vif->wdev->mtx);
  5253. }
  5254. static int ath6kl_cfg80211_add_key(struct wiphy *wiphy, struct net_device *ndev,
  5255. --- a/drivers/net/wireless/ath/ath9k/ar9462_2p1_initvals.h
  5256. +++ b/drivers/net/wireless/ath/ath9k/ar9462_2p1_initvals.h
  5257. @@ -20,6 +20,44 @@
  5258. /* AR9462 2.1 */
  5259. +#define ar9462_2p1_mac_postamble ar9462_2p0_mac_postamble
  5260. +
  5261. +#define ar9462_2p1_baseband_core ar9462_2p0_baseband_core
  5262. +
  5263. +#define ar9462_2p1_radio_core ar9462_2p0_radio_core
  5264. +
  5265. +#define ar9462_2p1_radio_postamble ar9462_2p0_radio_postamble
  5266. +
  5267. +#define ar9462_2p1_soc_postamble ar9462_2p0_soc_postamble
  5268. +
  5269. +#define ar9462_2p1_radio_postamble_sys2ant ar9462_2p0_radio_postamble_sys2ant
  5270. +
  5271. +#define ar9462_2p1_common_rx_gain ar9462_2p0_common_rx_gain
  5272. +
  5273. +#define ar9462_2p1_common_mixed_rx_gain ar9462_2p0_common_mixed_rx_gain
  5274. +
  5275. +#define ar9462_2p1_common_5g_xlna_only_rxgain ar9462_2p0_common_5g_xlna_only_rxgain
  5276. +
  5277. +#define ar9462_2p1_baseband_core_mix_rxgain ar9462_2p0_baseband_core_mix_rxgain
  5278. +
  5279. +#define ar9462_2p1_baseband_postamble_mix_rxgain ar9462_2p0_baseband_postamble_mix_rxgain
  5280. +
  5281. +#define ar9462_2p1_baseband_postamble_5g_xlna ar9462_2p0_baseband_postamble_5g_xlna
  5282. +
  5283. +#define ar9462_2p1_common_wo_xlna_rx_gain ar9462_2p0_common_wo_xlna_rx_gain
  5284. +
  5285. +#define ar9462_2p1_modes_low_ob_db_tx_gain ar9462_2p0_modes_low_ob_db_tx_gain
  5286. +
  5287. +#define ar9462_2p1_modes_high_ob_db_tx_gain ar9462_2p0_modes_high_ob_db_tx_gain
  5288. +
  5289. +#define ar9462_2p1_modes_mix_ob_db_tx_gain ar9462_2p0_modes_mix_ob_db_tx_gain
  5290. +
  5291. +#define ar9462_2p1_modes_fast_clock ar9462_2p0_modes_fast_clock
  5292. +
  5293. +#define ar9462_2p1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
  5294. +
  5295. +#define ar9462_2p1_pciephy_clkreq_disable_L1 ar9462_2p0_pciephy_clkreq_disable_L1
  5296. +
  5297. static const u32 ar9462_2p1_mac_core[][2] = {
  5298. /* Addr allmodes */
  5299. {0x00000008, 0x00000000},
  5300. @@ -183,168 +221,6 @@ static const u32 ar9462_2p1_mac_core[][2
  5301. {0x000083d0, 0x000301ff},
  5302. };
  5303. -static const u32 ar9462_2p1_mac_postamble[][5] = {
  5304. - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  5305. - {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
  5306. - {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
  5307. - {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
  5308. - {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
  5309. - {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
  5310. - {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
  5311. - {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
  5312. - {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
  5313. -};
  5314. -
  5315. -static const u32 ar9462_2p1_baseband_core[][2] = {
  5316. - /* Addr allmodes */
  5317. - {0x00009800, 0xafe68e30},
  5318. - {0x00009804, 0xfd14e000},
  5319. - {0x00009808, 0x9c0a9f6b},
  5320. - {0x0000980c, 0x04900000},
  5321. - {0x00009814, 0x9280c00a},
  5322. - {0x00009818, 0x00000000},
  5323. - {0x0000981c, 0x00020028},
  5324. - {0x00009834, 0x6400a290},
  5325. - {0x00009838, 0x0108ecff},
  5326. - {0x0000983c, 0x0d000600},
  5327. - {0x00009880, 0x201fff00},
  5328. - {0x00009884, 0x00001042},
  5329. - {0x000098a4, 0x00200400},
  5330. - {0x000098b0, 0x32440bbe},
  5331. - {0x000098d0, 0x004b6a8e},
  5332. - {0x000098d4, 0x00000820},
  5333. - {0x000098dc, 0x00000000},
  5334. - {0x000098e4, 0x01ffffff},
  5335. - {0x000098e8, 0x01ffffff},
  5336. - {0x000098ec, 0x01ffffff},
  5337. - {0x000098f0, 0x00000000},
  5338. - {0x000098f4, 0x00000000},
  5339. - {0x00009bf0, 0x80000000},
  5340. - {0x00009c04, 0xff55ff55},
  5341. - {0x00009c08, 0x0320ff55},
  5342. - {0x00009c0c, 0x00000000},
  5343. - {0x00009c10, 0x00000000},
  5344. - {0x00009c14, 0x00046384},
  5345. - {0x00009c18, 0x05b6b440},
  5346. - {0x00009c1c, 0x00b6b440},
  5347. - {0x00009d00, 0xc080a333},
  5348. - {0x00009d04, 0x40206c10},
  5349. - {0x00009d08, 0x009c4060},
  5350. - {0x00009d0c, 0x9883800a},
  5351. - {0x00009d10, 0x01834061},
  5352. - {0x00009d14, 0x00c0040b},
  5353. - {0x00009d18, 0x00000000},
  5354. - {0x00009e08, 0x0038230c},
  5355. - {0x00009e24, 0x990bb515},
  5356. - {0x00009e28, 0x0c6f0000},
  5357. - {0x00009e30, 0x06336f77},
  5358. - {0x00009e34, 0x6af6532f},
  5359. - {0x00009e38, 0x0cc80c00},
  5360. - {0x00009e40, 0x15262820},
  5361. - {0x00009e4c, 0x00001004},
  5362. - {0x00009e50, 0x00ff03f1},
  5363. - {0x00009e54, 0xe4c555c2},
  5364. - {0x00009e58, 0xfd857722},
  5365. - {0x00009e5c, 0xe9198724},
  5366. - {0x00009fc0, 0x803e4788},
  5367. - {0x00009fc4, 0x0001efb5},
  5368. - {0x00009fcc, 0x40000014},
  5369. - {0x00009fd0, 0x0a193b93},
  5370. - {0x0000a20c, 0x00000000},
  5371. - {0x0000a220, 0x00000000},
  5372. - {0x0000a224, 0x00000000},
  5373. - {0x0000a228, 0x10002310},
  5374. - {0x0000a23c, 0x00000000},
  5375. - {0x0000a244, 0x0c000000},
  5376. - {0x0000a2a0, 0x00000001},
  5377. - {0x0000a2c0, 0x00000001},
  5378. - {0x0000a2c8, 0x00000000},
  5379. - {0x0000a2cc, 0x18c43433},
  5380. - {0x0000a2d4, 0x00000000},
  5381. - {0x0000a2ec, 0x00000000},
  5382. - {0x0000a2f0, 0x00000000},
  5383. - {0x0000a2f4, 0x00000000},
  5384. - {0x0000a2f8, 0x00000000},
  5385. - {0x0000a344, 0x00000000},
  5386. - {0x0000a34c, 0x00000000},
  5387. - {0x0000a350, 0x0000a000},
  5388. - {0x0000a364, 0x00000000},
  5389. - {0x0000a370, 0x00000000},
  5390. - {0x0000a390, 0x00000001},
  5391. - {0x0000a394, 0x00000444},
  5392. - {0x0000a398, 0x001f0e0f},
  5393. - {0x0000a39c, 0x0075393f},
  5394. - {0x0000a3a0, 0xb79f6427},
  5395. - {0x0000a3c0, 0x20202020},
  5396. - {0x0000a3c4, 0x22222220},
  5397. - {0x0000a3c8, 0x20200020},
  5398. - {0x0000a3cc, 0x20202020},
  5399. - {0x0000a3d0, 0x20202020},
  5400. - {0x0000a3d4, 0x20202020},
  5401. - {0x0000a3d8, 0x20202020},
  5402. - {0x0000a3dc, 0x20202020},
  5403. - {0x0000a3e0, 0x20202020},
  5404. - {0x0000a3e4, 0x20202020},
  5405. - {0x0000a3e8, 0x20202020},
  5406. - {0x0000a3ec, 0x20202020},
  5407. - {0x0000a3f0, 0x00000000},
  5408. - {0x0000a3f4, 0x00000006},
  5409. - {0x0000a3f8, 0x0c9bd380},
  5410. - {0x0000a3fc, 0x000f0f01},
  5411. - {0x0000a400, 0x8fa91f01},
  5412. - {0x0000a404, 0x00000000},
  5413. - {0x0000a408, 0x0e79e5c6},
  5414. - {0x0000a40c, 0x00820820},
  5415. - {0x0000a414, 0x1ce739ce},
  5416. - {0x0000a418, 0x2d001dce},
  5417. - {0x0000a434, 0x00000000},
  5418. - {0x0000a438, 0x00001801},
  5419. - {0x0000a43c, 0x00100000},
  5420. - {0x0000a444, 0x00000000},
  5421. - {0x0000a448, 0x05000080},
  5422. - {0x0000a44c, 0x00000001},
  5423. - {0x0000a450, 0x00010000},
  5424. - {0x0000a454, 0x07000000},
  5425. - {0x0000a644, 0xbfad9d74},
  5426. - {0x0000a648, 0x0048060a},
  5427. - {0x0000a64c, 0x00002037},
  5428. - {0x0000a670, 0x03020100},
  5429. - {0x0000a674, 0x09080504},
  5430. - {0x0000a678, 0x0d0c0b0a},
  5431. - {0x0000a67c, 0x13121110},
  5432. - {0x0000a680, 0x31301514},
  5433. - {0x0000a684, 0x35343332},
  5434. - {0x0000a688, 0x00000036},
  5435. - {0x0000a690, 0x00000838},
  5436. - {0x0000a6b0, 0x0000000a},
  5437. - {0x0000a6b4, 0x00512c01},
  5438. - {0x0000a7c0, 0x00000000},
  5439. - {0x0000a7c4, 0xfffffffc},
  5440. - {0x0000a7c8, 0x00000000},
  5441. - {0x0000a7cc, 0x00000000},
  5442. - {0x0000a7d0, 0x00000000},
  5443. - {0x0000a7d4, 0x00000004},
  5444. - {0x0000a7dc, 0x00000000},
  5445. - {0x0000a7f0, 0x80000000},
  5446. - {0x0000a8d0, 0x004b6a8e},
  5447. - {0x0000a8d4, 0x00000820},
  5448. - {0x0000a8dc, 0x00000000},
  5449. - {0x0000a8f0, 0x00000000},
  5450. - {0x0000a8f4, 0x00000000},
  5451. - {0x0000abf0, 0x80000000},
  5452. - {0x0000b2d0, 0x00000080},
  5453. - {0x0000b2d4, 0x00000000},
  5454. - {0x0000b2ec, 0x00000000},
  5455. - {0x0000b2f0, 0x00000000},
  5456. - {0x0000b2f4, 0x00000000},
  5457. - {0x0000b2f8, 0x00000000},
  5458. - {0x0000b408, 0x0e79e5c0},
  5459. - {0x0000b40c, 0x00820820},
  5460. - {0x0000b420, 0x00000000},
  5461. - {0x0000b6b0, 0x0000000a},
  5462. - {0x0000b6b4, 0x00000001},
  5463. -};
  5464. -
  5465. static const u32 ar9462_2p1_baseband_postamble[][5] = {
  5466. /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  5467. {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
  5468. @@ -361,7 +237,7 @@ static const u32 ar9462_2p1_baseband_pos
  5469. {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32365a5e},
  5470. {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  5471. {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
  5472. - {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
  5473. + {0x00009e20, 0x000003a5, 0x000003a5, 0x000003a5, 0x000003a5},
  5474. {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
  5475. {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
  5476. {0x00009e44, 0x62321e27, 0x62321e27, 0xfe291e27, 0xfe291e27},
  5477. @@ -400,1375 +276,16 @@ static const u32 ar9462_2p1_baseband_pos
  5478. {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x00100000},
  5479. {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  5480. {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
  5481. - {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
  5482. + {0x0000ae20, 0x000001a6, 0x000001a6, 0x000001aa, 0x000001aa},
  5483. {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
  5484. };
  5485. -static const u32 ar9462_2p1_radio_core[][2] = {
  5486. - /* Addr allmodes */
  5487. - {0x00016000, 0x36db6db6},
  5488. - {0x00016004, 0x6db6db40},
  5489. - {0x00016008, 0x73f00000},
  5490. - {0x0001600c, 0x00000000},
  5491. - {0x00016010, 0x6d820001},
  5492. - {0x00016040, 0x7f80fff8},
  5493. - {0x0001604c, 0x2699e04f},
  5494. - {0x00016050, 0x6db6db6c},
  5495. - {0x00016058, 0x6c200000},
  5496. - {0x00016080, 0x000c0000},
  5497. - {0x00016084, 0x9a68048c},
  5498. - {0x00016088, 0x54214514},
  5499. - {0x0001608c, 0x1203040b},
  5500. - {0x00016090, 0x24926490},
  5501. - {0x00016098, 0xd2888888},
  5502. - {0x000160a0, 0x0a108ffe},
  5503. - {0x000160a4, 0x812fc491},
  5504. - {0x000160a8, 0x423c8000},
  5505. - {0x000160b4, 0x92000000},
  5506. - {0x000160b8, 0x0285dddc},
  5507. - {0x000160bc, 0x02908888},
  5508. - {0x000160c0, 0x00adb6d0},
  5509. - {0x000160c4, 0x6db6db60},
  5510. - {0x000160c8, 0x6db6db6c},
  5511. - {0x000160cc, 0x0de6c1b0},
  5512. - {0x00016100, 0x3fffbe04},
  5513. - {0x00016104, 0xfff80000},
  5514. - {0x00016108, 0x00200400},
  5515. - {0x00016110, 0x00000000},
  5516. - {0x00016144, 0x02084080},
  5517. - {0x00016148, 0x000080c0},
  5518. - {0x00016280, 0x050a0001},
  5519. - {0x00016284, 0x3d841418},
  5520. - {0x00016288, 0x00000000},
  5521. - {0x0001628c, 0xe3000000},
  5522. - {0x00016290, 0xa1005080},
  5523. - {0x00016294, 0x00000020},
  5524. - {0x00016298, 0x54a82900},
  5525. - {0x00016340, 0x121e4276},
  5526. - {0x00016344, 0x00300000},
  5527. - {0x00016400, 0x36db6db6},
  5528. - {0x00016404, 0x6db6db40},
  5529. - {0x00016408, 0x73f00000},
  5530. - {0x0001640c, 0x00000000},
  5531. - {0x00016410, 0x6c800001},
  5532. - {0x00016440, 0x7f80fff8},
  5533. - {0x0001644c, 0x4699e04f},
  5534. - {0x00016450, 0x6db6db6c},
  5535. - {0x00016500, 0x3fffbe04},
  5536. - {0x00016504, 0xfff80000},
  5537. - {0x00016508, 0x00200400},
  5538. - {0x00016510, 0x00000000},
  5539. - {0x00016544, 0x02084080},
  5540. - {0x00016548, 0x000080c0},
  5541. -};
  5542. -
  5543. -static const u32 ar9462_2p1_radio_postamble[][5] = {
  5544. - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  5545. - {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
  5546. - {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70},
  5547. - {0x0001610c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
  5548. - {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
  5549. -};
  5550. -
  5551. static const u32 ar9462_2p1_soc_preamble[][2] = {
  5552. /* Addr allmodes */
  5553. - {0x000040a4, 0x00a0c1c9},
  5554. + {0x000040a4, 0x00a0c9c9},
  5555. {0x00007020, 0x00000000},
  5556. {0x00007034, 0x00000002},
  5557. {0x00007038, 0x000004c2},
  5558. };
  5559. -static const u32 ar9462_2p1_soc_postamble[][5] = {
  5560. - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  5561. - {0x00007010, 0x00000033, 0x00000033, 0x00000033, 0x00000033},
  5562. -};
  5563. -
  5564. -static const u32 ar9462_2p1_radio_postamble_sys2ant[][5] = {
  5565. - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  5566. - {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
  5567. - {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
  5568. - {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
  5569. -};
  5570. -
  5571. -static const u32 ar9462_2p1_common_rx_gain[][2] = {
  5572. - /* Addr allmodes */
  5573. - {0x0000a000, 0x00010000},
  5574. - {0x0000a004, 0x00030002},
  5575. - {0x0000a008, 0x00050004},
  5576. - {0x0000a00c, 0x00810080},
  5577. - {0x0000a010, 0x00830082},
  5578. - {0x0000a014, 0x01810180},
  5579. - {0x0000a018, 0x01830182},
  5580. - {0x0000a01c, 0x01850184},
  5581. - {0x0000a020, 0x01890188},
  5582. - {0x0000a024, 0x018b018a},
  5583. - {0x0000a028, 0x018d018c},
  5584. - {0x0000a02c, 0x01910190},
  5585. - {0x0000a030, 0x01930192},
  5586. - {0x0000a034, 0x01950194},
  5587. - {0x0000a038, 0x038a0196},
  5588. - {0x0000a03c, 0x038c038b},
  5589. - {0x0000a040, 0x0390038d},
  5590. - {0x0000a044, 0x03920391},
  5591. - {0x0000a048, 0x03940393},
  5592. - {0x0000a04c, 0x03960395},
  5593. - {0x0000a050, 0x00000000},
  5594. - {0x0000a054, 0x00000000},
  5595. - {0x0000a058, 0x00000000},
  5596. - {0x0000a05c, 0x00000000},
  5597. - {0x0000a060, 0x00000000},
  5598. - {0x0000a064, 0x00000000},
  5599. - {0x0000a068, 0x00000000},
  5600. - {0x0000a06c, 0x00000000},
  5601. - {0x0000a070, 0x00000000},
  5602. - {0x0000a074, 0x00000000},
  5603. - {0x0000a078, 0x00000000},
  5604. - {0x0000a07c, 0x00000000},
  5605. - {0x0000a080, 0x22222229},
  5606. - {0x0000a084, 0x1d1d1d1d},
  5607. - {0x0000a088, 0x1d1d1d1d},
  5608. - {0x0000a08c, 0x1d1d1d1d},
  5609. - {0x0000a090, 0x171d1d1d},
  5610. - {0x0000a094, 0x11111717},
  5611. - {0x0000a098, 0x00030311},
  5612. - {0x0000a09c, 0x00000000},
  5613. - {0x0000a0a0, 0x00000000},
  5614. - {0x0000a0a4, 0x00000000},
  5615. - {0x0000a0a8, 0x00000000},
  5616. - {0x0000a0ac, 0x00000000},
  5617. - {0x0000a0b0, 0x00000000},
  5618. - {0x0000a0b4, 0x00000000},
  5619. - {0x0000a0b8, 0x00000000},
  5620. - {0x0000a0bc, 0x00000000},
  5621. - {0x0000a0c0, 0x001f0000},
  5622. - {0x0000a0c4, 0x01000101},
  5623. - {0x0000a0c8, 0x011e011f},
  5624. - {0x0000a0cc, 0x011c011d},
  5625. - {0x0000a0d0, 0x02030204},
  5626. - {0x0000a0d4, 0x02010202},
  5627. - {0x0000a0d8, 0x021f0200},
  5628. - {0x0000a0dc, 0x0302021e},
  5629. - {0x0000a0e0, 0x03000301},
  5630. - {0x0000a0e4, 0x031e031f},
  5631. - {0x0000a0e8, 0x0402031d},
  5632. - {0x0000a0ec, 0x04000401},
  5633. - {0x0000a0f0, 0x041e041f},
  5634. - {0x0000a0f4, 0x0502041d},
  5635. - {0x0000a0f8, 0x05000501},
  5636. - {0x0000a0fc, 0x051e051f},
  5637. - {0x0000a100, 0x06010602},
  5638. - {0x0000a104, 0x061f0600},
  5639. - {0x0000a108, 0x061d061e},
  5640. - {0x0000a10c, 0x07020703},
  5641. - {0x0000a110, 0x07000701},
  5642. - {0x0000a114, 0x00000000},
  5643. - {0x0000a118, 0x00000000},
  5644. - {0x0000a11c, 0x00000000},
  5645. - {0x0000a120, 0x00000000},
  5646. - {0x0000a124, 0x00000000},
  5647. - {0x0000a128, 0x00000000},
  5648. - {0x0000a12c, 0x00000000},
  5649. - {0x0000a130, 0x00000000},
  5650. - {0x0000a134, 0x00000000},
  5651. - {0x0000a138, 0x00000000},
  5652. - {0x0000a13c, 0x00000000},
  5653. - {0x0000a140, 0x001f0000},
  5654. - {0x0000a144, 0x01000101},
  5655. - {0x0000a148, 0x011e011f},
  5656. - {0x0000a14c, 0x011c011d},
  5657. - {0x0000a150, 0x02030204},
  5658. - {0x0000a154, 0x02010202},
  5659. - {0x0000a158, 0x021f0200},
  5660. - {0x0000a15c, 0x0302021e},
  5661. - {0x0000a160, 0x03000301},
  5662. - {0x0000a164, 0x031e031f},
  5663. - {0x0000a168, 0x0402031d},
  5664. - {0x0000a16c, 0x04000401},
  5665. - {0x0000a170, 0x041e041f},
  5666. - {0x0000a174, 0x0502041d},
  5667. - {0x0000a178, 0x05000501},
  5668. - {0x0000a17c, 0x051e051f},
  5669. - {0x0000a180, 0x06010602},
  5670. - {0x0000a184, 0x061f0600},
  5671. - {0x0000a188, 0x061d061e},
  5672. - {0x0000a18c, 0x07020703},
  5673. - {0x0000a190, 0x07000701},
  5674. - {0x0000a194, 0x00000000},
  5675. - {0x0000a198, 0x00000000},
  5676. - {0x0000a19c, 0x00000000},
  5677. - {0x0000a1a0, 0x00000000},
  5678. - {0x0000a1a4, 0x00000000},
  5679. - {0x0000a1a8, 0x00000000},
  5680. - {0x0000a1ac, 0x00000000},
  5681. - {0x0000a1b0, 0x00000000},
  5682. - {0x0000a1b4, 0x00000000},
  5683. - {0x0000a1b8, 0x00000000},
  5684. - {0x0000a1bc, 0x00000000},
  5685. - {0x0000a1c0, 0x00000000},
  5686. - {0x0000a1c4, 0x00000000},
  5687. - {0x0000a1c8, 0x00000000},
  5688. - {0x0000a1cc, 0x00000000},
  5689. - {0x0000a1d0, 0x00000000},
  5690. - {0x0000a1d4, 0x00000000},
  5691. - {0x0000a1d8, 0x00000000},
  5692. - {0x0000a1dc, 0x00000000},
  5693. - {0x0000a1e0, 0x00000000},
  5694. - {0x0000a1e4, 0x00000000},
  5695. - {0x0000a1e8, 0x00000000},
  5696. - {0x0000a1ec, 0x00000000},
  5697. - {0x0000a1f0, 0x00000396},
  5698. - {0x0000a1f4, 0x00000396},
  5699. - {0x0000a1f8, 0x00000396},
  5700. - {0x0000a1fc, 0x00000196},
  5701. - {0x0000b000, 0x00010000},
  5702. - {0x0000b004, 0x00030002},
  5703. - {0x0000b008, 0x00050004},
  5704. - {0x0000b00c, 0x00810080},
  5705. - {0x0000b010, 0x00830082},
  5706. - {0x0000b014, 0x01810180},
  5707. - {0x0000b018, 0x01830182},
  5708. - {0x0000b01c, 0x01850184},
  5709. - {0x0000b020, 0x02810280},
  5710. - {0x0000b024, 0x02830282},
  5711. - {0x0000b028, 0x02850284},
  5712. - {0x0000b02c, 0x02890288},
  5713. - {0x0000b030, 0x028b028a},
  5714. - {0x0000b034, 0x0388028c},
  5715. - {0x0000b038, 0x038a0389},
  5716. - {0x0000b03c, 0x038c038b},
  5717. - {0x0000b040, 0x0390038d},
  5718. - {0x0000b044, 0x03920391},
  5719. - {0x0000b048, 0x03940393},
  5720. - {0x0000b04c, 0x03960395},
  5721. - {0x0000b050, 0x00000000},
  5722. - {0x0000b054, 0x00000000},
  5723. - {0x0000b058, 0x00000000},
  5724. - {0x0000b05c, 0x00000000},
  5725. - {0x0000b060, 0x00000000},
  5726. - {0x0000b064, 0x00000000},
  5727. - {0x0000b068, 0x00000000},
  5728. - {0x0000b06c, 0x00000000},
  5729. - {0x0000b070, 0x00000000},
  5730. - {0x0000b074, 0x00000000},
  5731. - {0x0000b078, 0x00000000},
  5732. - {0x0000b07c, 0x00000000},
  5733. - {0x0000b080, 0x2a2d2f32},
  5734. - {0x0000b084, 0x21232328},
  5735. - {0x0000b088, 0x19191c1e},
  5736. - {0x0000b08c, 0x12141417},
  5737. - {0x0000b090, 0x07070e0e},
  5738. - {0x0000b094, 0x03030305},
  5739. - {0x0000b098, 0x00000003},
  5740. - {0x0000b09c, 0x00000000},
  5741. - {0x0000b0a0, 0x00000000},
  5742. - {0x0000b0a4, 0x00000000},
  5743. - {0x0000b0a8, 0x00000000},
  5744. - {0x0000b0ac, 0x00000000},
  5745. - {0x0000b0b0, 0x00000000},
  5746. - {0x0000b0b4, 0x00000000},
  5747. - {0x0000b0b8, 0x00000000},
  5748. - {0x0000b0bc, 0x00000000},
  5749. - {0x0000b0c0, 0x003f0020},
  5750. - {0x0000b0c4, 0x00400041},
  5751. - {0x0000b0c8, 0x0140005f},
  5752. - {0x0000b0cc, 0x0160015f},
  5753. - {0x0000b0d0, 0x017e017f},
  5754. - {0x0000b0d4, 0x02410242},
  5755. - {0x0000b0d8, 0x025f0240},
  5756. - {0x0000b0dc, 0x027f0260},
  5757. - {0x0000b0e0, 0x0341027e},
  5758. - {0x0000b0e4, 0x035f0340},
  5759. - {0x0000b0e8, 0x037f0360},
  5760. - {0x0000b0ec, 0x04400441},
  5761. - {0x0000b0f0, 0x0460045f},
  5762. - {0x0000b0f4, 0x0541047f},
  5763. - {0x0000b0f8, 0x055f0540},
  5764. - {0x0000b0fc, 0x057f0560},
  5765. - {0x0000b100, 0x06400641},
  5766. - {0x0000b104, 0x0660065f},
  5767. - {0x0000b108, 0x067e067f},
  5768. - {0x0000b10c, 0x07410742},
  5769. - {0x0000b110, 0x075f0740},
  5770. - {0x0000b114, 0x077f0760},
  5771. - {0x0000b118, 0x07800781},
  5772. - {0x0000b11c, 0x07a0079f},
  5773. - {0x0000b120, 0x07c107bf},
  5774. - {0x0000b124, 0x000007c0},
  5775. - {0x0000b128, 0x00000000},
  5776. - {0x0000b12c, 0x00000000},
  5777. - {0x0000b130, 0x00000000},
  5778. - {0x0000b134, 0x00000000},
  5779. - {0x0000b138, 0x00000000},
  5780. - {0x0000b13c, 0x00000000},
  5781. - {0x0000b140, 0x003f0020},
  5782. - {0x0000b144, 0x00400041},
  5783. - {0x0000b148, 0x0140005f},
  5784. - {0x0000b14c, 0x0160015f},
  5785. - {0x0000b150, 0x017e017f},
  5786. - {0x0000b154, 0x02410242},
  5787. - {0x0000b158, 0x025f0240},
  5788. - {0x0000b15c, 0x027f0260},
  5789. - {0x0000b160, 0x0341027e},
  5790. - {0x0000b164, 0x035f0340},
  5791. - {0x0000b168, 0x037f0360},
  5792. - {0x0000b16c, 0x04400441},
  5793. - {0x0000b170, 0x0460045f},
  5794. - {0x0000b174, 0x0541047f},
  5795. - {0x0000b178, 0x055f0540},
  5796. - {0x0000b17c, 0x057f0560},
  5797. - {0x0000b180, 0x06400641},
  5798. - {0x0000b184, 0x0660065f},
  5799. - {0x0000b188, 0x067e067f},
  5800. - {0x0000b18c, 0x07410742},
  5801. - {0x0000b190, 0x075f0740},
  5802. - {0x0000b194, 0x077f0760},
  5803. - {0x0000b198, 0x07800781},
  5804. - {0x0000b19c, 0x07a0079f},
  5805. - {0x0000b1a0, 0x07c107bf},
  5806. - {0x0000b1a4, 0x000007c0},
  5807. - {0x0000b1a8, 0x00000000},
  5808. - {0x0000b1ac, 0x00000000},
  5809. - {0x0000b1b0, 0x00000000},
  5810. - {0x0000b1b4, 0x00000000},
  5811. - {0x0000b1b8, 0x00000000},
  5812. - {0x0000b1bc, 0x00000000},
  5813. - {0x0000b1c0, 0x00000000},
  5814. - {0x0000b1c4, 0x00000000},
  5815. - {0x0000b1c8, 0x00000000},
  5816. - {0x0000b1cc, 0x00000000},
  5817. - {0x0000b1d0, 0x00000000},
  5818. - {0x0000b1d4, 0x00000000},
  5819. - {0x0000b1d8, 0x00000000},
  5820. - {0x0000b1dc, 0x00000000},
  5821. - {0x0000b1e0, 0x00000000},
  5822. - {0x0000b1e4, 0x00000000},
  5823. - {0x0000b1e8, 0x00000000},
  5824. - {0x0000b1ec, 0x00000000},
  5825. - {0x0000b1f0, 0x00000396},
  5826. - {0x0000b1f4, 0x00000396},
  5827. - {0x0000b1f8, 0x00000396},
  5828. - {0x0000b1fc, 0x00000196},
  5829. -};
  5830. -
  5831. -static const u32 ar9462_2p1_common_mixed_rx_gain[][2] = {
  5832. - /* Addr allmodes */
  5833. - {0x0000a000, 0x00010000},
  5834. - {0x0000a004, 0x00030002},
  5835. - {0x0000a008, 0x00050004},
  5836. - {0x0000a00c, 0x00810080},
  5837. - {0x0000a010, 0x00830082},
  5838. - {0x0000a014, 0x01810180},
  5839. - {0x0000a018, 0x01830182},
  5840. - {0x0000a01c, 0x01850184},
  5841. - {0x0000a020, 0x01890188},
  5842. - {0x0000a024, 0x018b018a},
  5843. - {0x0000a028, 0x018d018c},
  5844. - {0x0000a02c, 0x03820190},
  5845. - {0x0000a030, 0x03840383},
  5846. - {0x0000a034, 0x03880385},
  5847. - {0x0000a038, 0x038a0389},
  5848. - {0x0000a03c, 0x038c038b},
  5849. - {0x0000a040, 0x0390038d},
  5850. - {0x0000a044, 0x03920391},
  5851. - {0x0000a048, 0x03940393},
  5852. - {0x0000a04c, 0x03960395},
  5853. - {0x0000a050, 0x00000000},
  5854. - {0x0000a054, 0x00000000},
  5855. - {0x0000a058, 0x00000000},
  5856. - {0x0000a05c, 0x00000000},
  5857. - {0x0000a060, 0x00000000},
  5858. - {0x0000a064, 0x00000000},
  5859. - {0x0000a068, 0x00000000},
  5860. - {0x0000a06c, 0x00000000},
  5861. - {0x0000a070, 0x00000000},
  5862. - {0x0000a074, 0x00000000},
  5863. - {0x0000a078, 0x00000000},
  5864. - {0x0000a07c, 0x00000000},
  5865. - {0x0000a080, 0x29292929},
  5866. - {0x0000a084, 0x29292929},
  5867. - {0x0000a088, 0x29292929},
  5868. - {0x0000a08c, 0x29292929},
  5869. - {0x0000a090, 0x22292929},
  5870. - {0x0000a094, 0x1d1d2222},
  5871. - {0x0000a098, 0x0c111117},
  5872. - {0x0000a09c, 0x00030303},
  5873. - {0x0000a0a0, 0x00000000},
  5874. - {0x0000a0a4, 0x00000000},
  5875. - {0x0000a0a8, 0x00000000},
  5876. - {0x0000a0ac, 0x00000000},
  5877. - {0x0000a0b0, 0x00000000},
  5878. - {0x0000a0b4, 0x00000000},
  5879. - {0x0000a0b8, 0x00000000},
  5880. - {0x0000a0bc, 0x00000000},
  5881. - {0x0000a0c0, 0x001f0000},
  5882. - {0x0000a0c4, 0x01000101},
  5883. - {0x0000a0c8, 0x011e011f},
  5884. - {0x0000a0cc, 0x011c011d},
  5885. - {0x0000a0d0, 0x02030204},
  5886. - {0x0000a0d4, 0x02010202},
  5887. - {0x0000a0d8, 0x021f0200},
  5888. - {0x0000a0dc, 0x0302021e},
  5889. - {0x0000a0e0, 0x03000301},
  5890. - {0x0000a0e4, 0x031e031f},
  5891. - {0x0000a0e8, 0x0402031d},
  5892. - {0x0000a0ec, 0x04000401},
  5893. - {0x0000a0f0, 0x041e041f},
  5894. - {0x0000a0f4, 0x0502041d},
  5895. - {0x0000a0f8, 0x05000501},
  5896. - {0x0000a0fc, 0x051e051f},
  5897. - {0x0000a100, 0x06010602},
  5898. - {0x0000a104, 0x061f0600},
  5899. - {0x0000a108, 0x061d061e},
  5900. - {0x0000a10c, 0x07020703},
  5901. - {0x0000a110, 0x07000701},
  5902. - {0x0000a114, 0x00000000},
  5903. - {0x0000a118, 0x00000000},
  5904. - {0x0000a11c, 0x00000000},
  5905. - {0x0000a120, 0x00000000},
  5906. - {0x0000a124, 0x00000000},
  5907. - {0x0000a128, 0x00000000},
  5908. - {0x0000a12c, 0x00000000},
  5909. - {0x0000a130, 0x00000000},
  5910. - {0x0000a134, 0x00000000},
  5911. - {0x0000a138, 0x00000000},
  5912. - {0x0000a13c, 0x00000000},
  5913. - {0x0000a140, 0x001f0000},
  5914. - {0x0000a144, 0x01000101},
  5915. - {0x0000a148, 0x011e011f},
  5916. - {0x0000a14c, 0x011c011d},
  5917. - {0x0000a150, 0x02030204},
  5918. - {0x0000a154, 0x02010202},
  5919. - {0x0000a158, 0x021f0200},
  5920. - {0x0000a15c, 0x0302021e},
  5921. - {0x0000a160, 0x03000301},
  5922. - {0x0000a164, 0x031e031f},
  5923. - {0x0000a168, 0x0402031d},
  5924. - {0x0000a16c, 0x04000401},
  5925. - {0x0000a170, 0x041e041f},
  5926. - {0x0000a174, 0x0502041d},
  5927. - {0x0000a178, 0x05000501},
  5928. - {0x0000a17c, 0x051e051f},
  5929. - {0x0000a180, 0x06010602},
  5930. - {0x0000a184, 0x061f0600},
  5931. - {0x0000a188, 0x061d061e},
  5932. - {0x0000a18c, 0x07020703},
  5933. - {0x0000a190, 0x07000701},
  5934. - {0x0000a194, 0x00000000},
  5935. - {0x0000a198, 0x00000000},
  5936. - {0x0000a19c, 0x00000000},
  5937. - {0x0000a1a0, 0x00000000},
  5938. - {0x0000a1a4, 0x00000000},
  5939. - {0x0000a1a8, 0x00000000},
  5940. - {0x0000a1ac, 0x00000000},
  5941. - {0x0000a1b0, 0x00000000},
  5942. - {0x0000a1b4, 0x00000000},
  5943. - {0x0000a1b8, 0x00000000},
  5944. - {0x0000a1bc, 0x00000000},
  5945. - {0x0000a1c0, 0x00000000},
  5946. - {0x0000a1c4, 0x00000000},
  5947. - {0x0000a1c8, 0x00000000},
  5948. - {0x0000a1cc, 0x00000000},
  5949. - {0x0000a1d0, 0x00000000},
  5950. - {0x0000a1d4, 0x00000000},
  5951. - {0x0000a1d8, 0x00000000},
  5952. - {0x0000a1dc, 0x00000000},
  5953. - {0x0000a1e0, 0x00000000},
  5954. - {0x0000a1e4, 0x00000000},
  5955. - {0x0000a1e8, 0x00000000},
  5956. - {0x0000a1ec, 0x00000000},
  5957. - {0x0000a1f0, 0x00000396},
  5958. - {0x0000a1f4, 0x00000396},
  5959. - {0x0000a1f8, 0x00000396},
  5960. - {0x0000a1fc, 0x00000196},
  5961. - {0x0000b000, 0x00010000},
  5962. - {0x0000b004, 0x00030002},
  5963. - {0x0000b008, 0x00050004},
  5964. - {0x0000b00c, 0x00810080},
  5965. - {0x0000b010, 0x00830082},
  5966. - {0x0000b014, 0x01810180},
  5967. - {0x0000b018, 0x01830182},
  5968. - {0x0000b01c, 0x01850184},
  5969. - {0x0000b020, 0x02810280},
  5970. - {0x0000b024, 0x02830282},
  5971. - {0x0000b028, 0x02850284},
  5972. - {0x0000b02c, 0x02890288},
  5973. - {0x0000b030, 0x028b028a},
  5974. - {0x0000b034, 0x0388028c},
  5975. - {0x0000b038, 0x038a0389},
  5976. - {0x0000b03c, 0x038c038b},
  5977. - {0x0000b040, 0x0390038d},
  5978. - {0x0000b044, 0x03920391},
  5979. - {0x0000b048, 0x03940393},
  5980. - {0x0000b04c, 0x03960395},
  5981. - {0x0000b050, 0x00000000},
  5982. - {0x0000b054, 0x00000000},
  5983. - {0x0000b058, 0x00000000},
  5984. - {0x0000b05c, 0x00000000},
  5985. - {0x0000b060, 0x00000000},
  5986. - {0x0000b064, 0x00000000},
  5987. - {0x0000b068, 0x00000000},
  5988. - {0x0000b06c, 0x00000000},
  5989. - {0x0000b070, 0x00000000},
  5990. - {0x0000b074, 0x00000000},
  5991. - {0x0000b078, 0x00000000},
  5992. - {0x0000b07c, 0x00000000},
  5993. - {0x0000b080, 0x2a2d2f32},
  5994. - {0x0000b084, 0x21232328},
  5995. - {0x0000b088, 0x19191c1e},
  5996. - {0x0000b08c, 0x12141417},
  5997. - {0x0000b090, 0x07070e0e},
  5998. - {0x0000b094, 0x03030305},
  5999. - {0x0000b098, 0x00000003},
  6000. - {0x0000b09c, 0x00000000},
  6001. - {0x0000b0a0, 0x00000000},
  6002. - {0x0000b0a4, 0x00000000},
  6003. - {0x0000b0a8, 0x00000000},
  6004. - {0x0000b0ac, 0x00000000},
  6005. - {0x0000b0b0, 0x00000000},
  6006. - {0x0000b0b4, 0x00000000},
  6007. - {0x0000b0b8, 0x00000000},
  6008. - {0x0000b0bc, 0x00000000},
  6009. - {0x0000b0c0, 0x003f0020},
  6010. - {0x0000b0c4, 0x00400041},
  6011. - {0x0000b0c8, 0x0140005f},
  6012. - {0x0000b0cc, 0x0160015f},
  6013. - {0x0000b0d0, 0x017e017f},
  6014. - {0x0000b0d4, 0x02410242},
  6015. - {0x0000b0d8, 0x025f0240},
  6016. - {0x0000b0dc, 0x027f0260},
  6017. - {0x0000b0e0, 0x0341027e},
  6018. - {0x0000b0e4, 0x035f0340},
  6019. - {0x0000b0e8, 0x037f0360},
  6020. - {0x0000b0ec, 0x04400441},
  6021. - {0x0000b0f0, 0x0460045f},
  6022. - {0x0000b0f4, 0x0541047f},
  6023. - {0x0000b0f8, 0x055f0540},
  6024. - {0x0000b0fc, 0x057f0560},
  6025. - {0x0000b100, 0x06400641},
  6026. - {0x0000b104, 0x0660065f},
  6027. - {0x0000b108, 0x067e067f},
  6028. - {0x0000b10c, 0x07410742},
  6029. - {0x0000b110, 0x075f0740},
  6030. - {0x0000b114, 0x077f0760},
  6031. - {0x0000b118, 0x07800781},
  6032. - {0x0000b11c, 0x07a0079f},
  6033. - {0x0000b120, 0x07c107bf},
  6034. - {0x0000b124, 0x000007c0},
  6035. - {0x0000b128, 0x00000000},
  6036. - {0x0000b12c, 0x00000000},
  6037. - {0x0000b130, 0x00000000},
  6038. - {0x0000b134, 0x00000000},
  6039. - {0x0000b138, 0x00000000},
  6040. - {0x0000b13c, 0x00000000},
  6041. - {0x0000b140, 0x003f0020},
  6042. - {0x0000b144, 0x00400041},
  6043. - {0x0000b148, 0x0140005f},
  6044. - {0x0000b14c, 0x0160015f},
  6045. - {0x0000b150, 0x017e017f},
  6046. - {0x0000b154, 0x02410242},
  6047. - {0x0000b158, 0x025f0240},
  6048. - {0x0000b15c, 0x027f0260},
  6049. - {0x0000b160, 0x0341027e},
  6050. - {0x0000b164, 0x035f0340},
  6051. - {0x0000b168, 0x037f0360},
  6052. - {0x0000b16c, 0x04400441},
  6053. - {0x0000b170, 0x0460045f},
  6054. - {0x0000b174, 0x0541047f},
  6055. - {0x0000b178, 0x055f0540},
  6056. - {0x0000b17c, 0x057f0560},
  6057. - {0x0000b180, 0x06400641},
  6058. - {0x0000b184, 0x0660065f},
  6059. - {0x0000b188, 0x067e067f},
  6060. - {0x0000b18c, 0x07410742},
  6061. - {0x0000b190, 0x075f0740},
  6062. - {0x0000b194, 0x077f0760},
  6063. - {0x0000b198, 0x07800781},
  6064. - {0x0000b19c, 0x07a0079f},
  6065. - {0x0000b1a0, 0x07c107bf},
  6066. - {0x0000b1a4, 0x000007c0},
  6067. - {0x0000b1a8, 0x00000000},
  6068. - {0x0000b1ac, 0x00000000},
  6069. - {0x0000b1b0, 0x00000000},
  6070. - {0x0000b1b4, 0x00000000},
  6071. - {0x0000b1b8, 0x00000000},
  6072. - {0x0000b1bc, 0x00000000},
  6073. - {0x0000b1c0, 0x00000000},
  6074. - {0x0000b1c4, 0x00000000},
  6075. - {0x0000b1c8, 0x00000000},
  6076. - {0x0000b1cc, 0x00000000},
  6077. - {0x0000b1d0, 0x00000000},
  6078. - {0x0000b1d4, 0x00000000},
  6079. - {0x0000b1d8, 0x00000000},
  6080. - {0x0000b1dc, 0x00000000},
  6081. - {0x0000b1e0, 0x00000000},
  6082. - {0x0000b1e4, 0x00000000},
  6083. - {0x0000b1e8, 0x00000000},
  6084. - {0x0000b1ec, 0x00000000},
  6085. - {0x0000b1f0, 0x00000396},
  6086. - {0x0000b1f4, 0x00000396},
  6087. - {0x0000b1f8, 0x00000396},
  6088. - {0x0000b1fc, 0x00000196},
  6089. -};
  6090. -
  6091. -static const u32 ar9462_2p1_baseband_core_mix_rxgain[][2] = {
  6092. - /* Addr allmodes */
  6093. - {0x00009fd0, 0x0a2d6b93},
  6094. -};
  6095. -
  6096. -static const u32 ar9462_2p1_baseband_postamble_mix_rxgain[][5] = {
  6097. - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  6098. - {0x00009820, 0x206a022e, 0x206a022e, 0x206a01ae, 0x206a01ae},
  6099. - {0x00009824, 0x63c640de, 0x5ac640d0, 0x63c640da, 0x63c640da},
  6100. - {0x00009828, 0x0796be89, 0x0696b081, 0x0916be81, 0x0916be81},
  6101. - {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000d8, 0x6c4000d8},
  6102. - {0x00009e10, 0x92c88d2e, 0x7ec88d2e, 0x7ec86d2e, 0x7ec86d2e},
  6103. - {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3236605e, 0x32395c5e},
  6104. -};
  6105. -
  6106. -static const u32 ar9462_2p1_baseband_postamble_5g_xlna[][5] = {
  6107. - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  6108. - {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
  6109. -};
  6110. -
  6111. -static const u32 ar9462_2p1_common_wo_xlna_rx_gain[][2] = {
  6112. - /* Addr allmodes */
  6113. - {0x0000a000, 0x00010000},
  6114. - {0x0000a004, 0x00030002},
  6115. - {0x0000a008, 0x00050004},
  6116. - {0x0000a00c, 0x00810080},
  6117. - {0x0000a010, 0x00830082},
  6118. - {0x0000a014, 0x01810180},
  6119. - {0x0000a018, 0x01830182},
  6120. - {0x0000a01c, 0x01850184},
  6121. - {0x0000a020, 0x01890188},
  6122. - {0x0000a024, 0x018b018a},
  6123. - {0x0000a028, 0x018d018c},
  6124. - {0x0000a02c, 0x03820190},
  6125. - {0x0000a030, 0x03840383},
  6126. - {0x0000a034, 0x03880385},
  6127. - {0x0000a038, 0x038a0389},
  6128. - {0x0000a03c, 0x038c038b},
  6129. - {0x0000a040, 0x0390038d},
  6130. - {0x0000a044, 0x03920391},
  6131. - {0x0000a048, 0x03940393},
  6132. - {0x0000a04c, 0x03960395},
  6133. - {0x0000a050, 0x00000000},
  6134. - {0x0000a054, 0x00000000},
  6135. - {0x0000a058, 0x00000000},
  6136. - {0x0000a05c, 0x00000000},
  6137. - {0x0000a060, 0x00000000},
  6138. - {0x0000a064, 0x00000000},
  6139. - {0x0000a068, 0x00000000},
  6140. - {0x0000a06c, 0x00000000},
  6141. - {0x0000a070, 0x00000000},
  6142. - {0x0000a074, 0x00000000},
  6143. - {0x0000a078, 0x00000000},
  6144. - {0x0000a07c, 0x00000000},
  6145. - {0x0000a080, 0x29292929},
  6146. - {0x0000a084, 0x29292929},
  6147. - {0x0000a088, 0x29292929},
  6148. - {0x0000a08c, 0x29292929},
  6149. - {0x0000a090, 0x22292929},
  6150. - {0x0000a094, 0x1d1d2222},
  6151. - {0x0000a098, 0x0c111117},
  6152. - {0x0000a09c, 0x00030303},
  6153. - {0x0000a0a0, 0x00000000},
  6154. - {0x0000a0a4, 0x00000000},
  6155. - {0x0000a0a8, 0x00000000},
  6156. - {0x0000a0ac, 0x00000000},
  6157. - {0x0000a0b0, 0x00000000},
  6158. - {0x0000a0b4, 0x00000000},
  6159. - {0x0000a0b8, 0x00000000},
  6160. - {0x0000a0bc, 0x00000000},
  6161. - {0x0000a0c0, 0x001f0000},
  6162. - {0x0000a0c4, 0x01000101},
  6163. - {0x0000a0c8, 0x011e011f},
  6164. - {0x0000a0cc, 0x011c011d},
  6165. - {0x0000a0d0, 0x02030204},
  6166. - {0x0000a0d4, 0x02010202},
  6167. - {0x0000a0d8, 0x021f0200},
  6168. - {0x0000a0dc, 0x0302021e},
  6169. - {0x0000a0e0, 0x03000301},
  6170. - {0x0000a0e4, 0x031e031f},
  6171. - {0x0000a0e8, 0x0402031d},
  6172. - {0x0000a0ec, 0x04000401},
  6173. - {0x0000a0f0, 0x041e041f},
  6174. - {0x0000a0f4, 0x0502041d},
  6175. - {0x0000a0f8, 0x05000501},
  6176. - {0x0000a0fc, 0x051e051f},
  6177. - {0x0000a100, 0x06010602},
  6178. - {0x0000a104, 0x061f0600},
  6179. - {0x0000a108, 0x061d061e},
  6180. - {0x0000a10c, 0x07020703},
  6181. - {0x0000a110, 0x07000701},
  6182. - {0x0000a114, 0x00000000},
  6183. - {0x0000a118, 0x00000000},
  6184. - {0x0000a11c, 0x00000000},
  6185. - {0x0000a120, 0x00000000},
  6186. - {0x0000a124, 0x00000000},
  6187. - {0x0000a128, 0x00000000},
  6188. - {0x0000a12c, 0x00000000},
  6189. - {0x0000a130, 0x00000000},
  6190. - {0x0000a134, 0x00000000},
  6191. - {0x0000a138, 0x00000000},
  6192. - {0x0000a13c, 0x00000000},
  6193. - {0x0000a140, 0x001f0000},
  6194. - {0x0000a144, 0x01000101},
  6195. - {0x0000a148, 0x011e011f},
  6196. - {0x0000a14c, 0x011c011d},
  6197. - {0x0000a150, 0x02030204},
  6198. - {0x0000a154, 0x02010202},
  6199. - {0x0000a158, 0x021f0200},
  6200. - {0x0000a15c, 0x0302021e},
  6201. - {0x0000a160, 0x03000301},
  6202. - {0x0000a164, 0x031e031f},
  6203. - {0x0000a168, 0x0402031d},
  6204. - {0x0000a16c, 0x04000401},
  6205. - {0x0000a170, 0x041e041f},
  6206. - {0x0000a174, 0x0502041d},
  6207. - {0x0000a178, 0x05000501},
  6208. - {0x0000a17c, 0x051e051f},
  6209. - {0x0000a180, 0x06010602},
  6210. - {0x0000a184, 0x061f0600},
  6211. - {0x0000a188, 0x061d061e},
  6212. - {0x0000a18c, 0x07020703},
  6213. - {0x0000a190, 0x07000701},
  6214. - {0x0000a194, 0x00000000},
  6215. - {0x0000a198, 0x00000000},
  6216. - {0x0000a19c, 0x00000000},
  6217. - {0x0000a1a0, 0x00000000},
  6218. - {0x0000a1a4, 0x00000000},
  6219. - {0x0000a1a8, 0x00000000},
  6220. - {0x0000a1ac, 0x00000000},
  6221. - {0x0000a1b0, 0x00000000},
  6222. - {0x0000a1b4, 0x00000000},
  6223. - {0x0000a1b8, 0x00000000},
  6224. - {0x0000a1bc, 0x00000000},
  6225. - {0x0000a1c0, 0x00000000},
  6226. - {0x0000a1c4, 0x00000000},
  6227. - {0x0000a1c8, 0x00000000},
  6228. - {0x0000a1cc, 0x00000000},
  6229. - {0x0000a1d0, 0x00000000},
  6230. - {0x0000a1d4, 0x00000000},
  6231. - {0x0000a1d8, 0x00000000},
  6232. - {0x0000a1dc, 0x00000000},
  6233. - {0x0000a1e0, 0x00000000},
  6234. - {0x0000a1e4, 0x00000000},
  6235. - {0x0000a1e8, 0x00000000},
  6236. - {0x0000a1ec, 0x00000000},
  6237. - {0x0000a1f0, 0x00000396},
  6238. - {0x0000a1f4, 0x00000396},
  6239. - {0x0000a1f8, 0x00000396},
  6240. - {0x0000a1fc, 0x00000196},
  6241. - {0x0000b000, 0x00010000},
  6242. - {0x0000b004, 0x00030002},
  6243. - {0x0000b008, 0x00050004},
  6244. - {0x0000b00c, 0x00810080},
  6245. - {0x0000b010, 0x00830082},
  6246. - {0x0000b014, 0x01810180},
  6247. - {0x0000b018, 0x01830182},
  6248. - {0x0000b01c, 0x01850184},
  6249. - {0x0000b020, 0x02810280},
  6250. - {0x0000b024, 0x02830282},
  6251. - {0x0000b028, 0x02850284},
  6252. - {0x0000b02c, 0x02890288},
  6253. - {0x0000b030, 0x028b028a},
  6254. - {0x0000b034, 0x0388028c},
  6255. - {0x0000b038, 0x038a0389},
  6256. - {0x0000b03c, 0x038c038b},
  6257. - {0x0000b040, 0x0390038d},
  6258. - {0x0000b044, 0x03920391},
  6259. - {0x0000b048, 0x03940393},
  6260. - {0x0000b04c, 0x03960395},
  6261. - {0x0000b050, 0x00000000},
  6262. - {0x0000b054, 0x00000000},
  6263. - {0x0000b058, 0x00000000},
  6264. - {0x0000b05c, 0x00000000},
  6265. - {0x0000b060, 0x00000000},
  6266. - {0x0000b064, 0x00000000},
  6267. - {0x0000b068, 0x00000000},
  6268. - {0x0000b06c, 0x00000000},
  6269. - {0x0000b070, 0x00000000},
  6270. - {0x0000b074, 0x00000000},
  6271. - {0x0000b078, 0x00000000},
  6272. - {0x0000b07c, 0x00000000},
  6273. - {0x0000b080, 0x32323232},
  6274. - {0x0000b084, 0x2f2f3232},
  6275. - {0x0000b088, 0x23282a2d},
  6276. - {0x0000b08c, 0x1c1e2123},
  6277. - {0x0000b090, 0x14171919},
  6278. - {0x0000b094, 0x0e0e1214},
  6279. - {0x0000b098, 0x03050707},
  6280. - {0x0000b09c, 0x00030303},
  6281. - {0x0000b0a0, 0x00000000},
  6282. - {0x0000b0a4, 0x00000000},
  6283. - {0x0000b0a8, 0x00000000},
  6284. - {0x0000b0ac, 0x00000000},
  6285. - {0x0000b0b0, 0x00000000},
  6286. - {0x0000b0b4, 0x00000000},
  6287. - {0x0000b0b8, 0x00000000},
  6288. - {0x0000b0bc, 0x00000000},
  6289. - {0x0000b0c0, 0x003f0020},
  6290. - {0x0000b0c4, 0x00400041},
  6291. - {0x0000b0c8, 0x0140005f},
  6292. - {0x0000b0cc, 0x0160015f},
  6293. - {0x0000b0d0, 0x017e017f},
  6294. - {0x0000b0d4, 0x02410242},
  6295. - {0x0000b0d8, 0x025f0240},
  6296. - {0x0000b0dc, 0x027f0260},
  6297. - {0x0000b0e0, 0x0341027e},
  6298. - {0x0000b0e4, 0x035f0340},
  6299. - {0x0000b0e8, 0x037f0360},
  6300. - {0x0000b0ec, 0x04400441},
  6301. - {0x0000b0f0, 0x0460045f},
  6302. - {0x0000b0f4, 0x0541047f},
  6303. - {0x0000b0f8, 0x055f0540},
  6304. - {0x0000b0fc, 0x057f0560},
  6305. - {0x0000b100, 0x06400641},
  6306. - {0x0000b104, 0x0660065f},
  6307. - {0x0000b108, 0x067e067f},
  6308. - {0x0000b10c, 0x07410742},
  6309. - {0x0000b110, 0x075f0740},
  6310. - {0x0000b114, 0x077f0760},
  6311. - {0x0000b118, 0x07800781},
  6312. - {0x0000b11c, 0x07a0079f},
  6313. - {0x0000b120, 0x07c107bf},
  6314. - {0x0000b124, 0x000007c0},
  6315. - {0x0000b128, 0x00000000},
  6316. - {0x0000b12c, 0x00000000},
  6317. - {0x0000b130, 0x00000000},
  6318. - {0x0000b134, 0x00000000},
  6319. - {0x0000b138, 0x00000000},
  6320. - {0x0000b13c, 0x00000000},
  6321. - {0x0000b140, 0x003f0020},
  6322. - {0x0000b144, 0x00400041},
  6323. - {0x0000b148, 0x0140005f},
  6324. - {0x0000b14c, 0x0160015f},
  6325. - {0x0000b150, 0x017e017f},
  6326. - {0x0000b154, 0x02410242},
  6327. - {0x0000b158, 0x025f0240},
  6328. - {0x0000b15c, 0x027f0260},
  6329. - {0x0000b160, 0x0341027e},
  6330. - {0x0000b164, 0x035f0340},
  6331. - {0x0000b168, 0x037f0360},
  6332. - {0x0000b16c, 0x04400441},
  6333. - {0x0000b170, 0x0460045f},
  6334. - {0x0000b174, 0x0541047f},
  6335. - {0x0000b178, 0x055f0540},
  6336. - {0x0000b17c, 0x057f0560},
  6337. - {0x0000b180, 0x06400641},
  6338. - {0x0000b184, 0x0660065f},
  6339. - {0x0000b188, 0x067e067f},
  6340. - {0x0000b18c, 0x07410742},
  6341. - {0x0000b190, 0x075f0740},
  6342. - {0x0000b194, 0x077f0760},
  6343. - {0x0000b198, 0x07800781},
  6344. - {0x0000b19c, 0x07a0079f},
  6345. - {0x0000b1a0, 0x07c107bf},
  6346. - {0x0000b1a4, 0x000007c0},
  6347. - {0x0000b1a8, 0x00000000},
  6348. - {0x0000b1ac, 0x00000000},
  6349. - {0x0000b1b0, 0x00000000},
  6350. - {0x0000b1b4, 0x00000000},
  6351. - {0x0000b1b8, 0x00000000},
  6352. - {0x0000b1bc, 0x00000000},
  6353. - {0x0000b1c0, 0x00000000},
  6354. - {0x0000b1c4, 0x00000000},
  6355. - {0x0000b1c8, 0x00000000},
  6356. - {0x0000b1cc, 0x00000000},
  6357. - {0x0000b1d0, 0x00000000},
  6358. - {0x0000b1d4, 0x00000000},
  6359. - {0x0000b1d8, 0x00000000},
  6360. - {0x0000b1dc, 0x00000000},
  6361. - {0x0000b1e0, 0x00000000},
  6362. - {0x0000b1e4, 0x00000000},
  6363. - {0x0000b1e8, 0x00000000},
  6364. - {0x0000b1ec, 0x00000000},
  6365. - {0x0000b1f0, 0x00000396},
  6366. - {0x0000b1f4, 0x00000396},
  6367. - {0x0000b1f8, 0x00000396},
  6368. - {0x0000b1fc, 0x00000196},
  6369. -};
  6370. -
  6371. -static const u32 ar9462_2p1_common_5g_xlna_only_rx_gain[][2] = {
  6372. - /* Addr allmodes */
  6373. - {0x0000a000, 0x00010000},
  6374. - {0x0000a004, 0x00030002},
  6375. - {0x0000a008, 0x00050004},
  6376. - {0x0000a00c, 0x00810080},
  6377. - {0x0000a010, 0x00830082},
  6378. - {0x0000a014, 0x01810180},
  6379. - {0x0000a018, 0x01830182},
  6380. - {0x0000a01c, 0x01850184},
  6381. - {0x0000a020, 0x01890188},
  6382. - {0x0000a024, 0x018b018a},
  6383. - {0x0000a028, 0x018d018c},
  6384. - {0x0000a02c, 0x03820190},
  6385. - {0x0000a030, 0x03840383},
  6386. - {0x0000a034, 0x03880385},
  6387. - {0x0000a038, 0x038a0389},
  6388. - {0x0000a03c, 0x038c038b},
  6389. - {0x0000a040, 0x0390038d},
  6390. - {0x0000a044, 0x03920391},
  6391. - {0x0000a048, 0x03940393},
  6392. - {0x0000a04c, 0x03960395},
  6393. - {0x0000a050, 0x00000000},
  6394. - {0x0000a054, 0x00000000},
  6395. - {0x0000a058, 0x00000000},
  6396. - {0x0000a05c, 0x00000000},
  6397. - {0x0000a060, 0x00000000},
  6398. - {0x0000a064, 0x00000000},
  6399. - {0x0000a068, 0x00000000},
  6400. - {0x0000a06c, 0x00000000},
  6401. - {0x0000a070, 0x00000000},
  6402. - {0x0000a074, 0x00000000},
  6403. - {0x0000a078, 0x00000000},
  6404. - {0x0000a07c, 0x00000000},
  6405. - {0x0000a080, 0x29292929},
  6406. - {0x0000a084, 0x29292929},
  6407. - {0x0000a088, 0x29292929},
  6408. - {0x0000a08c, 0x29292929},
  6409. - {0x0000a090, 0x22292929},
  6410. - {0x0000a094, 0x1d1d2222},
  6411. - {0x0000a098, 0x0c111117},
  6412. - {0x0000a09c, 0x00030303},
  6413. - {0x0000a0a0, 0x00000000},
  6414. - {0x0000a0a4, 0x00000000},
  6415. - {0x0000a0a8, 0x00000000},
  6416. - {0x0000a0ac, 0x00000000},
  6417. - {0x0000a0b0, 0x00000000},
  6418. - {0x0000a0b4, 0x00000000},
  6419. - {0x0000a0b8, 0x00000000},
  6420. - {0x0000a0bc, 0x00000000},
  6421. - {0x0000a0c0, 0x001f0000},
  6422. - {0x0000a0c4, 0x01000101},
  6423. - {0x0000a0c8, 0x011e011f},
  6424. - {0x0000a0cc, 0x011c011d},
  6425. - {0x0000a0d0, 0x02030204},
  6426. - {0x0000a0d4, 0x02010202},
  6427. - {0x0000a0d8, 0x021f0200},
  6428. - {0x0000a0dc, 0x0302021e},
  6429. - {0x0000a0e0, 0x03000301},
  6430. - {0x0000a0e4, 0x031e031f},
  6431. - {0x0000a0e8, 0x0402031d},
  6432. - {0x0000a0ec, 0x04000401},
  6433. - {0x0000a0f0, 0x041e041f},
  6434. - {0x0000a0f4, 0x0502041d},
  6435. - {0x0000a0f8, 0x05000501},
  6436. - {0x0000a0fc, 0x051e051f},
  6437. - {0x0000a100, 0x06010602},
  6438. - {0x0000a104, 0x061f0600},
  6439. - {0x0000a108, 0x061d061e},
  6440. - {0x0000a10c, 0x07020703},
  6441. - {0x0000a110, 0x07000701},
  6442. - {0x0000a114, 0x00000000},
  6443. - {0x0000a118, 0x00000000},
  6444. - {0x0000a11c, 0x00000000},
  6445. - {0x0000a120, 0x00000000},
  6446. - {0x0000a124, 0x00000000},
  6447. - {0x0000a128, 0x00000000},
  6448. - {0x0000a12c, 0x00000000},
  6449. - {0x0000a130, 0x00000000},
  6450. - {0x0000a134, 0x00000000},
  6451. - {0x0000a138, 0x00000000},
  6452. - {0x0000a13c, 0x00000000},
  6453. - {0x0000a140, 0x001f0000},
  6454. - {0x0000a144, 0x01000101},
  6455. - {0x0000a148, 0x011e011f},
  6456. - {0x0000a14c, 0x011c011d},
  6457. - {0x0000a150, 0x02030204},
  6458. - {0x0000a154, 0x02010202},
  6459. - {0x0000a158, 0x021f0200},
  6460. - {0x0000a15c, 0x0302021e},
  6461. - {0x0000a160, 0x03000301},
  6462. - {0x0000a164, 0x031e031f},
  6463. - {0x0000a168, 0x0402031d},
  6464. - {0x0000a16c, 0x04000401},
  6465. - {0x0000a170, 0x041e041f},
  6466. - {0x0000a174, 0x0502041d},
  6467. - {0x0000a178, 0x05000501},
  6468. - {0x0000a17c, 0x051e051f},
  6469. - {0x0000a180, 0x06010602},
  6470. - {0x0000a184, 0x061f0600},
  6471. - {0x0000a188, 0x061d061e},
  6472. - {0x0000a18c, 0x07020703},
  6473. - {0x0000a190, 0x07000701},
  6474. - {0x0000a194, 0x00000000},
  6475. - {0x0000a198, 0x00000000},
  6476. - {0x0000a19c, 0x00000000},
  6477. - {0x0000a1a0, 0x00000000},
  6478. - {0x0000a1a4, 0x00000000},
  6479. - {0x0000a1a8, 0x00000000},
  6480. - {0x0000a1ac, 0x00000000},
  6481. - {0x0000a1b0, 0x00000000},
  6482. - {0x0000a1b4, 0x00000000},
  6483. - {0x0000a1b8, 0x00000000},
  6484. - {0x0000a1bc, 0x00000000},
  6485. - {0x0000a1c0, 0x00000000},
  6486. - {0x0000a1c4, 0x00000000},
  6487. - {0x0000a1c8, 0x00000000},
  6488. - {0x0000a1cc, 0x00000000},
  6489. - {0x0000a1d0, 0x00000000},
  6490. - {0x0000a1d4, 0x00000000},
  6491. - {0x0000a1d8, 0x00000000},
  6492. - {0x0000a1dc, 0x00000000},
  6493. - {0x0000a1e0, 0x00000000},
  6494. - {0x0000a1e4, 0x00000000},
  6495. - {0x0000a1e8, 0x00000000},
  6496. - {0x0000a1ec, 0x00000000},
  6497. - {0x0000a1f0, 0x00000396},
  6498. - {0x0000a1f4, 0x00000396},
  6499. - {0x0000a1f8, 0x00000396},
  6500. - {0x0000a1fc, 0x00000196},
  6501. - {0x0000b000, 0x00010000},
  6502. - {0x0000b004, 0x00030002},
  6503. - {0x0000b008, 0x00050004},
  6504. - {0x0000b00c, 0x00810080},
  6505. - {0x0000b010, 0x00830082},
  6506. - {0x0000b014, 0x01810180},
  6507. - {0x0000b018, 0x01830182},
  6508. - {0x0000b01c, 0x01850184},
  6509. - {0x0000b020, 0x02810280},
  6510. - {0x0000b024, 0x02830282},
  6511. - {0x0000b028, 0x02850284},
  6512. - {0x0000b02c, 0x02890288},
  6513. - {0x0000b030, 0x028b028a},
  6514. - {0x0000b034, 0x0388028c},
  6515. - {0x0000b038, 0x038a0389},
  6516. - {0x0000b03c, 0x038c038b},
  6517. - {0x0000b040, 0x0390038d},
  6518. - {0x0000b044, 0x03920391},
  6519. - {0x0000b048, 0x03940393},
  6520. - {0x0000b04c, 0x03960395},
  6521. - {0x0000b050, 0x00000000},
  6522. - {0x0000b054, 0x00000000},
  6523. - {0x0000b058, 0x00000000},
  6524. - {0x0000b05c, 0x00000000},
  6525. - {0x0000b060, 0x00000000},
  6526. - {0x0000b064, 0x00000000},
  6527. - {0x0000b068, 0x00000000},
  6528. - {0x0000b06c, 0x00000000},
  6529. - {0x0000b070, 0x00000000},
  6530. - {0x0000b074, 0x00000000},
  6531. - {0x0000b078, 0x00000000},
  6532. - {0x0000b07c, 0x00000000},
  6533. - {0x0000b080, 0x2a2d2f32},
  6534. - {0x0000b084, 0x21232328},
  6535. - {0x0000b088, 0x19191c1e},
  6536. - {0x0000b08c, 0x12141417},
  6537. - {0x0000b090, 0x07070e0e},
  6538. - {0x0000b094, 0x03030305},
  6539. - {0x0000b098, 0x00000003},
  6540. - {0x0000b09c, 0x00000000},
  6541. - {0x0000b0a0, 0x00000000},
  6542. - {0x0000b0a4, 0x00000000},
  6543. - {0x0000b0a8, 0x00000000},
  6544. - {0x0000b0ac, 0x00000000},
  6545. - {0x0000b0b0, 0x00000000},
  6546. - {0x0000b0b4, 0x00000000},
  6547. - {0x0000b0b8, 0x00000000},
  6548. - {0x0000b0bc, 0x00000000},
  6549. - {0x0000b0c0, 0x003f0020},
  6550. - {0x0000b0c4, 0x00400041},
  6551. - {0x0000b0c8, 0x0140005f},
  6552. - {0x0000b0cc, 0x0160015f},
  6553. - {0x0000b0d0, 0x017e017f},
  6554. - {0x0000b0d4, 0x02410242},
  6555. - {0x0000b0d8, 0x025f0240},
  6556. - {0x0000b0dc, 0x027f0260},
  6557. - {0x0000b0e0, 0x0341027e},
  6558. - {0x0000b0e4, 0x035f0340},
  6559. - {0x0000b0e8, 0x037f0360},
  6560. - {0x0000b0ec, 0x04400441},
  6561. - {0x0000b0f0, 0x0460045f},
  6562. - {0x0000b0f4, 0x0541047f},
  6563. - {0x0000b0f8, 0x055f0540},
  6564. - {0x0000b0fc, 0x057f0560},
  6565. - {0x0000b100, 0x06400641},
  6566. - {0x0000b104, 0x0660065f},
  6567. - {0x0000b108, 0x067e067f},
  6568. - {0x0000b10c, 0x07410742},
  6569. - {0x0000b110, 0x075f0740},
  6570. - {0x0000b114, 0x077f0760},
  6571. - {0x0000b118, 0x07800781},
  6572. - {0x0000b11c, 0x07a0079f},
  6573. - {0x0000b120, 0x07c107bf},
  6574. - {0x0000b124, 0x000007c0},
  6575. - {0x0000b128, 0x00000000},
  6576. - {0x0000b12c, 0x00000000},
  6577. - {0x0000b130, 0x00000000},
  6578. - {0x0000b134, 0x00000000},
  6579. - {0x0000b138, 0x00000000},
  6580. - {0x0000b13c, 0x00000000},
  6581. - {0x0000b140, 0x003f0020},
  6582. - {0x0000b144, 0x00400041},
  6583. - {0x0000b148, 0x0140005f},
  6584. - {0x0000b14c, 0x0160015f},
  6585. - {0x0000b150, 0x017e017f},
  6586. - {0x0000b154, 0x02410242},
  6587. - {0x0000b158, 0x025f0240},
  6588. - {0x0000b15c, 0x027f0260},
  6589. - {0x0000b160, 0x0341027e},
  6590. - {0x0000b164, 0x035f0340},
  6591. - {0x0000b168, 0x037f0360},
  6592. - {0x0000b16c, 0x04400441},
  6593. - {0x0000b170, 0x0460045f},
  6594. - {0x0000b174, 0x0541047f},
  6595. - {0x0000b178, 0x055f0540},
  6596. - {0x0000b17c, 0x057f0560},
  6597. - {0x0000b180, 0x06400641},
  6598. - {0x0000b184, 0x0660065f},
  6599. - {0x0000b188, 0x067e067f},
  6600. - {0x0000b18c, 0x07410742},
  6601. - {0x0000b190, 0x075f0740},
  6602. - {0x0000b194, 0x077f0760},
  6603. - {0x0000b198, 0x07800781},
  6604. - {0x0000b19c, 0x07a0079f},
  6605. - {0x0000b1a0, 0x07c107bf},
  6606. - {0x0000b1a4, 0x000007c0},
  6607. - {0x0000b1a8, 0x00000000},
  6608. - {0x0000b1ac, 0x00000000},
  6609. - {0x0000b1b0, 0x00000000},
  6610. - {0x0000b1b4, 0x00000000},
  6611. - {0x0000b1b8, 0x00000000},
  6612. - {0x0000b1bc, 0x00000000},
  6613. - {0x0000b1c0, 0x00000000},
  6614. - {0x0000b1c4, 0x00000000},
  6615. - {0x0000b1c8, 0x00000000},
  6616. - {0x0000b1cc, 0x00000000},
  6617. - {0x0000b1d0, 0x00000000},
  6618. - {0x0000b1d4, 0x00000000},
  6619. - {0x0000b1d8, 0x00000000},
  6620. - {0x0000b1dc, 0x00000000},
  6621. - {0x0000b1e0, 0x00000000},
  6622. - {0x0000b1e4, 0x00000000},
  6623. - {0x0000b1e8, 0x00000000},
  6624. - {0x0000b1ec, 0x00000000},
  6625. - {0x0000b1f0, 0x00000396},
  6626. - {0x0000b1f4, 0x00000396},
  6627. - {0x0000b1f8, 0x00000396},
  6628. - {0x0000b1fc, 0x00000196},
  6629. -};
  6630. -
  6631. -static const u32 ar9462_2p1_modes_low_ob_db_tx_gain[][5] = {
  6632. - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  6633. - {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
  6634. - {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
  6635. - {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
  6636. - {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
  6637. - {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
  6638. - {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
  6639. - {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6640. - {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6641. - {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
  6642. - {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
  6643. - {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
  6644. - {0x0000a510, 0x16000220, 0x16000220, 0x0f000202, 0x0f000202},
  6645. - {0x0000a514, 0x1c000223, 0x1c000223, 0x12000400, 0x12000400},
  6646. - {0x0000a518, 0x21020220, 0x21020220, 0x16000402, 0x16000402},
  6647. - {0x0000a51c, 0x27020223, 0x27020223, 0x19000404, 0x19000404},
  6648. - {0x0000a520, 0x2b022220, 0x2b022220, 0x1c000603, 0x1c000603},
  6649. - {0x0000a524, 0x2f022222, 0x2f022222, 0x21000a02, 0x21000a02},
  6650. - {0x0000a528, 0x34022225, 0x34022225, 0x25000a04, 0x25000a04},
  6651. - {0x0000a52c, 0x3a02222a, 0x3a02222a, 0x28000a20, 0x28000a20},
  6652. - {0x0000a530, 0x3e02222c, 0x3e02222c, 0x2c000e20, 0x2c000e20},
  6653. - {0x0000a534, 0x4202242a, 0x4202242a, 0x30000e22, 0x30000e22},
  6654. - {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
  6655. - {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
  6656. - {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
  6657. - {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
  6658. - {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
  6659. - {0x0000a54c, 0x5c04286b, 0x5c04286b, 0x47001a83, 0x47001a83},
  6660. - {0x0000a550, 0x61042a6c, 0x61042a6c, 0x4a001c84, 0x4a001c84},
  6661. - {0x0000a554, 0x66062a6c, 0x66062a6c, 0x4e001ce3, 0x4e001ce3},
  6662. - {0x0000a558, 0x6b062e6c, 0x6b062e6c, 0x52001ce5, 0x52001ce5},
  6663. - {0x0000a55c, 0x7006308c, 0x7006308c, 0x56001ce9, 0x56001ce9},
  6664. - {0x0000a560, 0x730a308a, 0x730a308a, 0x5a001ceb, 0x5a001ceb},
  6665. - {0x0000a564, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
  6666. - {0x0000a568, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
  6667. - {0x0000a56c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
  6668. - {0x0000a570, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
  6669. - {0x0000a574, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
  6670. - {0x0000a578, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
  6671. - {0x0000a57c, 0x770a308c, 0x770a308c, 0x5d001eec, 0x5d001eec},
  6672. - {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6673. - {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6674. - {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6675. - {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6676. - {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6677. - {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
  6678. - {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
  6679. - {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
  6680. - {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
  6681. - {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
  6682. - {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
  6683. - {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
  6684. - {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
  6685. - {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
  6686. - {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
  6687. - {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
  6688. - {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
  6689. - {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
  6690. - {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03f0f800, 0x03f0f800},
  6691. - {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
  6692. - {0x00016044, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
  6693. - {0x00016048, 0x64992060, 0x64992060, 0x64992060, 0x64992060},
  6694. - {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
  6695. - {0x00016444, 0x012482d4, 0x012482d4, 0x012482d4, 0x012482d4},
  6696. - {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
  6697. - {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
  6698. -};
  6699. -
  6700. -static const u32 ar9462_2p1_modes_high_ob_db_tx_gain[][5] = {
  6701. - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  6702. - {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
  6703. - {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
  6704. - {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
  6705. - {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
  6706. - {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
  6707. - {0x0000a410, 0x000050da, 0x000050da, 0x000050de, 0x000050de},
  6708. - {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6709. - {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
  6710. - {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
  6711. - {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
  6712. - {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
  6713. - {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
  6714. - {0x0000a514, 0x18022622, 0x18022622, 0x11000400, 0x11000400},
  6715. - {0x0000a518, 0x1b022822, 0x1b022822, 0x15000402, 0x15000402},
  6716. - {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
  6717. - {0x0000a520, 0x22022c41, 0x22022c41, 0x1b000603, 0x1b000603},
  6718. - {0x0000a524, 0x28023042, 0x28023042, 0x1f000a02, 0x1f000a02},
  6719. - {0x0000a528, 0x2c023044, 0x2c023044, 0x23000a04, 0x23000a04},
  6720. - {0x0000a52c, 0x2f023644, 0x2f023644, 0x26000a20, 0x26000a20},
  6721. - {0x0000a530, 0x34025643, 0x34025643, 0x2a000e20, 0x2a000e20},
  6722. - {0x0000a534, 0x38025a44, 0x38025a44, 0x2e000e22, 0x2e000e22},
  6723. - {0x0000a538, 0x3b025e45, 0x3b025e45, 0x31000e24, 0x31000e24},
  6724. - {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x34001640, 0x34001640},
  6725. - {0x0000a540, 0x48025e6c, 0x48025e6c, 0x38001660, 0x38001660},
  6726. - {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3b001861, 0x3b001861},
  6727. - {0x0000a548, 0x55025eb3, 0x55025eb3, 0x3e001a81, 0x3e001a81},
  6728. - {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x42001a83, 0x42001a83},
  6729. - {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x44001a84, 0x44001a84},
  6730. - {0x0000a554, 0x62025f56, 0x62025f56, 0x48001ce3, 0x48001ce3},
  6731. - {0x0000a558, 0x66027f56, 0x66027f56, 0x4c001ce5, 0x4c001ce5},
  6732. - {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x50001ce9, 0x50001ce9},
  6733. - {0x0000a560, 0x70049f56, 0x70049f56, 0x54001ceb, 0x54001ceb},
  6734. - {0x0000a564, 0x751ffff6, 0x751ffff6, 0x56001eec, 0x56001eec},
  6735. - {0x0000a568, 0x751ffff6, 0x751ffff6, 0x58001ef0, 0x58001ef0},
  6736. - {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x5a001ef4, 0x5a001ef4},
  6737. - {0x0000a570, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
  6738. - {0x0000a574, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
  6739. - {0x0000a578, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
  6740. - {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x5c001ff6, 0x5c001ff6},
  6741. - {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6742. - {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6743. - {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6744. - {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6745. - {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
  6746. - {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
  6747. - {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
  6748. - {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
  6749. - {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
  6750. - {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
  6751. - {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
  6752. - {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
  6753. - {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
  6754. - {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
  6755. - {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
  6756. - {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
  6757. - {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
  6758. - {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
  6759. - {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
  6760. - {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
  6761. - {0x00016044, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4},
  6762. - {0x00016048, 0x8db49060, 0x8db49060, 0x8db49060, 0x8db49060},
  6763. - {0x00016054, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
  6764. - {0x00016444, 0x056d82e4, 0x056d82e4, 0x056d82e4, 0x056d82e4},
  6765. - {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000},
  6766. - {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
  6767. -};
  6768. -
  6769. -static const u32 ar9462_2p1_modes_mix_ob_db_tx_gain[][5] = {
  6770. - /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  6771. - {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
  6772. - {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
  6773. - {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
  6774. - {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
  6775. - {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
  6776. - {0x0000a410, 0x0000d0da, 0x0000d0da, 0x0000d0de, 0x0000d0de},
  6777. - {0x0000a458, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6778. - {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
  6779. - {0x0000a504, 0x06002223, 0x06002223, 0x04000002, 0x04000002},
  6780. - {0x0000a508, 0x0a022220, 0x0a022220, 0x08000004, 0x08000004},
  6781. - {0x0000a50c, 0x0f022223, 0x0f022223, 0x0b000200, 0x0b000200},
  6782. - {0x0000a510, 0x14022620, 0x14022620, 0x0f000202, 0x0f000202},
  6783. - {0x0000a514, 0x18022622, 0x18022622, 0x12000400, 0x12000400},
  6784. - {0x0000a518, 0x1b022822, 0x1b022822, 0x16000402, 0x16000402},
  6785. - {0x0000a51c, 0x20022842, 0x20022842, 0x19000404, 0x19000404},
  6786. - {0x0000a520, 0x22022c41, 0x22022c41, 0x1c000603, 0x1c000603},
  6787. - {0x0000a524, 0x28023042, 0x28023042, 0x21000a02, 0x21000a02},
  6788. - {0x0000a528, 0x2c023044, 0x2c023044, 0x25000a04, 0x25000a04},
  6789. - {0x0000a52c, 0x2f023644, 0x2f023644, 0x28000a20, 0x28000a20},
  6790. - {0x0000a530, 0x34025643, 0x34025643, 0x2c000e20, 0x2c000e20},
  6791. - {0x0000a534, 0x38025a44, 0x38025a44, 0x30000e22, 0x30000e22},
  6792. - {0x0000a538, 0x3b025e45, 0x3b025e45, 0x34000e24, 0x34000e24},
  6793. - {0x0000a53c, 0x41025e4a, 0x41025e4a, 0x38001640, 0x38001640},
  6794. - {0x0000a540, 0x48025e6c, 0x48025e6c, 0x3c001660, 0x3c001660},
  6795. - {0x0000a544, 0x4e025e8e, 0x4e025e8e, 0x3f001861, 0x3f001861},
  6796. - {0x0000a548, 0x55025eb3, 0x55025eb3, 0x43001a81, 0x43001a81},
  6797. - {0x0000a54c, 0x58025ef3, 0x58025ef3, 0x47001a83, 0x47001a83},
  6798. - {0x0000a550, 0x5d025ef6, 0x5d025ef6, 0x4a001c84, 0x4a001c84},
  6799. - {0x0000a554, 0x62025f56, 0x62025f56, 0x4e001ce3, 0x4e001ce3},
  6800. - {0x0000a558, 0x66027f56, 0x66027f56, 0x52001ce5, 0x52001ce5},
  6801. - {0x0000a55c, 0x6a029f56, 0x6a029f56, 0x56001ce9, 0x56001ce9},
  6802. - {0x0000a560, 0x70049f56, 0x70049f56, 0x5a001ceb, 0x5a001ceb},
  6803. - {0x0000a564, 0x751ffff6, 0x751ffff6, 0x5c001eec, 0x5c001eec},
  6804. - {0x0000a568, 0x751ffff6, 0x751ffff6, 0x5e001ef0, 0x5e001ef0},
  6805. - {0x0000a56c, 0x751ffff6, 0x751ffff6, 0x60001ef4, 0x60001ef4},
  6806. - {0x0000a570, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
  6807. - {0x0000a574, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
  6808. - {0x0000a578, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
  6809. - {0x0000a57c, 0x751ffff6, 0x751ffff6, 0x62001ff6, 0x62001ff6},
  6810. - {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6811. - {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6812. - {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6813. - {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6814. - {0x0000a610, 0x00804000, 0x00804000, 0x00000000, 0x00000000},
  6815. - {0x0000a614, 0x00804201, 0x00804201, 0x01404000, 0x01404000},
  6816. - {0x0000a618, 0x0280c802, 0x0280c802, 0x01404501, 0x01404501},
  6817. - {0x0000a61c, 0x0280ca03, 0x0280ca03, 0x02008501, 0x02008501},
  6818. - {0x0000a620, 0x04c15104, 0x04c15104, 0x0280ca03, 0x0280ca03},
  6819. - {0x0000a624, 0x04c15305, 0x04c15305, 0x03010c04, 0x03010c04},
  6820. - {0x0000a628, 0x04c15305, 0x04c15305, 0x04014c04, 0x04014c04},
  6821. - {0x0000a62c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
  6822. - {0x0000a630, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
  6823. - {0x0000a634, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
  6824. - {0x0000a638, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
  6825. - {0x0000a63c, 0x04c15305, 0x04c15305, 0x04015005, 0x04015005},
  6826. - {0x0000b2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
  6827. - {0x0000b2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
  6828. - {0x0000b2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
  6829. - {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
  6830. -};
  6831. -
  6832. -static const u32 ar9462_2p1_modes_fast_clock[][3] = {
  6833. - /* Addr 5G_HT20 5G_HT40 */
  6834. - {0x00001030, 0x00000268, 0x000004d0},
  6835. - {0x00001070, 0x0000018c, 0x00000318},
  6836. - {0x000010b0, 0x00000fd0, 0x00001fa0},
  6837. - {0x00008014, 0x044c044c, 0x08980898},
  6838. - {0x0000801c, 0x148ec02b, 0x148ec057},
  6839. - {0x00008318, 0x000044c0, 0x00008980},
  6840. - {0x00009e00, 0x0372131c, 0x0372131c},
  6841. - {0x0000a230, 0x0000400b, 0x00004016},
  6842. - {0x0000a254, 0x00000898, 0x00001130},
  6843. -};
  6844. -
  6845. -static const u32 ar9462_2p1_baseband_core_txfir_coeff_japan_2484[][2] = {
  6846. - /* Addr allmodes */
  6847. - {0x0000a398, 0x00000000},
  6848. - {0x0000a39c, 0x6f7f0301},
  6849. - {0x0000a3a0, 0xca9228ee},
  6850. -};
  6851. -
  6852. #endif /* INITVALS_9462_2P1_H */
  6853. --- a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
  6854. +++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
  6855. @@ -32,13 +32,6 @@ static const u32 ar9485_1_1_mac_postambl
  6856. {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
  6857. };
  6858. -static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
  6859. - /* Addr allmodes */
  6860. - {0x00018c00, 0x18012e5e},
  6861. - {0x00018c04, 0x000801d8},
  6862. - {0x00018c08, 0x0000080c},
  6863. -};
  6864. -
  6865. static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {
  6866. /* Addr allmodes */
  6867. {0x00009e00, 0x037216a0},
  6868. @@ -1101,20 +1094,6 @@ static const u32 ar9485_common_rx_gain_1
  6869. {0x0000a1fc, 0x00000296},
  6870. };
  6871. -static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
  6872. - /* Addr allmodes */
  6873. - {0x00018c00, 0x18052e5e},
  6874. - {0x00018c04, 0x000801d8},
  6875. - {0x00018c08, 0x0000080c},
  6876. -};
  6877. -
  6878. -static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
  6879. - /* Addr allmodes */
  6880. - {0x00018c00, 0x18053e5e},
  6881. - {0x00018c04, 0x000801d8},
  6882. - {0x00018c08, 0x0000080c},
  6883. -};
  6884. -
  6885. static const u32 ar9485_1_1_soc_preamble[][2] = {
  6886. /* Addr allmodes */
  6887. {0x00004014, 0xba280400},
  6888. @@ -1173,13 +1152,6 @@ static const u32 ar9485_1_1_baseband_pos
  6889. {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  6890. };
  6891. -static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
  6892. - /* Addr allmodes */
  6893. - {0x00018c00, 0x18013e5e},
  6894. - {0x00018c04, 0x000801d8},
  6895. - {0x00018c08, 0x0000080c},
  6896. -};
  6897. -
  6898. static const u32 ar9485_1_1_radio_postamble[][2] = {
  6899. /* Addr allmodes */
  6900. {0x0001609c, 0x0b283f31},
  6901. @@ -1358,4 +1330,18 @@ static const u32 ar9485_1_1_baseband_cor
  6902. {0x0000a3a0, 0xca9228ee},
  6903. };
  6904. +static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
  6905. + /* Addr allmodes */
  6906. + {0x00018c00, 0x18013e5e},
  6907. + {0x00018c04, 0x000801d8},
  6908. + {0x00018c08, 0x0000080c},
  6909. +};
  6910. +
  6911. +static const u32 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1[][2] = {
  6912. + /* Addr allmodes */
  6913. + {0x00018c00, 0x1801265e},
  6914. + {0x00018c04, 0x000801d8},
  6915. + {0x00018c08, 0x0000080c},
  6916. +};
  6917. +
  6918. #endif /* INITVALS_9485_H */
  6919. --- a/drivers/net/wireless/ath/ath9k/pci.c
  6920. +++ b/drivers/net/wireless/ath/ath9k/pci.c
  6921. @@ -195,6 +195,93 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_i
  6922. 0x3219),
  6923. .driver_data = ATH9K_PCI_BT_ANT_DIV },
  6924. + /* AR9485 cards with PLL power-save disabled by default. */
  6925. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  6926. + 0x0032,
  6927. + PCI_VENDOR_ID_AZWAVE,
  6928. + 0x2C97),
  6929. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  6930. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  6931. + 0x0032,
  6932. + PCI_VENDOR_ID_AZWAVE,
  6933. + 0x2100),
  6934. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  6935. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  6936. + 0x0032,
  6937. + 0x1C56, /* ASKEY */
  6938. + 0x4001),
  6939. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  6940. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  6941. + 0x0032,
  6942. + 0x11AD, /* LITEON */
  6943. + 0x6627),
  6944. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  6945. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  6946. + 0x0032,
  6947. + 0x11AD, /* LITEON */
  6948. + 0x6628),
  6949. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  6950. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  6951. + 0x0032,
  6952. + PCI_VENDOR_ID_FOXCONN,
  6953. + 0xE04E),
  6954. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  6955. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  6956. + 0x0032,
  6957. + PCI_VENDOR_ID_FOXCONN,
  6958. + 0xE04F),
  6959. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  6960. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  6961. + 0x0032,
  6962. + 0x144F, /* ASKEY */
  6963. + 0x7197),
  6964. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  6965. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  6966. + 0x0032,
  6967. + 0x1B9A, /* XAVI */
  6968. + 0x2000),
  6969. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  6970. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  6971. + 0x0032,
  6972. + 0x1B9A, /* XAVI */
  6973. + 0x2001),
  6974. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  6975. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  6976. + 0x0032,
  6977. + PCI_VENDOR_ID_AZWAVE,
  6978. + 0x1186),
  6979. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  6980. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  6981. + 0x0032,
  6982. + PCI_VENDOR_ID_AZWAVE,
  6983. + 0x1F86),
  6984. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  6985. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  6986. + 0x0032,
  6987. + PCI_VENDOR_ID_AZWAVE,
  6988. + 0x1195),
  6989. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  6990. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  6991. + 0x0032,
  6992. + PCI_VENDOR_ID_AZWAVE,
  6993. + 0x1F95),
  6994. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  6995. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  6996. + 0x0032,
  6997. + 0x1B9A, /* XAVI */
  6998. + 0x1C00),
  6999. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  7000. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  7001. + 0x0032,
  7002. + 0x1B9A, /* XAVI */
  7003. + 0x1C01),
  7004. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  7005. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
  7006. + 0x0032,
  7007. + PCI_VENDOR_ID_ASUSTEK,
  7008. + 0x850D),
  7009. + .driver_data = ATH9K_PCI_NO_PLL_PWRSAVE },
  7010. +
  7011. { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
  7012. { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */
  7013. --- a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
  7014. +++ b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
  7015. @@ -20,7 +20,7 @@
  7016. /* AR9462 2.0 */
  7017. -static const u32 ar9462_modes_fast_clock_2p0[][3] = {
  7018. +static const u32 ar9462_2p0_modes_fast_clock[][3] = {
  7019. /* Addr 5G_HT20 5G_HT40 */
  7020. {0x00001030, 0x00000268, 0x000004d0},
  7021. {0x00001070, 0x0000018c, 0x00000318},
  7022. @@ -33,13 +33,6 @@ static const u32 ar9462_modes_fast_clock
  7023. {0x0000a254, 0x00000898, 0x00001130},
  7024. };
  7025. -static const u32 ar9462_pciephy_clkreq_enable_L1_2p0[][2] = {
  7026. - /* Addr allmodes */
  7027. - {0x00018c00, 0x18253ede},
  7028. - {0x00018c04, 0x000801d8},
  7029. - {0x00018c08, 0x0003780c},
  7030. -};
  7031. -
  7032. static const u32 ar9462_2p0_baseband_postamble[][5] = {
  7033. /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  7034. {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
  7035. @@ -99,7 +92,7 @@ static const u32 ar9462_2p0_baseband_pos
  7036. {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
  7037. };
  7038. -static const u32 ar9462_common_rx_gain_table_2p0[][2] = {
  7039. +static const u32 ar9462_2p0_common_rx_gain[][2] = {
  7040. /* Addr allmodes */
  7041. {0x0000a000, 0x00010000},
  7042. {0x0000a004, 0x00030002},
  7043. @@ -359,20 +352,13 @@ static const u32 ar9462_common_rx_gain_t
  7044. {0x0000b1fc, 0x00000196},
  7045. };
  7046. -static const u32 ar9462_pciephy_clkreq_disable_L1_2p0[][2] = {
  7047. +static const u32 ar9462_2p0_pciephy_clkreq_disable_L1[][2] = {
  7048. /* Addr allmodes */
  7049. {0x00018c00, 0x18213ede},
  7050. {0x00018c04, 0x000801d8},
  7051. {0x00018c08, 0x0003780c},
  7052. };
  7053. -static const u32 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = {
  7054. - /* Addr allmodes */
  7055. - {0x00018c00, 0x18212ede},
  7056. - {0x00018c04, 0x000801d8},
  7057. - {0x00018c08, 0x0003780c},
  7058. -};
  7059. -
  7060. static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = {
  7061. /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  7062. {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
  7063. @@ -380,7 +366,7 @@ static const u32 ar9462_2p0_radio_postam
  7064. {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
  7065. };
  7066. -static const u32 ar9462_common_wo_xlna_rx_gain_table_2p0[][2] = {
  7067. +static const u32 ar9462_2p0_common_wo_xlna_rx_gain[][2] = {
  7068. /* Addr allmodes */
  7069. {0x0000a000, 0x00010000},
  7070. {0x0000a004, 0x00030002},
  7071. @@ -647,7 +633,7 @@ static const u32 ar9462_2p0_baseband_cor
  7072. {0x0000a3a0, 0xca9228ee},
  7073. };
  7074. -static const u32 ar9462_modes_low_ob_db_tx_gain_table_2p0[][5] = {
  7075. +static const u32 ar9462_2p0_modes_low_ob_db_tx_gain[][5] = {
  7076. /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  7077. {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
  7078. {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
  7079. @@ -879,7 +865,7 @@ static const u32 ar9462_2p0_radio_postam
  7080. {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
  7081. };
  7082. -static const u32 ar9462_modes_mix_ob_db_tx_gain_table_2p0[][5] = {
  7083. +static const u32 ar9462_2p0_modes_mix_ob_db_tx_gain[][5] = {
  7084. /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  7085. {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
  7086. {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
  7087. @@ -942,7 +928,7 @@ static const u32 ar9462_modes_mix_ob_db_
  7088. {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
  7089. };
  7090. -static const u32 ar9462_modes_high_ob_db_tx_gain_table_2p0[][5] = {
  7091. +static const u32 ar9462_2p0_modes_high_ob_db_tx_gain[][5] = {
  7092. /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  7093. {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
  7094. {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
  7095. @@ -1252,7 +1238,7 @@ static const u32 ar9462_2p0_mac_postambl
  7096. {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
  7097. };
  7098. -static const u32 ar9462_common_mixed_rx_gain_table_2p0[][2] = {
  7099. +static const u32 ar9462_2p0_common_mixed_rx_gain[][2] = {
  7100. /* Addr allmodes */
  7101. {0x0000a000, 0x00010000},
  7102. {0x0000a004, 0x00030002},
  7103. @@ -1517,7 +1503,7 @@ static const u32 ar9462_2p0_baseband_pos
  7104. {0x00009e3c, 0xcf946220, 0xcf946220, 0xcfd5c782, 0xcfd5c282},
  7105. };
  7106. -static const u32 ar9462_2p0_5g_xlna_only_rxgain[][2] = {
  7107. +static const u32 ar9462_2p0_common_5g_xlna_only_rxgain[][2] = {
  7108. /* Addr allmodes */
  7109. {0x0000a000, 0x00010000},
  7110. {0x0000a004, 0x00030002},
  7111. --- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
  7112. +++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
  7113. @@ -352,7 +352,7 @@ static const u32 ar9300_2p2_baseband_pos
  7114. {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
  7115. {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
  7116. {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
  7117. - {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982},
  7118. + {0x0000a2d0, 0x00041983, 0x00041983, 0x00041981, 0x00041982},
  7119. {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
  7120. {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  7121. {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
  7122. @@ -378,9 +378,9 @@ static const u32 ar9300_2p2_baseband_cor
  7123. {0x00009814, 0x9280c00a},
  7124. {0x00009818, 0x00000000},
  7125. {0x0000981c, 0x00020028},
  7126. - {0x00009834, 0x6400a290},
  7127. + {0x00009834, 0x6400a190},
  7128. {0x00009838, 0x0108ecff},
  7129. - {0x0000983c, 0x0d000600},
  7130. + {0x0000983c, 0x14000600},
  7131. {0x00009880, 0x201fff00},
  7132. {0x00009884, 0x00001042},
  7133. {0x000098a4, 0x00200400},
  7134. @@ -401,7 +401,7 @@ static const u32 ar9300_2p2_baseband_cor
  7135. {0x00009d04, 0x40206c10},
  7136. {0x00009d08, 0x009c4060},
  7137. {0x00009d0c, 0x9883800a},
  7138. - {0x00009d10, 0x01834061},
  7139. + {0x00009d10, 0x01884061},
  7140. {0x00009d14, 0x00c0040b},
  7141. {0x00009d18, 0x00000000},
  7142. {0x00009e08, 0x0038230c},
  7143. @@ -459,7 +459,7 @@ static const u32 ar9300_2p2_baseband_cor
  7144. {0x0000a3e8, 0x20202020},
  7145. {0x0000a3ec, 0x20202020},
  7146. {0x0000a3f0, 0x00000000},
  7147. - {0x0000a3f4, 0x00000246},
  7148. + {0x0000a3f4, 0x00000000},
  7149. {0x0000a3f8, 0x0c9bd380},
  7150. {0x0000a3fc, 0x000f0f01},
  7151. {0x0000a400, 0x8fa91f01},
  7152. @@ -644,7 +644,7 @@ static const u32 ar9300Modes_high_ob_db_
  7153. {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
  7154. {0x0000a2e4, 0x01ff0000, 0x01ff0000, 0x03f0f800, 0x03f0f800},
  7155. {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
  7156. - {0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
  7157. + {0x0000a410, 0x000050d4, 0x000050d4, 0x000050d9, 0x000050d9},
  7158. {0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
  7159. {0x0000a504, 0x04002222, 0x04002222, 0x04000002, 0x04000002},
  7160. {0x0000a508, 0x09002421, 0x09002421, 0x08000004, 0x08000004},
  7161. @@ -1086,8 +1086,8 @@ static const u32 ar9300Common_rx_gain_ta
  7162. {0x0000b074, 0x00000000},
  7163. {0x0000b078, 0x00000000},
  7164. {0x0000b07c, 0x00000000},
  7165. - {0x0000b080, 0x2a2d2f32},
  7166. - {0x0000b084, 0x21232328},
  7167. + {0x0000b080, 0x23232323},
  7168. + {0x0000b084, 0x21232323},
  7169. {0x0000b088, 0x19191c1e},
  7170. {0x0000b08c, 0x12141417},
  7171. {0x0000b090, 0x07070e0e},
  7172. @@ -1385,9 +1385,9 @@ static const u32 ar9300_2p2_mac_core[][2
  7173. {0x000081f8, 0x00000000},
  7174. {0x000081fc, 0x00000000},
  7175. {0x00008240, 0x00100000},
  7176. - {0x00008244, 0x0010f424},
  7177. + {0x00008244, 0x0010f400},
  7178. {0x00008248, 0x00000800},
  7179. - {0x0000824c, 0x0001e848},
  7180. + {0x0000824c, 0x0001e800},
  7181. {0x00008250, 0x00000000},
  7182. {0x00008254, 0x00000000},
  7183. {0x00008258, 0x00000000},
  7184. @@ -1726,14 +1726,14 @@ static const u32 ar9300PciePhy_pll_on_cl
  7185. static const u32 ar9300PciePhy_clkreq_enable_L1_2p2[][2] = {
  7186. /* Addr allmodes */
  7187. - {0x00004040, 0x08253e5e},
  7188. + {0x00004040, 0x0825365e},
  7189. {0x00004040, 0x0008003b},
  7190. {0x00004044, 0x00000000},
  7191. };
  7192. static const u32 ar9300PciePhy_clkreq_disable_L1_2p2[][2] = {
  7193. /* Addr allmodes */
  7194. - {0x00004040, 0x08213e5e},
  7195. + {0x00004040, 0x0821365e},
  7196. {0x00004040, 0x0008003b},
  7197. {0x00004044, 0x00000000},
  7198. };
  7199. --- /dev/null
  7200. +++ b/drivers/net/wireless/ath/ath9k/ar9565_1p1_initvals.h
  7201. @@ -0,0 +1,64 @@
  7202. +/*
  7203. + * Copyright (c) 2010-2011 Atheros Communications Inc.
  7204. + * Copyright (c) 2011-2012 Qualcomm Atheros Inc.
  7205. + *
  7206. + * Permission to use, copy, modify, and/or distribute this software for any
  7207. + * purpose with or without fee is hereby granted, provided that the above
  7208. + * copyright notice and this permission notice appear in all copies.
  7209. + *
  7210. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  7211. + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  7212. + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  7213. + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  7214. + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  7215. + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  7216. + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  7217. + */
  7218. +
  7219. +#ifndef INITVALS_9565_1P1_H
  7220. +#define INITVALS_9565_1P1_H
  7221. +
  7222. +/* AR9565 1.1 */
  7223. +
  7224. +#define ar9565_1p1_mac_core ar9565_1p0_mac_core
  7225. +
  7226. +#define ar9565_1p1_mac_postamble ar9565_1p0_mac_postamble
  7227. +
  7228. +#define ar9565_1p1_baseband_core ar9565_1p0_baseband_core
  7229. +
  7230. +#define ar9565_1p1_baseband_postamble ar9565_1p0_baseband_postamble
  7231. +
  7232. +#define ar9565_1p1_radio_core ar9565_1p0_radio_core
  7233. +
  7234. +#define ar9565_1p1_soc_preamble ar9565_1p0_soc_preamble
  7235. +
  7236. +#define ar9565_1p1_soc_postamble ar9565_1p0_soc_postamble
  7237. +
  7238. +#define ar9565_1p1_Common_rx_gain_table ar9565_1p0_Common_rx_gain_table
  7239. +
  7240. +#define ar9565_1p1_Modes_lowest_ob_db_tx_gain_table ar9565_1p0_Modes_lowest_ob_db_tx_gain_table
  7241. +
  7242. +#define ar9565_1p1_pciephy_clkreq_disable_L1 ar9565_1p0_pciephy_clkreq_disable_L1
  7243. +
  7244. +#define ar9565_1p1_modes_fast_clock ar9565_1p0_modes_fast_clock
  7245. +
  7246. +#define ar9565_1p1_common_wo_xlna_rx_gain_table ar9565_1p0_common_wo_xlna_rx_gain_table
  7247. +
  7248. +#define ar9565_1p1_modes_low_ob_db_tx_gain_table ar9565_1p0_modes_low_ob_db_tx_gain_table
  7249. +
  7250. +#define ar9565_1p1_modes_high_ob_db_tx_gain_table ar9565_1p0_modes_high_ob_db_tx_gain_table
  7251. +
  7252. +#define ar9565_1p1_modes_high_power_tx_gain_table ar9565_1p0_modes_high_power_tx_gain_table
  7253. +
  7254. +#define ar9565_1p1_baseband_core_txfir_coeff_japan_2484 ar9565_1p0_baseband_core_txfir_coeff_japan_2484
  7255. +
  7256. +static const u32 ar9565_1p1_radio_postamble[][5] = {
  7257. + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  7258. + {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
  7259. + {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
  7260. + {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70},
  7261. + {0x0001610c, 0x40000000, 0x40000000, 0x40000000, 0x40000000},
  7262. + {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
  7263. +};
  7264. +
  7265. +#endif /* INITVALS_9565_1P1_H */
  7266. --- a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
  7267. +++ b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
  7268. @@ -20,18 +20,34 @@
  7269. /* AR9580 1.0 */
  7270. +#define ar9580_1p0_soc_preamble ar9300_2p2_soc_preamble
  7271. +
  7272. +#define ar9580_1p0_soc_postamble ar9300_2p2_soc_postamble
  7273. +
  7274. +#define ar9580_1p0_radio_core ar9300_2p2_radio_core
  7275. +
  7276. +#define ar9580_1p0_mac_postamble ar9300_2p2_mac_postamble
  7277. +
  7278. +#define ar9580_1p0_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
  7279. +
  7280. +#define ar9580_1p0_type5_tx_gain_table ar9300Modes_type5_tx_gain_table_2p2
  7281. +
  7282. +#define ar9580_1p0_high_ob_db_tx_gain_table ar9300Modes_high_ob_db_tx_gain_table_2p2
  7283. +
  7284. #define ar9580_1p0_modes_fast_clock ar9300Modes_fast_clock_2p2
  7285. +#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
  7286. +
  7287. static const u32 ar9580_1p0_radio_postamble[][5] = {
  7288. /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  7289. {0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
  7290. {0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
  7291. {0x000160b0, 0x03284f3e, 0x03284f3e, 0x05d08f20, 0x05d08f20},
  7292. - {0x0001610c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
  7293. + {0x0001610c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
  7294. {0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
  7295. - {0x0001650c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
  7296. + {0x0001650c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
  7297. {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
  7298. - {0x0001690c, 0x08000000, 0x00000000, 0x00000000, 0x00000000},
  7299. + {0x0001690c, 0xc8000000, 0xc0000000, 0xc0000000, 0xc0000000},
  7300. {0x00016940, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
  7301. };
  7302. @@ -44,9 +60,9 @@ static const u32 ar9580_1p0_baseband_cor
  7303. {0x00009814, 0x3280c00a},
  7304. {0x00009818, 0x00000000},
  7305. {0x0000981c, 0x00020028},
  7306. - {0x00009834, 0x6400a290},
  7307. + {0x00009834, 0x6400a190},
  7308. {0x00009838, 0x0108ecff},
  7309. - {0x0000983c, 0x0d000600},
  7310. + {0x0000983c, 0x14000600},
  7311. {0x00009880, 0x201fff00},
  7312. {0x00009884, 0x00001042},
  7313. {0x000098a4, 0x00200400},
  7314. @@ -67,7 +83,7 @@ static const u32 ar9580_1p0_baseband_cor
  7315. {0x00009d04, 0x40206c10},
  7316. {0x00009d08, 0x009c4060},
  7317. {0x00009d0c, 0x9883800a},
  7318. - {0x00009d10, 0x01834061},
  7319. + {0x00009d10, 0x01884061},
  7320. {0x00009d14, 0x00c0040b},
  7321. {0x00009d18, 0x00000000},
  7322. {0x00009e08, 0x0038230c},
  7323. @@ -198,8 +214,6 @@ static const u32 ar9580_1p0_baseband_cor
  7324. {0x0000c420, 0x00000000},
  7325. };
  7326. -#define ar9580_1p0_mac_postamble ar9300_2p2_mac_postamble
  7327. -
  7328. static const u32 ar9580_1p0_low_ob_db_tx_gain_table[][5] = {
  7329. /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  7330. {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
  7331. @@ -306,7 +320,112 @@ static const u32 ar9580_1p0_low_ob_db_tx
  7332. {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
  7333. };
  7334. -#define ar9580_1p0_high_power_tx_gain_table ar9580_1p0_low_ob_db_tx_gain_table
  7335. +static const u32 ar9580_1p0_high_power_tx_gain_table[][5] = {
  7336. + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  7337. + {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
  7338. + {0x0000a2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
  7339. + {0x0000a2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
  7340. + {0x0000a2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
  7341. + {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
  7342. + {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  7343. + {0x0000a504, 0x06000003, 0x06000003, 0x04000002, 0x04000002},
  7344. + {0x0000a508, 0x0a000020, 0x0a000020, 0x08000004, 0x08000004},
  7345. + {0x0000a50c, 0x10000023, 0x10000023, 0x0b000200, 0x0b000200},
  7346. + {0x0000a510, 0x15000028, 0x15000028, 0x0f000202, 0x0f000202},
  7347. + {0x0000a514, 0x1b00002b, 0x1b00002b, 0x12000400, 0x12000400},
  7348. + {0x0000a518, 0x1f020028, 0x1f020028, 0x16000402, 0x16000402},
  7349. + {0x0000a51c, 0x2502002b, 0x2502002b, 0x19000404, 0x19000404},
  7350. + {0x0000a520, 0x2a04002a, 0x2a04002a, 0x1c000603, 0x1c000603},
  7351. + {0x0000a524, 0x2e06002a, 0x2e06002a, 0x21000a02, 0x21000a02},
  7352. + {0x0000a528, 0x3302202d, 0x3302202d, 0x25000a04, 0x25000a04},
  7353. + {0x0000a52c, 0x3804202c, 0x3804202c, 0x28000a20, 0x28000a20},
  7354. + {0x0000a530, 0x3c06202c, 0x3c06202c, 0x2c000e20, 0x2c000e20},
  7355. + {0x0000a534, 0x4108202d, 0x4108202d, 0x30000e22, 0x30000e22},
  7356. + {0x0000a538, 0x4506402d, 0x4506402d, 0x34000e24, 0x34000e24},
  7357. + {0x0000a53c, 0x4906222d, 0x4906222d, 0x38001640, 0x38001640},
  7358. + {0x0000a540, 0x4d062231, 0x4d062231, 0x3c001660, 0x3c001660},
  7359. + {0x0000a544, 0x50082231, 0x50082231, 0x3f001861, 0x3f001861},
  7360. + {0x0000a548, 0x5608422e, 0x5608422e, 0x43001a81, 0x43001a81},
  7361. + {0x0000a54c, 0x5e08442e, 0x5e08442e, 0x47001a83, 0x47001a83},
  7362. + {0x0000a550, 0x620a4431, 0x620a4431, 0x4a001c84, 0x4a001c84},
  7363. + {0x0000a554, 0x640a4432, 0x640a4432, 0x4e001ce3, 0x4e001ce3},
  7364. + {0x0000a558, 0x680a4434, 0x680a4434, 0x52001ce5, 0x52001ce5},
  7365. + {0x0000a55c, 0x6c0a6434, 0x6c0a6434, 0x56001ce9, 0x56001ce9},
  7366. + {0x0000a560, 0x6f0a6633, 0x6f0a6633, 0x5a001ceb, 0x5a001ceb},
  7367. + {0x0000a564, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
  7368. + {0x0000a568, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
  7369. + {0x0000a56c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
  7370. + {0x0000a570, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
  7371. + {0x0000a574, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
  7372. + {0x0000a578, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
  7373. + {0x0000a57c, 0x730c6634, 0x730c6634, 0x5d001eec, 0x5d001eec},
  7374. + {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
  7375. + {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
  7376. + {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
  7377. + {0x0000a58c, 0x10800023, 0x10800023, 0x0b800200, 0x0b800200},
  7378. + {0x0000a590, 0x15800028, 0x15800028, 0x0f800202, 0x0f800202},
  7379. + {0x0000a594, 0x1b80002b, 0x1b80002b, 0x12800400, 0x12800400},
  7380. + {0x0000a598, 0x1f820028, 0x1f820028, 0x16800402, 0x16800402},
  7381. + {0x0000a59c, 0x2582002b, 0x2582002b, 0x19800404, 0x19800404},
  7382. + {0x0000a5a0, 0x2a84002a, 0x2a84002a, 0x1c800603, 0x1c800603},
  7383. + {0x0000a5a4, 0x2e86002a, 0x2e86002a, 0x21800a02, 0x21800a02},
  7384. + {0x0000a5a8, 0x3382202d, 0x3382202d, 0x25800a04, 0x25800a04},
  7385. + {0x0000a5ac, 0x3884202c, 0x3884202c, 0x28800a20, 0x28800a20},
  7386. + {0x0000a5b0, 0x3c86202c, 0x3c86202c, 0x2c800e20, 0x2c800e20},
  7387. + {0x0000a5b4, 0x4188202d, 0x4188202d, 0x30800e22, 0x30800e22},
  7388. + {0x0000a5b8, 0x4586402d, 0x4586402d, 0x34800e24, 0x34800e24},
  7389. + {0x0000a5bc, 0x4986222d, 0x4986222d, 0x38801640, 0x38801640},
  7390. + {0x0000a5c0, 0x4d862231, 0x4d862231, 0x3c801660, 0x3c801660},
  7391. + {0x0000a5c4, 0x50882231, 0x50882231, 0x3f801861, 0x3f801861},
  7392. + {0x0000a5c8, 0x5688422e, 0x5688422e, 0x43801a81, 0x43801a81},
  7393. + {0x0000a5cc, 0x5a88442e, 0x5a88442e, 0x47801a83, 0x47801a83},
  7394. + {0x0000a5d0, 0x5e8a4431, 0x5e8a4431, 0x4a801c84, 0x4a801c84},
  7395. + {0x0000a5d4, 0x648a4432, 0x648a4432, 0x4e801ce3, 0x4e801ce3},
  7396. + {0x0000a5d8, 0x688a4434, 0x688a4434, 0x52801ce5, 0x52801ce5},
  7397. + {0x0000a5dc, 0x6c8a6434, 0x6c8a6434, 0x56801ce9, 0x56801ce9},
  7398. + {0x0000a5e0, 0x6f8a6633, 0x6f8a6633, 0x5a801ceb, 0x5a801ceb},
  7399. + {0x0000a5e4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
  7400. + {0x0000a5e8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
  7401. + {0x0000a5ec, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
  7402. + {0x0000a5f0, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
  7403. + {0x0000a5f4, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
  7404. + {0x0000a5f8, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
  7405. + {0x0000a5fc, 0x738c6634, 0x738c6634, 0x5d801eec, 0x5d801eec},
  7406. + {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  7407. + {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  7408. + {0x0000a608, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
  7409. + {0x0000a60c, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
  7410. + {0x0000a610, 0x01804601, 0x01804601, 0x00000000, 0x00000000},
  7411. + {0x0000a614, 0x01804601, 0x01804601, 0x01404000, 0x01404000},
  7412. + {0x0000a618, 0x01804601, 0x01804601, 0x01404501, 0x01404501},
  7413. + {0x0000a61c, 0x01804601, 0x01804601, 0x02008501, 0x02008501},
  7414. + {0x0000a620, 0x03408d02, 0x03408d02, 0x0280ca03, 0x0280ca03},
  7415. + {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
  7416. + {0x0000a628, 0x03410d04, 0x03410d04, 0x04014c04, 0x04014c04},
  7417. + {0x0000a62c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
  7418. + {0x0000a630, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
  7419. + {0x0000a634, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
  7420. + {0x0000a638, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
  7421. + {0x0000a63c, 0x03410d04, 0x03410d04, 0x04015005, 0x04015005},
  7422. + {0x0000b2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
  7423. + {0x0000b2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
  7424. + {0x0000b2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
  7425. + {0x0000b2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
  7426. + {0x0000c2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
  7427. + {0x0000c2e0, 0x000f0000, 0x000f0000, 0x03ccc584, 0x03ccc584},
  7428. + {0x0000c2e4, 0x03f00000, 0x03f00000, 0x03f0f800, 0x03f0f800},
  7429. + {0x0000c2e8, 0x00000000, 0x00000000, 0x03ff0000, 0x03ff0000},
  7430. + {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
  7431. + {0x00016048, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
  7432. + {0x00016068, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
  7433. + {0x00016288, 0x05a2040a, 0x05a2040a, 0x05a20408, 0x05a20408},
  7434. + {0x00016444, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
  7435. + {0x00016448, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
  7436. + {0x00016468, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
  7437. + {0x00016844, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
  7438. + {0x00016848, 0x65240001, 0x65240001, 0x66480001, 0x66480001},
  7439. + {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
  7440. +};
  7441. static const u32 ar9580_1p0_lowest_ob_db_tx_gain_table[][5] = {
  7442. /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  7443. @@ -414,8 +533,6 @@ static const u32 ar9580_1p0_lowest_ob_db
  7444. {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
  7445. };
  7446. -#define ar9580_1p0_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
  7447. -
  7448. static const u32 ar9580_1p0_mac_core[][2] = {
  7449. /* Addr allmodes */
  7450. {0x00000008, 0x00000000},
  7451. @@ -679,14 +796,6 @@ static const u32 ar9580_1p0_mixed_ob_db_
  7452. {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
  7453. };
  7454. -#define ar9580_1p0_wo_xlna_rx_gain_table ar9300Common_wo_xlna_rx_gain_table_2p2
  7455. -
  7456. -#define ar9580_1p0_soc_postamble ar9300_2p2_soc_postamble
  7457. -
  7458. -#define ar9580_1p0_high_ob_db_tx_gain_table ar9300Modes_high_ob_db_tx_gain_table_2p2
  7459. -
  7460. -#define ar9580_1p0_type5_tx_gain_table ar9300Modes_type5_tx_gain_table_2p2
  7461. -
  7462. static const u32 ar9580_1p0_type6_tx_gain_table[][5] = {
  7463. /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
  7464. {0x0000a2dc, 0x000cfff0, 0x000cfff0, 0x03aaa352, 0x03aaa352},
  7465. @@ -761,160 +870,264 @@ static const u32 ar9580_1p0_type6_tx_gai
  7466. {0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
  7467. };
  7468. -static const u32 ar9580_1p0_soc_preamble[][2] = {
  7469. - /* Addr allmodes */
  7470. - {0x000040a4, 0x00a0c1c9},
  7471. - {0x00007008, 0x00000000},
  7472. - {0x00007020, 0x00000000},
  7473. - {0x00007034, 0x00000002},
  7474. - {0x00007038, 0x000004c2},
  7475. - {0x00007048, 0x00000008},
  7476. -};
  7477. -
  7478. -#define ar9580_1p0_rx_gain_table ar9462_common_rx_gain_table_2p0
  7479. -
  7480. -static const u32 ar9580_1p0_radio_core[][2] = {
  7481. +static const u32 ar9580_1p0_rx_gain_table[][2] = {
  7482. /* Addr allmodes */
  7483. - {0x00016000, 0x36db6db6},
  7484. - {0x00016004, 0x6db6db40},
  7485. - {0x00016008, 0x73f00000},
  7486. - {0x0001600c, 0x00000000},
  7487. - {0x00016040, 0x7f80fff8},
  7488. - {0x0001604c, 0x76d005b5},
  7489. - {0x00016050, 0x556cf031},
  7490. - {0x00016054, 0x13449440},
  7491. - {0x00016058, 0x0c51c92c},
  7492. - {0x0001605c, 0x3db7fffc},
  7493. - {0x00016060, 0xfffffffc},
  7494. - {0x00016064, 0x000f0278},
  7495. - {0x0001606c, 0x6db60000},
  7496. - {0x00016080, 0x00000000},
  7497. - {0x00016084, 0x0e48048c},
  7498. - {0x00016088, 0x54214514},
  7499. - {0x0001608c, 0x119f481e},
  7500. - {0x00016090, 0x24926490},
  7501. - {0x00016098, 0xd2888888},
  7502. - {0x000160a0, 0x0a108ffe},
  7503. - {0x000160a4, 0x812fc370},
  7504. - {0x000160a8, 0x423c8000},
  7505. - {0x000160b4, 0x92480080},
  7506. - {0x000160c0, 0x00adb6d0},
  7507. - {0x000160c4, 0x6db6db60},
  7508. - {0x000160c8, 0x6db6db6c},
  7509. - {0x000160cc, 0x01e6c000},
  7510. - {0x00016100, 0x3fffbe01},
  7511. - {0x00016104, 0xfff80000},
  7512. - {0x00016108, 0x00080010},
  7513. - {0x00016144, 0x02084080},
  7514. - {0x00016148, 0x00000000},
  7515. - {0x00016280, 0x058a0001},
  7516. - {0x00016284, 0x3d840208},
  7517. - {0x00016288, 0x05a20408},
  7518. - {0x0001628c, 0x00038c07},
  7519. - {0x00016290, 0x00000004},
  7520. - {0x00016294, 0x458aa14f},
  7521. - {0x00016380, 0x00000000},
  7522. - {0x00016384, 0x00000000},
  7523. - {0x00016388, 0x00800700},
  7524. - {0x0001638c, 0x00800700},
  7525. - {0x00016390, 0x00800700},
  7526. - {0x00016394, 0x00000000},
  7527. - {0x00016398, 0x00000000},
  7528. - {0x0001639c, 0x00000000},
  7529. - {0x000163a0, 0x00000001},
  7530. - {0x000163a4, 0x00000001},
  7531. - {0x000163a8, 0x00000000},
  7532. - {0x000163ac, 0x00000000},
  7533. - {0x000163b0, 0x00000000},
  7534. - {0x000163b4, 0x00000000},
  7535. - {0x000163b8, 0x00000000},
  7536. - {0x000163bc, 0x00000000},
  7537. - {0x000163c0, 0x000000a0},
  7538. - {0x000163c4, 0x000c0000},
  7539. - {0x000163c8, 0x14021402},
  7540. - {0x000163cc, 0x00001402},
  7541. - {0x000163d0, 0x00000000},
  7542. - {0x000163d4, 0x00000000},
  7543. - {0x00016400, 0x36db6db6},
  7544. - {0x00016404, 0x6db6db40},
  7545. - {0x00016408, 0x73f00000},
  7546. - {0x0001640c, 0x00000000},
  7547. - {0x00016440, 0x7f80fff8},
  7548. - {0x0001644c, 0x76d005b5},
  7549. - {0x00016450, 0x556cf031},
  7550. - {0x00016454, 0x13449440},
  7551. - {0x00016458, 0x0c51c92c},
  7552. - {0x0001645c, 0x3db7fffc},
  7553. - {0x00016460, 0xfffffffc},
  7554. - {0x00016464, 0x000f0278},
  7555. - {0x0001646c, 0x6db60000},
  7556. - {0x00016500, 0x3fffbe01},
  7557. - {0x00016504, 0xfff80000},
  7558. - {0x00016508, 0x00080010},
  7559. - {0x00016544, 0x02084080},
  7560. - {0x00016548, 0x00000000},
  7561. - {0x00016780, 0x00000000},
  7562. - {0x00016784, 0x00000000},
  7563. - {0x00016788, 0x00800700},
  7564. - {0x0001678c, 0x00800700},
  7565. - {0x00016790, 0x00800700},
  7566. - {0x00016794, 0x00000000},
  7567. - {0x00016798, 0x00000000},
  7568. - {0x0001679c, 0x00000000},
  7569. - {0x000167a0, 0x00000001},
  7570. - {0x000167a4, 0x00000001},
  7571. - {0x000167a8, 0x00000000},
  7572. - {0x000167ac, 0x00000000},
  7573. - {0x000167b0, 0x00000000},
  7574. - {0x000167b4, 0x00000000},
  7575. - {0x000167b8, 0x00000000},
  7576. - {0x000167bc, 0x00000000},
  7577. - {0x000167c0, 0x000000a0},
  7578. - {0x000167c4, 0x000c0000},
  7579. - {0x000167c8, 0x14021402},
  7580. - {0x000167cc, 0x00001402},
  7581. - {0x000167d0, 0x00000000},
  7582. - {0x000167d4, 0x00000000},
  7583. - {0x00016800, 0x36db6db6},
  7584. - {0x00016804, 0x6db6db40},
  7585. - {0x00016808, 0x73f00000},
  7586. - {0x0001680c, 0x00000000},
  7587. - {0x00016840, 0x7f80fff8},
  7588. - {0x0001684c, 0x76d005b5},
  7589. - {0x00016850, 0x556cf031},
  7590. - {0x00016854, 0x13449440},
  7591. - {0x00016858, 0x0c51c92c},
  7592. - {0x0001685c, 0x3db7fffc},
  7593. - {0x00016860, 0xfffffffc},
  7594. - {0x00016864, 0x000f0278},
  7595. - {0x0001686c, 0x6db60000},
  7596. - {0x00016900, 0x3fffbe01},
  7597. - {0x00016904, 0xfff80000},
  7598. - {0x00016908, 0x00080010},
  7599. - {0x00016944, 0x02084080},
  7600. - {0x00016948, 0x00000000},
  7601. - {0x00016b80, 0x00000000},
  7602. - {0x00016b84, 0x00000000},
  7603. - {0x00016b88, 0x00800700},
  7604. - {0x00016b8c, 0x00800700},
  7605. - {0x00016b90, 0x00800700},
  7606. - {0x00016b94, 0x00000000},
  7607. - {0x00016b98, 0x00000000},
  7608. - {0x00016b9c, 0x00000000},
  7609. - {0x00016ba0, 0x00000001},
  7610. - {0x00016ba4, 0x00000001},
  7611. - {0x00016ba8, 0x00000000},
  7612. - {0x00016bac, 0x00000000},
  7613. - {0x00016bb0, 0x00000000},
  7614. - {0x00016bb4, 0x00000000},
  7615. - {0x00016bb8, 0x00000000},
  7616. - {0x00016bbc, 0x00000000},
  7617. - {0x00016bc0, 0x000000a0},
  7618. - {0x00016bc4, 0x000c0000},
  7619. - {0x00016bc8, 0x14021402},
  7620. - {0x00016bcc, 0x00001402},
  7621. - {0x00016bd0, 0x00000000},
  7622. - {0x00016bd4, 0x00000000},
  7623. + {0x0000a000, 0x00010000},
  7624. + {0x0000a004, 0x00030002},
  7625. + {0x0000a008, 0x00050004},
  7626. + {0x0000a00c, 0x00810080},
  7627. + {0x0000a010, 0x00830082},
  7628. + {0x0000a014, 0x01810180},
  7629. + {0x0000a018, 0x01830182},
  7630. + {0x0000a01c, 0x01850184},
  7631. + {0x0000a020, 0x01890188},
  7632. + {0x0000a024, 0x018b018a},
  7633. + {0x0000a028, 0x018d018c},
  7634. + {0x0000a02c, 0x01910190},
  7635. + {0x0000a030, 0x01930192},
  7636. + {0x0000a034, 0x01950194},
  7637. + {0x0000a038, 0x038a0196},
  7638. + {0x0000a03c, 0x038c038b},
  7639. + {0x0000a040, 0x0390038d},
  7640. + {0x0000a044, 0x03920391},
  7641. + {0x0000a048, 0x03940393},
  7642. + {0x0000a04c, 0x03960395},
  7643. + {0x0000a050, 0x00000000},
  7644. + {0x0000a054, 0x00000000},
  7645. + {0x0000a058, 0x00000000},
  7646. + {0x0000a05c, 0x00000000},
  7647. + {0x0000a060, 0x00000000},
  7648. + {0x0000a064, 0x00000000},
  7649. + {0x0000a068, 0x00000000},
  7650. + {0x0000a06c, 0x00000000},
  7651. + {0x0000a070, 0x00000000},
  7652. + {0x0000a074, 0x00000000},
  7653. + {0x0000a078, 0x00000000},
  7654. + {0x0000a07c, 0x00000000},
  7655. + {0x0000a080, 0x22222229},
  7656. + {0x0000a084, 0x1d1d1d1d},
  7657. + {0x0000a088, 0x1d1d1d1d},
  7658. + {0x0000a08c, 0x1d1d1d1d},
  7659. + {0x0000a090, 0x171d1d1d},
  7660. + {0x0000a094, 0x11111717},
  7661. + {0x0000a098, 0x00030311},
  7662. + {0x0000a09c, 0x00000000},
  7663. + {0x0000a0a0, 0x00000000},
  7664. + {0x0000a0a4, 0x00000000},
  7665. + {0x0000a0a8, 0x00000000},
  7666. + {0x0000a0ac, 0x00000000},
  7667. + {0x0000a0b0, 0x00000000},
  7668. + {0x0000a0b4, 0x00000000},
  7669. + {0x0000a0b8, 0x00000000},
  7670. + {0x0000a0bc, 0x00000000},
  7671. + {0x0000a0c0, 0x001f0000},
  7672. + {0x0000a0c4, 0x01000101},
  7673. + {0x0000a0c8, 0x011e011f},
  7674. + {0x0000a0cc, 0x011c011d},
  7675. + {0x0000a0d0, 0x02030204},
  7676. + {0x0000a0d4, 0x02010202},
  7677. + {0x0000a0d8, 0x021f0200},
  7678. + {0x0000a0dc, 0x0302021e},
  7679. + {0x0000a0e0, 0x03000301},
  7680. + {0x0000a0e4, 0x031e031f},
  7681. + {0x0000a0e8, 0x0402031d},
  7682. + {0x0000a0ec, 0x04000401},
  7683. + {0x0000a0f0, 0x041e041f},
  7684. + {0x0000a0f4, 0x0502041d},
  7685. + {0x0000a0f8, 0x05000501},
  7686. + {0x0000a0fc, 0x051e051f},
  7687. + {0x0000a100, 0x06010602},
  7688. + {0x0000a104, 0x061f0600},
  7689. + {0x0000a108, 0x061d061e},
  7690. + {0x0000a10c, 0x07020703},
  7691. + {0x0000a110, 0x07000701},
  7692. + {0x0000a114, 0x00000000},
  7693. + {0x0000a118, 0x00000000},
  7694. + {0x0000a11c, 0x00000000},
  7695. + {0x0000a120, 0x00000000},
  7696. + {0x0000a124, 0x00000000},
  7697. + {0x0000a128, 0x00000000},
  7698. + {0x0000a12c, 0x00000000},
  7699. + {0x0000a130, 0x00000000},
  7700. + {0x0000a134, 0x00000000},
  7701. + {0x0000a138, 0x00000000},
  7702. + {0x0000a13c, 0x00000000},
  7703. + {0x0000a140, 0x001f0000},
  7704. + {0x0000a144, 0x01000101},
  7705. + {0x0000a148, 0x011e011f},
  7706. + {0x0000a14c, 0x011c011d},
  7707. + {0x0000a150, 0x02030204},
  7708. + {0x0000a154, 0x02010202},
  7709. + {0x0000a158, 0x021f0200},
  7710. + {0x0000a15c, 0x0302021e},
  7711. + {0x0000a160, 0x03000301},
  7712. + {0x0000a164, 0x031e031f},
  7713. + {0x0000a168, 0x0402031d},
  7714. + {0x0000a16c, 0x04000401},
  7715. + {0x0000a170, 0x041e041f},
  7716. + {0x0000a174, 0x0502041d},
  7717. + {0x0000a178, 0x05000501},
  7718. + {0x0000a17c, 0x051e051f},
  7719. + {0x0000a180, 0x06010602},
  7720. + {0x0000a184, 0x061f0600},
  7721. + {0x0000a188, 0x061d061e},
  7722. + {0x0000a18c, 0x07020703},
  7723. + {0x0000a190, 0x07000701},
  7724. + {0x0000a194, 0x00000000},
  7725. + {0x0000a198, 0x00000000},
  7726. + {0x0000a19c, 0x00000000},
  7727. + {0x0000a1a0, 0x00000000},
  7728. + {0x0000a1a4, 0x00000000},
  7729. + {0x0000a1a8, 0x00000000},
  7730. + {0x0000a1ac, 0x00000000},
  7731. + {0x0000a1b0, 0x00000000},
  7732. + {0x0000a1b4, 0x00000000},
  7733. + {0x0000a1b8, 0x00000000},
  7734. + {0x0000a1bc, 0x00000000},
  7735. + {0x0000a1c0, 0x00000000},
  7736. + {0x0000a1c4, 0x00000000},
  7737. + {0x0000a1c8, 0x00000000},
  7738. + {0x0000a1cc, 0x00000000},
  7739. + {0x0000a1d0, 0x00000000},
  7740. + {0x0000a1d4, 0x00000000},
  7741. + {0x0000a1d8, 0x00000000},
  7742. + {0x0000a1dc, 0x00000000},
  7743. + {0x0000a1e0, 0x00000000},
  7744. + {0x0000a1e4, 0x00000000},
  7745. + {0x0000a1e8, 0x00000000},
  7746. + {0x0000a1ec, 0x00000000},
  7747. + {0x0000a1f0, 0x00000396},
  7748. + {0x0000a1f4, 0x00000396},
  7749. + {0x0000a1f8, 0x00000396},
  7750. + {0x0000a1fc, 0x00000196},
  7751. + {0x0000b000, 0x00010000},
  7752. + {0x0000b004, 0x00030002},
  7753. + {0x0000b008, 0x00050004},
  7754. + {0x0000b00c, 0x00810080},
  7755. + {0x0000b010, 0x00830082},
  7756. + {0x0000b014, 0x01810180},
  7757. + {0x0000b018, 0x01830182},
  7758. + {0x0000b01c, 0x01850184},
  7759. + {0x0000b020, 0x02810280},
  7760. + {0x0000b024, 0x02830282},
  7761. + {0x0000b028, 0x02850284},
  7762. + {0x0000b02c, 0x02890288},
  7763. + {0x0000b030, 0x028b028a},
  7764. + {0x0000b034, 0x0388028c},
  7765. + {0x0000b038, 0x038a0389},
  7766. + {0x0000b03c, 0x038c038b},
  7767. + {0x0000b040, 0x0390038d},
  7768. + {0x0000b044, 0x03920391},
  7769. + {0x0000b048, 0x03940393},
  7770. + {0x0000b04c, 0x03960395},
  7771. + {0x0000b050, 0x00000000},
  7772. + {0x0000b054, 0x00000000},
  7773. + {0x0000b058, 0x00000000},
  7774. + {0x0000b05c, 0x00000000},
  7775. + {0x0000b060, 0x00000000},
  7776. + {0x0000b064, 0x00000000},
  7777. + {0x0000b068, 0x00000000},
  7778. + {0x0000b06c, 0x00000000},
  7779. + {0x0000b070, 0x00000000},
  7780. + {0x0000b074, 0x00000000},
  7781. + {0x0000b078, 0x00000000},
  7782. + {0x0000b07c, 0x00000000},
  7783. + {0x0000b080, 0x23232323},
  7784. + {0x0000b084, 0x21232323},
  7785. + {0x0000b088, 0x19191c1e},
  7786. + {0x0000b08c, 0x12141417},
  7787. + {0x0000b090, 0x07070e0e},
  7788. + {0x0000b094, 0x03030305},
  7789. + {0x0000b098, 0x00000003},
  7790. + {0x0000b09c, 0x00000000},
  7791. + {0x0000b0a0, 0x00000000},
  7792. + {0x0000b0a4, 0x00000000},
  7793. + {0x0000b0a8, 0x00000000},
  7794. + {0x0000b0ac, 0x00000000},
  7795. + {0x0000b0b0, 0x00000000},
  7796. + {0x0000b0b4, 0x00000000},
  7797. + {0x0000b0b8, 0x00000000},
  7798. + {0x0000b0bc, 0x00000000},
  7799. + {0x0000b0c0, 0x003f0020},
  7800. + {0x0000b0c4, 0x00400041},
  7801. + {0x0000b0c8, 0x0140005f},
  7802. + {0x0000b0cc, 0x0160015f},
  7803. + {0x0000b0d0, 0x017e017f},
  7804. + {0x0000b0d4, 0x02410242},
  7805. + {0x0000b0d8, 0x025f0240},
  7806. + {0x0000b0dc, 0x027f0260},
  7807. + {0x0000b0e0, 0x0341027e},
  7808. + {0x0000b0e4, 0x035f0340},
  7809. + {0x0000b0e8, 0x037f0360},
  7810. + {0x0000b0ec, 0x04400441},
  7811. + {0x0000b0f0, 0x0460045f},
  7812. + {0x0000b0f4, 0x0541047f},
  7813. + {0x0000b0f8, 0x055f0540},
  7814. + {0x0000b0fc, 0x057f0560},
  7815. + {0x0000b100, 0x06400641},
  7816. + {0x0000b104, 0x0660065f},
  7817. + {0x0000b108, 0x067e067f},
  7818. + {0x0000b10c, 0x07410742},
  7819. + {0x0000b110, 0x075f0740},
  7820. + {0x0000b114, 0x077f0760},
  7821. + {0x0000b118, 0x07800781},
  7822. + {0x0000b11c, 0x07a0079f},
  7823. + {0x0000b120, 0x07c107bf},
  7824. + {0x0000b124, 0x000007c0},
  7825. + {0x0000b128, 0x00000000},
  7826. + {0x0000b12c, 0x00000000},
  7827. + {0x0000b130, 0x00000000},
  7828. + {0x0000b134, 0x00000000},
  7829. + {0x0000b138, 0x00000000},
  7830. + {0x0000b13c, 0x00000000},
  7831. + {0x0000b140, 0x003f0020},
  7832. + {0x0000b144, 0x00400041},
  7833. + {0x0000b148, 0x0140005f},
  7834. + {0x0000b14c, 0x0160015f},
  7835. + {0x0000b150, 0x017e017f},
  7836. + {0x0000b154, 0x02410242},
  7837. + {0x0000b158, 0x025f0240},
  7838. + {0x0000b15c, 0x027f0260},
  7839. + {0x0000b160, 0x0341027e},
  7840. + {0x0000b164, 0x035f0340},
  7841. + {0x0000b168, 0x037f0360},
  7842. + {0x0000b16c, 0x04400441},
  7843. + {0x0000b170, 0x0460045f},
  7844. + {0x0000b174, 0x0541047f},
  7845. + {0x0000b178, 0x055f0540},
  7846. + {0x0000b17c, 0x057f0560},
  7847. + {0x0000b180, 0x06400641},
  7848. + {0x0000b184, 0x0660065f},
  7849. + {0x0000b188, 0x067e067f},
  7850. + {0x0000b18c, 0x07410742},
  7851. + {0x0000b190, 0x075f0740},
  7852. + {0x0000b194, 0x077f0760},
  7853. + {0x0000b198, 0x07800781},
  7854. + {0x0000b19c, 0x07a0079f},
  7855. + {0x0000b1a0, 0x07c107bf},
  7856. + {0x0000b1a4, 0x000007c0},
  7857. + {0x0000b1a8, 0x00000000},
  7858. + {0x0000b1ac, 0x00000000},
  7859. + {0x0000b1b0, 0x00000000},
  7860. + {0x0000b1b4, 0x00000000},
  7861. + {0x0000b1b8, 0x00000000},
  7862. + {0x0000b1bc, 0x00000000},
  7863. + {0x0000b1c0, 0x00000000},
  7864. + {0x0000b1c4, 0x00000000},
  7865. + {0x0000b1c8, 0x00000000},
  7866. + {0x0000b1cc, 0x00000000},
  7867. + {0x0000b1d0, 0x00000000},
  7868. + {0x0000b1d4, 0x00000000},
  7869. + {0x0000b1d8, 0x00000000},
  7870. + {0x0000b1dc, 0x00000000},
  7871. + {0x0000b1e0, 0x00000000},
  7872. + {0x0000b1e4, 0x00000000},
  7873. + {0x0000b1e8, 0x00000000},
  7874. + {0x0000b1ec, 0x00000000},
  7875. + {0x0000b1f0, 0x00000396},
  7876. + {0x0000b1f4, 0x00000396},
  7877. + {0x0000b1f8, 0x00000396},
  7878. + {0x0000b1fc, 0x00000196},
  7879. };
  7880. static const u32 ar9580_1p0_baseband_postamble[][5] = {
  7881. @@ -956,7 +1169,7 @@ static const u32 ar9580_1p0_baseband_pos
  7882. {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
  7883. {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
  7884. {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
  7885. - {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982},
  7886. + {0x0000a2d0, 0x00041983, 0x00041983, 0x00041981, 0x00041982},
  7887. {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
  7888. {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
  7889. {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
  7890. --- a/drivers/net/wireless/ath/ath9k/reg.h
  7891. +++ b/drivers/net/wireless/ath/ath9k/reg.h
  7892. @@ -809,6 +809,8 @@
  7893. #define AR_SREV_REVISION_9462_21 3
  7894. #define AR_SREV_VERSION_9565 0x2C0
  7895. #define AR_SREV_REVISION_9565_10 0
  7896. +#define AR_SREV_REVISION_9565_101 1
  7897. +#define AR_SREV_REVISION_9565_11 2
  7898. #define AR_SREV_VERSION_9550 0x400
  7899. #define AR_SREV_5416(_ah) \
  7900. @@ -927,10 +929,18 @@
  7901. #define AR_SREV_9565(_ah) \
  7902. (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565))
  7903. -
  7904. #define AR_SREV_9565_10(_ah) \
  7905. (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
  7906. ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_10))
  7907. +#define AR_SREV_9565_101(_ah) \
  7908. + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
  7909. + ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_101))
  7910. +#define AR_SREV_9565_11(_ah) \
  7911. + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
  7912. + ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_11))
  7913. +#define AR_SREV_9565_11_OR_LATER(_ah) \
  7914. + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \
  7915. + ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9565_11))
  7916. #define AR_SREV_9550(_ah) \
  7917. (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9550))